Identification wafer

Abstract

The invention relates to an identification wafer. The identification wafer is arranged on a flexible circuit board and is electrically connected to a printer. The device comprises a plurality of memory units, the memory units are arranged to form an array structure, the type of each memory unit in the array structure can be selected from a first transistor or a third transistor, and by configuring the pattern and state of the array structure, the ink cartridge provided with the identification wafer can be matched with a printer.

Description

Technical Field

[0001] The present invention relates to an identification chip, and more specifically, to an identification chip which can be reused, will not be disturbed by heat, and can increase environmental protection performance by providing an identification chip and electrically connecting it to a printer. Background Art

[0002] Inkjet printing technology, commonly known as "Inkjet Printing", is a widely used printing technology. Its history can be traced back to the 1950s when the British company Hewlett-Packard invented inkjet printing technology. Since then, inkjet printing technology has developed rapidly, making inkjet printers the mainstream technology for home and commercial printing. Inkjet printers have many advantages, including: low cost, especially economic advantages for home and small business use; high printing quality, which can provide high-resolution and high-quality images, especially in photos or pictures; convenient to use, inkjet printers are easy to install, and most inkjet printers can print through computers or mobile devices. When combined with the recent rise of multi-in-one functions (including fax, photocopying, scanning) of business machines, it can quickly expand the flexibility of paperwork in the office.

[0003] The inkjet head identification circuit in the inkjet printer is an important component in the inkjet printing technology. Since each type of inkjet printer needs to be matched with the corresponding inkjet head, and each inkjet head has its own special specifications, including: structure, ink used, number of nozzles, and control circuit characteristics, it is necessary to match a compatible printing system to operate with the inkjet printer through the inkjet head identification circuit. Specifically, the inkjet head identification circuit includes a fuse, a transistor reverse fuse, and related circuit components, which are used to store information including but not limited to the ink cartridge serial number, ink type, ink capacity, ink color, and matching information between the inkjet head and the inkjet printer to ensure printing quality and efficiency.

[0004] See also Figure 1A and Figure 1B, which describes the matching and control method between the ink cartridge 10 and the printer 30 in the prior art: the ink cartridge 10 includes an inkjet head chip 100A, and the inkjet head chip 100A stores the above-mentioned information such as the ink cartridge serial number, ink type, and matching information between the inkjet head and the printer. The general inkjet head chip 100A further includes a jet control circuit 110 and an inkjet head identification circuit 120, which are respectively coupled to the inkjet control terminal 320 and the identification signal terminal 310 on the printer 30. Among them, after receiving the ejection signal sent by the inkjet control terminal 320 of the printer 30, the above-mentioned jet control circuit 110 will activate the corresponding jet on the ink cartridge 10 to eject ink drops, and the inkjet head identification circuit 120 mainly provides an inkjet head identification signal to the identification signal terminal 310 of the printer 30, such as the above-mentioned ink cartridge serial number, ink type, matching information between the inkjet head and the printer, ink content, etc.

[0005] However, the defect of the prior art is that when the inkjet head chip 100A controls printing, it needs to heat the ink, which makes its structure inherently have a relatively high chip temperature and a more drastic temperature change, such as Figure 1C As shown in the conventional method of integrating the inkjet head identification circuit 120 into the inkjet head chip 100A, the chances of the components in the inkjet head identification circuit 120 malfunctioning due to the temperature factors mentioned above are increased, thereby affecting the stability of the identification signal during printing, resulting in lower reliability of the conventional technology. Alternatively, further reinforcement design can only be performed in terms of materials or structure, resulting in a choice between device reliability and manufacturing cost. Furthermore, since the ink cartridge 10 in the prior art is used up, the printer 30 will immediately burn the inkjet head chip 100A according to the ink content recorded in the inkjet head identification circuit 120 to permanently stop the operation of the ink cartridge 10, this means that the information that can be recorded by the inkjet head chip 100A in the prior art is disposable, so that the ink cartridge 10 currently on the market can only be used once. When the ink is exhausted, the ink cartridge 10 will be permanently unusable. However, considering that the mechanical structure of the ink cartridge 10 is still intact, and with the current environmental protection regulations becoming increasingly stringent, the environmental protection awareness of market consumers and the general public is gradually rising, and the cost of using economic resources of enterprises, the practice of the prior art will cause waste in the use of the ink cartridge 10. Therefore, in the current market, there is still a need to improve the existing ink cartridge 10, or the matching control method between the ink cartridge 10 and the printer 30, so that the ink cartridge 10 can be reused after being filled with ink to meet the purpose of environmental protection and economy. Summary of the invention

[0006] Based on the above reasons, the present invention proposes an identification chip, by electrically connecting an independent identification chip to the inkjet head chip located on the outer layer of the ink cartridge, that is, the inkjet head chip electrically connected to the flexible circuit board on the ink cartridge or the outer shell of the ink cartridge, through the identification signal provided by the identification chip, the inkjet head identification signal provided by the original inkjet head chip is optimized, so that the ink cartridge connected to the identification chip can continue to provide the printer with the printing needs after filling with new ink, instead of being a disposable consumable in the traditional way. In addition, since the identification chip is an independent component, it is more flexible in the location of the setting and is less likely to be affected by the heat energy of the inkjet head chip during operation, so that the identification chip can improve reliability while taking into account economic costs at the same time. Among them, in the memory unit of the identification chip, in order to increase the diversity of the circuit element composition in the memory unit, and at the same time make the memory unit have a modifiable function, and in order to make the information stored in the memory unit architecture in the identification chip, such as the ink cartridge serial number, identification code (Identification Code), ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, ink cartridge capacity change (ink capacity), the number of times the ink cartridge is used on the machine, etc., more detailed and complete, it can also increase the difficulty of reverse engineering to imitate the identification chip, increase the reuse of the ink cartridge, and reduce the cost spent by the enterprise to manufacture the ink cartridge, but can maintain the effectiveness of the intellectual property protection in the ink cartridge. Therefore, in order to achieve the above purpose, the present invention explores the circuit architecture in the above identification chip, and its detailed technical solution will be described in detail as follows.

[0007] The present invention proposes an identification chip, comprising the following elements: the identification chip provides an identification signal to match a printer; wherein the identification chip has a plurality of memory units, the plurality of memory units form an array structure, and further include a first transistor and a third transistor, that is, the main type of each single memory unit can be selected from the first transistor or the third transistor. In the present invention, by configuring the types and quantities of the plurality of memory units in the array structure in the identification chip, that is, the states of the first transistor and the third transistor, when reading the identification signal of the memory unit, the information recorded in the identification chip can be judged. In the embodiment of the present invention, the first transistor is a MOSFET Anti-Fuse, the third transistor is an EPROM, and the first transistor and the third transistor are generated on the same identification chip.

[0008] According to the present invention, the first transistor can be a metal oxide semiconductor field effect transistor (MOSFET), and can be selected from an N-type metal oxide semiconductor field effect transistor (NMOS) or a P-type metal oxide semiconductor field effect transistor (PMOS) according to the application requirements. In addition, the third transistor is an erasable programmable read only memory (EPROM).

[0009] According to the present invention, each memory unit further includes an identification signal terminal, a data terminal, and a second transistor, wherein the identification signal terminal is connected to the first transistor or the third transistor, the data terminal is connected to the gate of the second transistor, and the first transistor and the third transistor are connected to the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The detailed description of the present invention and the schematic diagram of the embodiments described below should enable a more complete understanding of the present invention; however, it should be understood that this is only a reference for understanding the application of the present invention, rather than limiting the present invention to a specific embodiment.

[0011] Figure 1A The structure of a known ink cartridge and the arrangement of an inkjet head chip are described.

[0012] Figure 1B The circuit architecture of the conventional printer connected to the inkjet head chip is described.

[0013] Figure 1C The circuit architecture of a conventional printer connected to an inkjet head chip is described.

[0014] Figure 2A A first setting method for connecting an identification chip to an ink cartridge is described.

[0015] Figure 2B A second method of connecting an identification chip to an ink cartridge is described.

[0016] Figure 2C A third configuration method for connecting an identification chip to an ink cartridge is described.

[0017] Figure 2D Describes how to configure the identification chip.

[0018] Figure 2E Describes the circuit of the printer and inkjet head chip, and the first circuit architecture after connecting the identification chip.

[0019] Figure 2F Describes the circuits of the printer and inkjet head chip, and the second and third circuit architectures after connecting the identification chip.

[0020] Figure 3AThe structure in which the identification chip is disposed on the flexible printed circuit board is described.

[0021] Figure 3B The invention describes an array structure formed by memory cells contained in an identification chip identification circuit to record information in an inkjet head.

[0022] Figure 4A The circuit structure of one embodiment of the memory unit in the present invention is described.

[0023] Figure 4B The circuit structure of one embodiment of the memory unit in the present invention is described.

[0024] Figure 4C The circuit structure of one embodiment of the memory unit in the present invention is described.

[0025] Figure 4D The circuit structure of one embodiment of the memory unit in the present invention is described.

[0026] Figure 4E In one embodiment of the present invention, a third transistor is used in the circuit structure of the memory unit, that is, an EPROM state.

[0027] Figure 5A The cross-sectional structure of the N-type metal oxide semi-conductor field effect transistor before burning in the present invention is described.

[0028] Figure 5B The cross-sectional structure of the N-type metal oxide semi-conductor field effect transistor after burning in the present invention is described.

[0029] Figure 5C The cross-sectional structure of the P-type metal oxide semi-conductor field effect transistor before burning in the present invention is described.

[0030] Figure 5D The cross-sectional structure of the P-type metal oxide semi-conductor field effect transistor after burning in the present invention is described.

[0031] Figure 5E The cross-sectional structure of the EPROM in the present invention is described.

[0032] Fig. 6A The array structure composed of the first and third transistors in one embodiment of the memory unit of the present invention is described.

[0033] Figure 6B The array structure composed of the first and third transistors in another embodiment of the memory unit of the present invention is described.

[0034]

Explanation of symbols

[0035] 10: Ink cartridge

[0036] 100: Flexible circuit board

[0037] 100A: Inkjet head chip

[0038] 110: Spray point control circuit

[0039] 120: Inkjet head identification circuit

[0040] 200: Flexible printed circuit board

[0041] 210: Identification chip

[0042] 211: Memory Unit

[0043] 310, 211A: Identification signal terminal

[0044] 211B: Data terminal

[0045] 211C: The First Transistor

[0046] 211E: Second transistor

[0047] 211G: The third transistor

[0048] 30: Printer

[0049] 320: Inkjet control terminal

[0050] G: Gate

[0051] N: N type

[0052] P: P type

[0053] GOX: Gate Oxide

[0054] S: Source

[0055] D: Drain

[0056] PG: Polysilicon Gate

[0057] M1: Floating Gate

[0058] M2: Control grid

[0059] ILD: First Dielectric Layer

[0060] IMD: Second Dielectric Layer DETAILED DESCRIPTION

[0061] The present invention will be described in detail with preferred embodiments and viewpoints. The following description provides specific implementation details of the present invention so that the reader can thoroughly understand the implementation methods of these embodiments. However, those skilled in the art in this field must understand that the present invention can also be implemented without these details. In addition, the present invention can also be used and implemented by other specific embodiments. The various details described in this specification can also be applied based on different needs, and various modifications or changes can be made without departing from the spirit of the present invention. Therefore, the present invention will be described with preferred embodiments and viewpoints. Such descriptions are to explain the structure of the present invention and are only used for illustration rather than to limit the scope of the patent application of the present invention. The terms used in the following description will be interpreted in the broadest reasonable way so that they can be used together with the detailed description of a specific embodiment of the present invention. Those skilled in the art can adjust the structure of the present invention according to manufacturing or application requirements to meet the needs of the actual industry. Among them, in this specification, the first transistor mentioned can be referred to as MOS, and if the first transistor is a metal oxide semiconductor field effect transistor anti-fuse (MOSFET Anti-Fuse), it can also be referred to as MOS or MOS-Anti-Fuse in this specification. Similarly, if the third transistor is an erasable and programmable unique memory, it can be referred to as EPROM. In addition, in order to transmit a signal for identification (ID), this specification provides identification signal terminals 310 and 211A in the printer 30 and the memory unit 211 respectively. Those skilled in the art can understand the current configuration of the identification signal terminals 310 and 211A through the context of the specification and the accompanying diagrams, so it is explained first.

[0062] See also Figure 2A , Figure 2E , Figure 3A and Figure 3BIn the first embodiment of the present invention, an identification chip 210 is proposed, which is arranged on a flexible circuit board 200. The flexible circuit board 200 is attached to and electrically connected to the inkjet head chip 100A in the flexible circuit board 100 located on the outer layer of the ink cartridge 10, wherein the identification chip 210 includes the following elements: a plurality of memory units 211, the plurality of memory units 211 are arranged in the identification chip 210 to form an array structure, the plurality of memory units 211 include a first transistor 211C and a third transistor 211G, and the states of the first transistor 211C and the third transistor 211G are configured in the order and quantity in the identification chip 210 to record information, and the ink cartridge 10 is matched with the printer 30 by transmitting an identification signal. In the embodiment of the present invention, the first transistor 211C is a MOSFET Anti-Fuse, the third transistor 211G is an erasable and programmable unique memory (EPROM), and the first transistor 211C and the third transistor 211G are generated on the same identification chip 210. The array structure formed by the memory unit 211 provides but is not limited to the information such as the ink cartridge serial number, identification code, ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, ink cartridge capacity change (ink capacity), and the number of times the ink cartridge is used on the printer, so that the printer 30 can identify the model and type of the inkjet head in the ink cartridge 10.

[0063] Please also see Figure 2A and Figure 2EAccording to the above embodiment of the present invention, the flexible printed circuit board 200 is arranged and attached to the flexible printed circuit board 100, and has an identification chip 210. When the ink cartridge 10 is installed in the printer 30, the identification chip 210 is coupled to the identification signal terminal 310 and the inkjet control terminal 320 in the printer 30 in terms of circuit structure. The dot control circuit 110 and the inkjet head identification circuit 120 in the inkjet head chip 100A are coupled to the inkjet control terminal 320 in the printer 30 to transmit the ejection signal. When the identification chip 210 is connected to the printer 30, the ejection signal of the inkjet head chip 100A will be maintained or optimized. At the same time, the identification signal provided by the identification chip 210 will replace or optimize the original inkjet head identification signal. In this way, although the inkjet head chip 100A is burned by the printer 30 due to the exhaustion of ink during the previous use, the ink cartridge 10 that was originally only disposable and discarded can still transmit the identification signal to the identification signal terminal 310 after the ink cartridge 10 is filled with ink. The printer 30 transmits the inkjet signal to the jet control circuit 110 through the inkjet control terminal 320 according to the identification signal to restart the corresponding jet on the ink cartridge 10 to eject ink droplets, so that the ink cartridge 10 has the performance of being reused, thereby achieving the purpose of the present invention.

[0064] See also Figure 2B , Figure 2C , Figure 2D and Figure 2F According to the other two embodiments of the present invention, the identification chip 210 can also be attached to the flexible circuit board 100 of the ink cartridge 10 itself, or to the outer shell of the ink cartridge 10. When the ink cartridge 10 is installed in the printer 30, the identification chip 210 will be coupled to the identification signal terminal 310 and the inkjet control terminal 320 in the printer 30 in terms of circuit structure. The dot control circuit 110 in the inkjet head chip 100A is coupled to the inkjet control terminal 320 in the printer 30 to transmit the ejection signal. The advantage of such a setting is that the positions of the identification chip 210 and the inkjet head chip 100A are independent of each other, so that the heat energy generated by the inkjet head chip 100A during operation, or the temperature change during the control of inkjet, can be far away from the position of the identification chip 210, which can ensure that the identification chip 210 will not be affected by temperature changes during the transmission of the identification signal to the greatest extent, thereby achieving the purpose of improving the reliability of the device of the present invention.

[0065] According to one viewpoint of the present invention, the identification chip 210 proposed by the present invention can be modified and recorded for multiple times by repeated burning, wherein the MOSFET Anti-Fuse selected by the first transistor 211C mainly records the information that will not change in the identification chip 210, such as specification parameters, ink cartridge serial number, identification code, ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, or any combination of the above; on the other hand, the EPROM selected by the third transistor 211G has a different resistance value each time it is burned, and can be mainly used as a recording carrier of variable information, such as changes in the ink cartridge capacity (ink capacity) during printing, the number of times the ink cartridge is used on the machine, or any combination of the above. In the embodiment of the present invention, no matter whether the MOSFET Anti-Fuse and the EPROM have been burned or not, there is no difference in the appearance of the identification chip 210 before and after, and whether the identification chip 210 is read, burned or used, it must be combined with a specific software algorithm. From the perspective of intellectual property rights and industrial utilization, the information security attacker cannot forge the identification chip 210 using the present invention through reverse engineering due to the lack of information on whether the MOSFET Anti-Fuse and the EPROM have been burned, thereby achieving the purpose of enhancing information security, protecting the rights and interests of both consumers and manufacturers in the industry, and making the encryption function and the information that can be recorded more complete. It has the advantages of simple structure, easy cost control and the ability to reuse the ink cartridge 10.

[0066] Please continue to read Figure 4A , Figure 4B , Figure 4C ,as well as Figure 4D , wherein, in an embodiment of the present invention, Figure 4A , Figure 4B The first transistor 211C in is of P type, and Figure 4C , Figure 4D The first transistor 211C in is of N-type. In addition, Figure 4EThe third transistor 211G in the circuit structure of the memory unit 211 in one embodiment of the present invention is described as an EPROM. In addition, in the embodiment of the present invention, in order to provide the function of burning the first transistor 211C and the third transistor 211G, each memory unit 211 further includes an identification signal terminal 211A, a data terminal 211B, and a second transistor 211E. The identification signal terminal 211A transmits an identification potential and is connected to the first transistor 211C or the third transistor 211G in the memory unit 211 to control whether to burn or not burn the first transistor 211C or the third transistor 211G. In addition, the data terminal 211B transmits a data potential and is connected to the gate G of the second transistor 211E, and the first transistor 211C or the third transistor 211G is connected to the second transistor 211E. The memory unit 211 controls the output of the identification signal by adjusting the data potential and the identification potential. In some embodiments of the present invention, the first transistor 211C can be selected from a metal oxide semi-conductor field effect transistor (MOSFET), and can be selected from an N-type or a P-type. In addition, the third transistor 211G is an EPROM. The above-mentioned memory unit 211 can be selected from the type of the first transistor 211C or the third transistor 211G according to the needs of actual applications, and any combination of the above-mentioned types can be performed in the array structure formed by multiple memory units 211 to improve the flexibility of information recording.

[0067] See also Figure 5A , Figure 5B , Figure 5C , Figure 5D , which illustrates the states of the first transistor 211C when it is burned green and not burned in the memory unit 211. According to the different states, the memory unit 211 can output a binary digit identification signal. Figure 5A and Figure 5B In one embodiment of the present invention, it is described that the first transistor 211C uses an N-type metal oxide semi-conductor field effect transistor. Figure 5A In the embodiment, the lower end of the gate G of the first transistor 211C has a gate oxide layer GOX. When the identification potential provided by the identification signal terminal 211A is less than a breakdown potential, the structure of the gate oxide layer GOX is intact. If the data terminal 211B provides a high potential at this time, the second transistor 211E will be in a conducting state, and the identification signal terminal 211A will be read as a high resistance state in the memory unit 211, and the identification signal outputted shows that the memory unit 211 is in an unburned state. On the other hand, Figure 5BWhen the potential provided by the identification signal terminal 211A is greater than the breakdown potential, the structure of the gate oxide layer GOX collapses, causing the gate G to be connected to the substrate of the first transistor 211C and causing irreversible damage. This will cause the identification signal terminal 211A to be read out as a low resistance state in the memory unit 211, and the output identification signal shows that the memory unit 211 is in a burned state, thereby achieving the purpose of outputting a binary identification signal. It should be noted that in the present invention, the above-mentioned binary identification signal is not limited to 0 and 1 corresponding to low resistance or high resistance, and it can also be 1 and 0 corresponding to low resistance or high resistance respectively, which can be set, changed or modified according to the actual application. In addition, Figure 5C , Figure 5D In it is described that the first transistor 211C can also be a P-type metal oxide semi-field effect transistor, and the gate oxide layer GOX can be controlled to collapse by controlling the potential provided by the identification signal terminal 211A, thereby burning / not burning the memory unit 211 to achieve the purpose of controlling the output of the binary identification signal. Since its burning / not burning mechanism is the same as that of the N-type metal oxide semi-field effect transistor, it will not be repeated below.

[0068] See also Figure 5E, which illustrates the cross-sectional structure of the third transistor 211G of the present invention. In the embodiment of the present invention, if the third transistor 211G is an EPROM, the main components contained therein include a source, a drain, a polysilicon gate, a floating gate M1, a first dielectric layer ILD, a control gate M2, and a second dielectric layer IMD. The source and the drain can be made of N-type or P-type semiconductors, and the first dielectric layer ILD is disposed between the polysilicon gate and the floating gate M1, and the second dielectric layer IMD is disposed between the floating gate M1 and the control gate M2. The polysilicon gate is used to connect the source and the drain, and the floating gate M1 and the control gate M2 are made of metal materials. In one embodiment of the present invention, if the source and drain are N-type semiconductors, when programming begins, a high voltage is provided at the drain, and electrons will move from the source to the drain through the polysilicon gate. Under the action of the high voltage, the moving force of the electrons is strengthened, and the energy causes the temperature of the electrons to rise, and they become hot electrons. Then, a high voltage is provided to the control gate M2, and the hot electrons will overcome the potential energy of the first dielectric layer ILD and transition to the floating gate M1. If the high voltage of the control gate M2 and the drain is turned off at this time, the hot electrons will be bound (stored) in the floating gate M1, and one programming will be completed. When the third transistor 211G is programmed, the value read will be high resistance (high), compared to the value read when there are no hot electrons in the floating gate M1 before programming, which is low resistance (low). In this way, the memory unit 211 can output a binary digit identification signal. Similarly, the above binary digit identification signal is not limited to 0 and 1 must correspond to low resistance or high resistance, it can also be 1 and 0 correspond to low resistance or high resistance respectively, which can be set, changed or modified according to the actual application. In addition, when the EPROM of the third transistor 211G is programmed multiple times, its resistance value will change when reading, and can be used as a variable record of information during repeated programming, such as the aforementioned ink cartridge capacity change (ink capacity), the number of times the ink cartridge is used on the machine, etc.

[0069] In the embodiments of the present invention, please refer to Fig. 6A and Figure 6B , which illustrates an array structure composed of a plurality of memory cells 211 in an identification chip 210, wherein the array structure includes a combination of a first transistor 211C (ie, MOS Anti-Fuse) and a third transistor 211G (ie, EPROM). Fig. 6A and Figure 6BIt is explained that in the combination of the identification chip 210, the diversity of the types of each memory unit 211 in the identification chip 210 can be increased. That is to say, when the array structure of the identification chip 210 has N memory units 211, it means that the arrangement of the array structure can have a variety of ways to record data. The advantage of such a structure is that, first of all, from the economic point of view, the manufacturing cost of the identification chip 210 with MOS Anti-Fuse and EPROM coexisting can be well controlled. From the perspective of identification signal recording, since the burning type selection of the identification chip 210 is increased, the identification chip 210 can also record more and more complete information, such as the ink cartridge serial number, identification code, ink type, ink capacity, ink color, inkjet head temperature, etc. Finally, in terms of information security and intellectual property, since the inkjet head chip 100A needs to be matched with relevant identification software, identification program or identification algorithm during the matching process with the printer 30, the increase in the burning type and diversity of the identification chip 210, combined with the above-mentioned calculation mechanism, can also enhance the strictness of the identification chip 210 in information security encryption, thereby protecting the intellectual property of the enterprise and the relevant rights of users. It should be noted here that the array structure composed of multiple memory units 211 in Figure 6 is only for illustration, and in the actual application of the present invention, it does not limit the placement position of Fuse, MOS Anti-Fuse and EPROM in the array structure (that is, the selection type and state of each memory unit 211) and the number of bits, for example Fig. 6A One aspect of the present invention is Figure 6B This is another implementation in the above description. Therefore, those skilled in the art can select or modify the placement and bit quantity of Fuse, MOS Anti-Fuse and EPROM in the array structure according to actual applications.

[0070] In summary, the present invention proposes a configuration structure of the memory unit in the identification chip identification circuit, so that the ink cartridge can be reused, improving the environmental performance of the product while maintaining the protection of intellectual property rights. It should be possible for people familiar with this technology to make various modifications as they wish, but they all do not depart from the scope of protection defined by the attached claims.

Claims

1. An identification chip, comprising: A plurality of memory cells are arranged to form an array structure, and the array structure also includes: a first transistor; and a third transistor; The identification chip is connected and matched with the printer by configuring the quantity, combination and position of the first transistor and the third transistor in the array structure, and transmits an identification signal to the printer.

2. The identification chip as claimed in claim 1, wherein the first transistor is selected from an N-type metal oxide semiconductor field effect transistor (NMOS) or a P-type metal oxide semiconductor field effect transistor (PMOS).

3. The identification chip as claimed in claim 1, wherein the third transistor comprises: A source, a drain, a polysilicon gate, a floating gate, a first dielectric layer, a control gate, and a second dielectric layer; wherein the first dielectric layer is arranged between the polysilicon gate and the floating gate, the second dielectric layer is arranged between the floating gate and the control gate, and the polysilicon gate is connected to the source and the drain. The identification chip as claimed in claim 3 , wherein the floating gate and the control gate are made of metal.

5. The identification chip as claimed in claim 1, wherein the plurality of memory units further comprises: an identification signal terminal connected to the first transistor or the third transistor to provide an identification potential; A data terminal, providing a data potential; as well as, a second transistor, the second transistor is connected to the first transistor or the third transistor, and a gate of the second transistor is connected to the data terminal; The plurality of memory units read the identification signal by adjusting the data potential and the identification potential.

6. An identification chip as described in claim 5, wherein when the identification signal end is connected to the first transistor, and the identification potential is less than a breakdown potential, and the data end provides a high potential, the identification signal end will be in a high resistance state in the corresponding multiple memory cells, and the output identification signal shows that the corresponding multiple memory cells are in an unburned state. 7 . The identification chip as claimed in claim 6 , wherein the structure of the gate oxide layer (GOX) of the first transistor is in a good state.

8. An identification chip as described in claim 5, wherein when the identification signal end is connected to the first transistor and the identification potential is greater than a breakdown potential, the identification signal end will be in a low resistance state in the corresponding multiple memory cells, and the output identification signal shows that the corresponding multiple memory cells are in a burned state. 9 . The identification chip as claimed in claim 8 , wherein a structure of a gate oxide layer (GOX) of the first transistor is in a collapsed state.

10. The identification chip as described in claim 1, wherein the information recorded in the identification chip includes information such as ink cartridge serial number, identification code, ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, ink cartridge capacity change (ink capacity), number of times the ink cartridge is used on the machine, etc., or any combination of the above.

11. The identification chip as described in claim 10, wherein the first transistor records information in the inkjet head chip that will not change, including ink cartridge serial number, identification code, ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, or any combination thereof.

12. The identification chip as claimed in claim 10, wherein the third transistor records information that will change in the inkjet head chip, including information such as changes in ink cartridge capacity (ink capacity), the number of times the ink cartridge is used on the machine, or any combination of the above.

Images