Semiconductor structure and semiconductor process detection method
By designing target holes and simulation holes in semiconductor structures, the filling conditions inside the target holes are characterized by using the filling conditions of the simulated holes surface, the problem that the existing technology cannot accurately monitor the filling conditions inside the silicon deep holes is solved, and effective detection of the hole filling process is achieved, and product yield is improved.
Patent Information
- Application Number
- CN202311137285.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-05
- Publication Date
- 2025-03-07
AI Technical Summary
The prior art cannot accurately monitor the filling conditions inside the silicon deep hole, which makes it difficult to detect abnormalities in the hole filling process in time, affecting the yield of the product.
A semiconductor structure is designed, including a substrate structure, a target hole and a simulation hole. The target hole and a simulation hole extend in the thickness direction of the substrate structure. The aperture of the simulation hole is equal to the aperture of the target hole, but the depth is smaller than the target hole. The filling condition inside the target hole is characterized by the filling condition of the simulation hole surface.
By scanning and comparing the filling conditions of the target hole and the simulated hole surface, it is possible to accurately obtain whether there are defects in a certain section of the hole filling process, thereby improving the product yield.
Smart Images
Figure CN119568989A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for detecting a semiconductor structure and a semiconductor process. Background Art
[0002] In the manufacturing process of MEMS (Micro Electromechanical System) devices, it is often necessary to etch deep silicon holes in the silicon substrate, and then use a hole filling process to fill the silicon deep holes with conductive materials. Abnormalities in the hole filling process usually lead to missing conductive material filling, thereby reducing the product yield. In current technology, defect scanning equipment can only monitor the filling conditions on the surface of the silicon deep hole, but cannot monitor the filling conditions inside the silicon deep hole, resulting in the inability to accurately obtain abnormal conditions in the hole filling process, which is not conducive to improving the product yield. Summary of the invention
[0003] Based on this, it is necessary to provide a method for detecting a semiconductor structure and a semiconductor process to address the above problems.
[0004] In a first aspect, an embodiment of the present application provides a semiconductor structure for detecting defects in a semiconductor process, including:
[0005] A substrate structure, wherein at least one target hole and at least one simulation hole are provided on the substrate structure; the target hole and the simulation hole are both along the thickness direction of the substrate structure, extending from the surface of the substrate structure toward the inside of the substrate structure; the aperture of the simulation hole is equal to the aperture of the target hole, and the depth of the simulation hole is less than the depth of the target hole;
[0006] The barrier layer covers the surface of the substrate structure, the hole wall of the target hole, and the hole wall of the simulation hole.
[0007] In one embodiment, there are a plurality of simulation holes, and the plurality of simulation holes are arranged at intervals on the substrate structure.
[0008] In one embodiment, the simulated holes are of multiple types, the simulated holes of the same type have the same depth, and the simulated holes of different types have different depths;
[0009] The number of the simulated holes of the same type is at least one.
[0010] In one of the embodiments, among all types of simulated holes, the depths of different types of simulated holes increase in increments according to a preset step size.
[0011] In one embodiment, the ratio of the depth to the diameter of the target hole is n, and the number of types of the simulated holes is a positive integer m;
[0012] The m and n satisfy the relationship: m+1≥n.
[0013] In one embodiment, the number of the simulation holes in the same type of simulation holes is multiple; the number of the target holes is multiple; a first exposure area and multiple second exposure areas are provided on the substrate structure;
[0014] The plurality of target holes are located in the first exposure area; the simulation holes of the same type are located in the same second exposure area, and the simulation holes of different types are located in different second exposure areas.
[0015] In one embodiment, in the same second exposure area, the simulation holes are evenly arranged;
[0016] And / or, the target holes are evenly arranged in the first exposure area.
[0017] In one embodiment, in the same second exposure area, the distance between two adjacent simulation holes is equal to the aperture of the simulation hole;
[0018] And / or, the distance between two adjacent target holes is equal to the aperture of the target hole.
[0019] In one embodiment, the substrate structure includes a base and a dielectric layer that are stacked, and the target hole and the simulation hole extend from a surface of the dielectric layer toward the base.
[0020] The semiconductor structure provided in the embodiment of the present application can be applied to the detection of defects in the hole filling process. Specifically, when the hole filling process to be detected is detected, the simulated hole and the target hole can be filled with the hole filling process to be detected. After the filling is completed, the filling condition on the surface of the simulated hole can characterize the filling condition of a certain section of the hole inside the target hole. Therefore, by scanning and comparing the surfaces of the target hole and the simulated hole through a defect scanning device, it can be obtained whether there is a defect in a certain section of the hole filling process, which is beneficial to improving the product yield.
[0021] In a second aspect, an embodiment of the present application provides a semiconductor process detection method, comprising:
[0022] Provide a semiconductor structure as described in any embodiment of the first aspect;
[0023] Filling a conductive layer in the target hole and the simulated hole of the semiconductor structure using a preset process;
[0024] Surface images of the target hole and the simulation hole are acquired, and performance parameters of the preset process are determined based on the surface images of the target hole and the simulation hole.
[0025] In one embodiment, the step of providing the semiconductor structure according to any embodiment of the first aspect comprises:
[0026] providing a substrate structure;
[0027] The target hole and the simulation hole are formed on the substrate structure; the target hole and the simulation hole are both along the thickness direction of the substrate structure, extending from the surface of the substrate structure to the inside of the substrate structure; the aperture of the simulation hole is equal to the aperture of the target hole, and the depth of the simulation hole is less than the depth of the target hole;
[0028] A barrier layer is formed on the substrate structure, wherein the barrier layer covers the surface of the substrate structure, the hole wall of the target hole, and the hole wall of the simulation hole.
[0029] In one embodiment, the step of filling the target hole and the simulated hole of the semiconductor structure with a conductive layer using a preset process includes:
[0030] Forming a conductive material layer on the substrate structure of the semiconductor structure by a preset process, wherein the conductive material layer fills the target hole and the simulation hole and covers the surface of the substrate structure;
[0031] The conductive material layer on the surface of the substrate structure is removed to expose the surface of the target hole and the surface of the simulation hole.
[0032] The semiconductor process detection method provided in the embodiment of the present application uses the filling condition of the simulated hole surface to characterize the filling condition of a certain section of the hole inside the target hole, thereby obtaining whether there are defects in the sub-segment process corresponding to the hole filling process through the surface images of the simulated hole and the target hole, which is beneficial to improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0034] Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor structure provided in an embodiment of the present application.
[0035] Figure 2 for Figure 1 Schematic top view of the semiconductor structure shown.
[0036] Figure 3A schematic flow chart of a semiconductor process detection method provided in an embodiment of the present application.
[0037] Figure 4 for Figure 3 A schematic diagram of the process of S100 in the detection method shown.
[0038] Figure 5 for Figure 3 A schematic diagram of the process of S200 in the detection method shown.
[0039] Figures 6 to 8 for Figure 4 A schematic diagram of the cross-sectional structure of a semiconductor structure during the process of the method shown.
[0040] Figure 9a and Figure 9b A semiconductor structure Figure 5 A schematic diagram of a cross-sectional structure during the process of the method is shown.
[0041] Fig.10a and Fig.10b Another semiconductor structure Figure 5 A schematic diagram of a cross-sectional structure during the process of the method is shown.
[0042] Fig.11 A relationship diagram between the simulated hole defect number and the target hole defect number provided in the embodiment of the present application.
[0043] Reference numerals:
[0044] 10. Semiconductor structure; 11. Substrate structure; 111. Base; 112. Dielectric layer; 12. Target hole; 13. Simulation hole; 131. First simulation hole; 132. Second simulation hole; 133. Third simulation hole; 14. Blocking layer; 151. First exposure area; 152. Second exposure area; 153. Exposure window; 20. Photoresist; 30. Conductive material layer; 31. Conductive layer. DETAILED DESCRIPTION
[0045] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.
[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0047] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0048] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0049] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0050] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.
[0051] First, refer to Figure 1 and Figure 2 As shown, an embodiment of the present application provides a semiconductor structure 10 for detecting defects in a semiconductor process. The semiconductor structure 10 includes a substrate structure 11 and a barrier layer 14 .
[0052] Among them, at least one target hole 12 and at least one simulation hole 13 are provided on the substrate structure 11. Both the target hole 12 and the simulation hole 13 extend from the surface of the substrate structure 11 to the inside of the substrate structure 11 along the thickness direction of the substrate structure 11. The aperture of the simulation hole 13 is equal to the aperture of the target hole 12, and the depth of the simulation hole 13 is less than the depth of the target hole 12. It can be understood that the substrate structure 11 has a top surface and a bottom surface that are relatively arranged, and the target hole 12 and the simulation hole 13 can extend from the top surface to the bottom surface.
[0053] Furthermore, the barrier layer 14 covers the surface of the substrate structure 11, the hole wall of the target hole 12, and the hole wall of the simulation hole 13. Here, the hole wall specifically includes the side and bottom of the hole. In one example, the material of the barrier layer 14 can be titanium, titanium nitride, etc.
[0054] It should be noted that the target hole 12 is a target through silicon via (TSV), and the simulation hole 13 is a hole structure used to simulate the target through silicon via. When filling the target hole 12, the hole filling process includes multiple sub-segment processes, and each sub-segment process corresponds to filling a small section of the target hole 12. By making the depth of the simulation hole 13 smaller than the depth of the target hole 12, the surface filling condition of the simulation hole 13 can be used to characterize the filling condition of a certain specific depth inside the target hole 12. Further, the filling condition of the specific depth can reflect whether the hole filling process is abnormal when filling the specific depth, that is, whether a certain sub-segment process corresponding to the specific depth in the hole filling process is abnormal.
[0055] In the embodiment of the present application, the target hole 12 has at least the following functions: 1. The surface filling condition of the target hole 12 can be used to characterize whether the last sub-segment process in the hole filling process is abnormal; 2. When the surface filling condition of the target hole 12 meets the preset requirements, the surface image of the target hole 12 can be used as a comparative reference for the surface image of the simulation hole 13, so that the process personnel can quickly determine whether the surface filling condition of the simulation hole 13 meets the preset requirements; 3. When the surface filling of the simulation hole 13 is abnormal and the simulation authenticity of the simulation hole 13 needs to be verified, the target hole 12 can be sliced and analyzed to verify whether the filling condition of a specific position in the target hole 12 is consistent with the filling condition of the surface of the simulation hole 13. Here, the preset requirement refers to that the hole filling is relatively complete and has no defects.
[0056] The semiconductor structure 10 provided in the embodiment of the present application is equivalent to a physical structure model for detecting a hole filling process, and can be applied to the detection of defects in the hole filling process. Specifically, when the hole filling process to be detected is detected, the simulated hole 13 and the target hole 12 can be filled with the hole filling process to be detected. After the filling is completed, the surfaces of the target hole 12 and the simulated hole 13 are scanned and compared by a defect scanning device to obtain whether there are defects in a certain sub-segment of the hole filling process, which is beneficial to improving the product yield.
[0057] In one embodiment, there are a plurality of simulation holes 13 , and the plurality of simulation holes 13 are arranged at intervals on the substrate structure 11 .
[0058] Specifically, the multiple simulation holes 13 can be arranged in the following manner:
[0059] In one example, the depths of the multiple simulated holes 13 are all equal, that is, all the simulated holes 13 are the same type of simulated holes 13. Since the multiple simulated holes 13 are distributed at different positions on the substrate structure 11, each simulated hole 13 can represent whether a certain sub-segment process of the hole filling process is abnormal at a specific position.
[0060] In another example, the depths of the plurality of simulated holes 13 are not equal. In this way, it is possible to characterize whether the plurality of sub-segment processes of the hole filling process are abnormal.
[0061] Providing a plurality of simulation holes 13 is helpful to improving the efficiency of semiconductor process detection.
[0062] In one embodiment, referring to Figure 1 As shown, there are multiple types of simulated holes 13, the same type of simulated holes 13 have the same depth, and different types of simulated holes 13 have different depths. The number of simulated holes 13 in the same type of simulated holes 13 is at least one.
[0063] In this way, each type of simulated hole 13 can characterize whether a certain sub-segment process of the hole filling process is abnormal. In this way, by setting multiple types of simulated holes 13, it is possible to characterize whether multiple sub-segment processes of the hole filling process are abnormal, which is beneficial to improving the efficiency of semiconductor process detection.
[0064] In one embodiment, among all types of simulation holes 13, the depths of different types of simulation holes 13 increase according to a preset step length, that is, each type of simulation hole 13 corresponds to a depth, and the depths of different types of simulation holes 13 are different, and the depths of all types of simulation holes 13 increase according to a preset step length. Exemplarily, there are three types of simulation holes 13, the depth of the first type of simulation hole 13 is 0.1H, the depth of the second type of simulation hole 13 is 0.2H, and the depth of the third type of simulation hole 13 is 0.3H, and the preset step length is 0.1H.
[0065] The above arrangement enables uniform inspection of the hole filling process.
[0066] In one embodiment, the ratio of the depth to the diameter of the target hole 12 is n, and the number of types of the simulation holes 13 is a positive integer m. m and n satisfy the relationship: m+1≥n.
[0067] In one example, the ratio of the depth to the aperture of the target hole 12 is 4, and the number of types of the simulated holes 13 can be 3, 4, 5, 6 or more. In another example, the ratio of the depth to the aperture of the target hole 12 is 4.5, and the number of types of the simulated holes 13 can be 4, 5, 6, 7 or more.
[0068] The above arrangement, by determining the number of types of the simulation holes 13 according to the ratio of the depth to the aperture of the target hole 12 , is helpful for obtaining the hole filling condition inside the target hole 12 on the one hand, and is helpful for improving the efficiency of semiconductor process detection on the other hand.
[0069] In one embodiment, the depth of the target hole 12 is H, and the preset step length is H / n, where n is the ratio of the depth of the target hole 12 to the hole diameter.
[0070] In this way, it is equivalent to increasing the depth of the simulated hole 13 according to a specific rule. In this way, by limiting the depth change of the simulated hole 13, the detection of the hole filling process can be relatively stable, continuous and uniform.
[0071] In one embodiment, among all the simulated holes 13, the ratio of the minimum depth of the simulated hole 13 to the depth of the target hole 12 is between 0.15 and 0.3. For example, the depth of the target hole 12 is H, and the minimum depth of the simulated hole 13 can be 0.15H, 0.2H, 0.25H or 0.3H.
[0072] It should be noted here that there are many types of simulation holes 13, and the depth of each simulation hole 13 is different. By limiting the minimum depth of the simulation hole 13, it is equivalent to limiting the depth of the simulation hole 13 of the type of simulation hole with the smallest depth. This is beneficial to the detection and evaluation of the sub-segment process corresponding to the depth.
[0073] In one embodiment, there are multiple simulated holes 13 in the same type of simulated holes 13. There are multiple target holes 12. It should be noted that among the same type of simulated holes 13, multiple simulated holes 13 are distributed at different positions on the substrate structure 11, so each simulated hole 13 can represent whether a certain sub-segment process of the hole filling process is abnormal at a specific position. Further, the multiple target holes 12 are distributed at different positions on the substrate structure 11, so each target hole 12 can represent whether the hole filling process is abnormal at different positions.
[0074] Further, a first exposure area 151 and a plurality of second exposure areas 152 are provided on the substrate structure 11. The plurality of target holes 12 are located in the first exposure area 151. The same type of simulation holes 13 are located in the same second exposure area 152, and different types of simulation holes 13 are located in different second exposure areas 152, respectively.
[0075] The above arrangement is equivalent to dividing the substrate structure 11 into a plurality of exposure areas, each of which has a hole structure of the same depth. This is beneficial to improving the manufacturing efficiency of the hole structure, thereby improving the manufacturing efficiency of the semiconductor structure 10 .
[0076] In one embodiment, the simulation holes 13 are evenly arranged in the same second exposure area 152. In this way, the arrangement of the simulation holes 13 is relatively even, so that the filling conditions of a certain sub-segment filling process at different positions in the second exposure area 152 can be evenly detected.
[0077] In one embodiment, the target holes 12 are evenly arranged in the first exposure area 151. In this way, the target holes 12 are evenly arranged, so that the filling conditions of a sub-segment filling process at different positions in the first exposure area 151 can be evenly detected.
[0078] In one embodiment, in the same second exposure area 152, the distance between two adjacent simulated holes 13 is equal to the aperture of the simulated hole 13. In this way, the arrangement density of the simulated holes 13 can be made larger, and the filling conditions at different positions of the hole filling process can be tested to the maximum extent.
[0079] In one embodiment, the distance between two adjacent target holes 12 is equal to the diameter of the target hole 12. In this way, the target holes 12 can be arranged at a higher density, and the filling conditions at different positions of the hole filling process can be tested to the maximum extent.
[0080] In one embodiment, the substrate structure 11 includes a base 111 and a dielectric layer 112 which are stacked, and the target hole 12 and the simulation hole 13 extend from the surface of the dielectric layer 112 toward the base 111 .
[0081] In one example, the material of the substrate 111 may be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), etc. The material of the dielectric layer 112 may be silicon dioxide.
[0082] Based on the description of the above embodiments, more specific embodiments are proposed below for detailed description.
[0083] Specifically, refer to Figure 1 and Figure 2 As shown, the semiconductor structure 10 includes a substrate structure 11 and a barrier layer 14. The substrate structure 11 is provided with a plurality of target holes 12 and a plurality of simulation holes 13. The target holes 12 and the simulation holes 13 are both along the thickness direction of the substrate structure 11, extending from the surface of the substrate structure 11 to the inside of the substrate structure 11. The aperture of the simulation hole 13 is equal to the aperture of the target hole 12, and the depth of the simulation hole 13 is less than the depth of the target hole 12. The barrier layer 14 covers the surface of the substrate structure 11, the hole wall of the target hole 12, and the hole wall of the simulation hole 13.
[0084] Further, the ratio of the depth to the aperture of the target hole 12 is 4, and there are three types of simulation holes 13, namely, the first simulation hole 131, the second simulation hole 132, and the third simulation hole 133. The depth of the target hole 12 is H, the depth of the first simulation hole 131 is 0.25H, the depth of the second simulation hole 132 is 0.5H, and the depth of the third simulation hole 133 is 0.75H, that is, the minimum depth of the simulation hole 13 is 0.25H, and the preset step size is 0.25H.
[0085] Further, a first exposure area 151 and three second exposure areas 152 are provided on the substrate structure 11. A plurality of exposure windows 153 are provided in the first exposure area 151, and a plurality of target holes 12 are provided in the area corresponding to each exposure window 153. The first simulation hole 131, the second simulation hole 132 and the third simulation hole 133 are respectively located in the three second exposure areas 152. Taking the second exposure area 152 where the first simulation hole 131 is located as an example, a plurality of exposure windows 153 are provided in the second exposure area 152, and a plurality of first simulation holes 131 are provided in the area corresponding to each exposure window 153.
[0086] When the semiconductor structure 10 is applied to the detection of defects in the hole filling process, it can simulate the filling condition inside the target hole 12 relatively accurately, thereby reflecting whether there are defects in the hole filling process, which is beneficial to improving the product yield.
[0087] Second, refer to Figure 3 , and combined with Figures 6 to 10b As shown, the embodiment of the present application provides a semiconductor process detection method, comprising:
[0088] S100: Provide a semiconductor structure 10 according to any one of the embodiments of the first aspect, that is, provide a physical structure model for detecting a hole filling process.
[0089] S200: Fill the target hole 12 and the simulation hole 13 of the semiconductor structure 10 with a conductive layer 31 using a preset process. Here, the preset process is a hole filling process, and specifically, the hole filling process may be magnetron sputtering, chemical vapor deposition (CVD), electroplating, atomic layer deposition (ALD), etc. In an example, the conductive layer 31 may be made of copper, tungsten, aluminum, etc.
[0090] S300: Acquire surface images of the target hole 12 and the simulated hole 13, and determine the performance parameters of the preset process based on the surface images of the target hole 12 and the simulated hole 13. Exemplarily, the surface images of the target hole 12 and the simulated hole 13 may be acquired by a measuring machine.
[0091] It should be noted that the target hole 12 is a target through silicon via (TSV). When filling the target hole 12, the hole filling process includes multiple sub-segment processes, and each sub-segment process corresponds to filling a small section of the target hole 12. In the embodiment of the present application, the target hole 12 has at least the following functions: 1. The surface filling condition of the target hole 12 can be used to characterize whether the last sub-segment process in the hole filling process is abnormal; 2. When the surface filling of the target hole 12 meets the preset requirements, the surface image of the target hole 12 can be used as a comparison reference for the surface image of the simulation hole 13, so that the process personnel can quickly determine whether the surface filling of the simulation hole 13 meets the preset requirements; 3. When the surface filling of the simulation hole 13 is abnormal and the simulation authenticity of the simulation hole 13 needs to be verified, the target hole 12 can be sliced and analyzed to verify whether the filling condition of a specific position in the target hole 12 is consistent with the filling condition of the surface of the simulation hole 13.
[0092] Therefore, when determining the performance parameters of the preset process, the following methods can be used:
[0093] In one example, the surface image of the simulated hole 13 is directly observed with naked eyes to see whether it meets the preset requirements.
[0094] In another example, when the last sub-stage process of the hole filling process is known to be normal, the surface image of the simulated hole 13 can be compared with the surface image of the target hole 12 to determine whether the surface image of the simulated hole 13 meets the preset requirements.
[0095] The semiconductor process detection method provided in the embodiment of the present application uses the filling condition of the surface of the simulated hole 13 to characterize the filling condition of a certain section of the hole inside the target hole 12, so as to obtain whether there are defects in the sub-segment process corresponding to the hole filling process through the surface images of the simulated hole 13 and the target hole 12, thereby facilitating the process personnel to carry out targeted improvements and adjustments to the hole filling process, which is conducive to improving product yield.
[0096] In one embodiment, referring to Figure 4 As shown, S100 includes the following steps:
[0097] S110: providing a substrate structure 11.
[0098] Specifically, S110 includes the following steps:
[0099] S111: providing a substrate 111. The substrate 111 may be made of single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS).
[0100] S112: forming a dielectric layer 112 on the substrate 111. For example, the dielectric layer 112 may be made of calcium dioxide.
[0101] After the dielectric layer 112 is formed, the following steps are performed:
[0102] S120: forming a target hole 12 and a simulated hole 13 on the substrate structure 11. Both the target hole 12 and the simulated hole 13 extend from the surface of the substrate structure 11 to the inside of the substrate structure 11 along the thickness direction of the substrate structure 11. The aperture of the simulated hole 13 is equal to the aperture of the target hole 12, and the depth of the simulated hole 13 is less than the depth of the target hole 12.
[0103] Specifically, combined Figure 7 and Figure 8 As shown, S120 includes the following steps:
[0104] S121: forming a photoresist 20 on the substrate structure 11. In the embodiment of the present application, the photoresist 20 is a positive photoresist 20.
[0105] S122: exposing and developing the photoresist 20.
[0106] In the embodiment of the present application, there are four exposure areas, and there are three types of simulation holes 13 on the substrate structure 11, wherein the target hole 12 is in one exposure area, and the three types of simulation holes 13 are respectively in the remaining three exposure areas. It can be understood that the exposure energies of the four exposure areas are different. In one example, the exposure energy is 10mj to 50mj, and the exposure focal length is -0.8 to 0.5.
[0107] S123: Etching the substrate structure 11. Specifically, the etching can be performed by a dry process or a wet process. In the embodiment of the present application, the substrate structure 11 is etched by a dry process. After etching, the following steps are performed:
[0108] S130: forming a barrier layer 14 on the substrate structure 11, the barrier layer 14 covers the surface of the substrate structure 11, the hole wall of the target hole 12, and the hole wall of the simulation hole 13. Exemplarily, the barrier layer 14 can be formed by a chemical vapor deposition (CVD) process.
[0109] In one embodiment, referring to Figure 5 As shown, S200 includes the following steps:
[0110] S210: A conductive material layer 30 is formed on the substrate structure 11 of the semiconductor structure 10 by using a preset process, and the conductive material layer 30 fills the target hole 12 and the simulation hole 13, and covers the surface of the substrate structure 11. Specifically, the conductive material layer 30 can be formed by magnetron sputtering, chemical vapor deposition (CVD), electroplating or atomic layer deposition (ALD).
[0111] S220: removing the conductive material layer 30 on the surface of the substrate structure 11 to expose the surface of the target hole 12 and the surface of the simulation hole 13. Exemplarily, the surface of the substrate structure 11 may be planarized by chemical mechanical planarization (CMP).
[0112] When the preset process has no defects, the filling condition of the conductive material layer 30 is as follows: Figure 9a and Figure 9b When the preset process has defects, the filling condition of the conductive material layer 30 is as shown in FIG. Fig.10a and Fig.10b shown.
[0113] It should be noted that the inventors verified the simulation authenticity of the simulated hole 13, that is, when the surface filling of the simulated hole 13 showed abnormality, the target hole 12 was sliced and analyzed to obtain the actual filling situation inside the target hole 12. The relationship between the number of defects in the simulated hole 13 and the number of defects in the target hole 12 is shown in the figure. Fig.11 As shown, through Fig.11 From the fitting curve in , it can be seen that the number of defects in the simulated hole 13 is linearly related to the number of defects in the target hole 12, indicating that the simulated hole 13 can better simulate the internal filling condition of the target hole 12.
[0114] It should be understood that in the embodiments of the present application, at least part of the steps in the drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0115] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0116] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A semiconductor structure for detecting defects in semiconductor processes, characterized in that: include: A substrate structure, wherein at least one target hole and at least one simulation hole are provided on the substrate structure; The target hole and the simulation hole are both along the thickness direction of the substrate structure, extending from the surface of the substrate structure toward the inside of the substrate structure; the aperture of the simulation hole is equal to the aperture of the target hole, and the depth of the simulation hole is less than the depth of the target hole; The barrier layer covers the surface of the substrate structure, the hole wall of the target hole, and the hole wall of the simulation hole.
2. The semiconductor structure according to claim 1, characterized in that: The number of the simulation holes is multiple, and the multiple simulation holes are arranged at intervals on the substrate structure.
3. The semiconductor structure according to claim 2, characterized in that: There are multiple types of the simulated holes, the simulated holes of the same type have the same depth, and the simulated holes of different types have different depths; The number of the simulated holes of the same type is at least one.
4. The semiconductor structure according to claim 3, characterized in that: Among all the simulated hole types, the depths of the simulated holes of different types increase in increments according to a preset step size.
5. The semiconductor structure according to claim 3, characterized in that: The ratio of the depth to the diameter of the target hole is n, and the number of types of the simulated holes is a positive integer m; The m and n satisfy the relationship: m+1≥n.
6. The semiconductor structure according to claim 3, characterized in that: There are multiple simulated holes in the same type of simulated holes; there are multiple target holes; a first exposure area and multiple second exposure areas are provided on the substrate structure; The plurality of target holes are located in the first exposure area; the simulation holes of the same type are located in the same second exposure area, and the simulation holes of different types are located in different second exposure areas.
7. The semiconductor structure according to claim 6, characterized in that: In the same second exposure area, the simulation holes are evenly arranged; And / or, the target holes are evenly arranged in the first exposure area.
8. The semiconductor structure according to claim 6, characterized in that: In the same second exposure area, the distance between two adjacent simulation holes is equal to the aperture of the simulation hole; And / or, the distance between two adjacent target holes is equal to the aperture of the target hole.
9. The semiconductor structure according to claim 1, characterized in that: The substrate structure comprises a base and a dielectric layer which are stacked, and the target hole and the simulation hole extend from the surface of the dielectric layer toward the base.
10. A semiconductor process detection method, characterized in that: include: Providing a semiconductor structure according to any one of claims 1 to 9; Filling a conductive layer in the target hole and the simulated hole of the semiconductor structure using a preset process; Surface images of the target hole and the simulation hole are acquired, and performance parameters of the preset process are determined based on the surface images of the target hole and the simulation hole.
11. The semiconductor process detection method according to claim 10, characterized in that: The step of providing a semiconductor structure as claimed in any one of claims 1 to 9 comprises: providing a substrate structure; The target hole and the simulation hole are formed on the substrate structure; the target hole and the simulation hole are both along the thickness direction of the substrate structure, extending from the surface of the substrate structure to the inside of the substrate structure; the aperture of the simulation hole is equal to the aperture of the target hole, and the depth of the simulation hole is less than the depth of the target hole; A barrier layer is formed on the substrate structure, wherein the barrier layer covers the surface of the substrate structure, the hole wall of the target hole, and the hole wall of the simulation hole.
12. The semiconductor process detection method according to claim 10, characterized in that: The step of filling the target hole and the simulated hole of the semiconductor structure with a conductive layer using a preset process includes: Forming a conductive material layer on the substrate structure of the semiconductor structure by a preset process, wherein the conductive material layer fills the target hole and the simulation hole and covers the surface of the substrate structure; The conductive material layer on the surface of the substrate structure is removed to expose the surface of the target hole and the surface of the simulation hole.