Single-chip microcomputer key circuit and electronic equipment

Abstract

The invention provides a single-chip microcomputer key circuit and electronic equipment, a first key extension module comprises # imgabs0 # group first extension units, each # imgabs0 # group first extension unit comprises 2N pairs of first extension subunits, each pair of first extension subunits comprises a first key group and a second key group, and a plurality of key switches are respectively arranged in the first key group and the second key group; the input end of each first key group or each second key group is respectively coupled with N ports in the 2N ports, and the output end of each first key group or each second key group is respectively coupled with the other N ports; n ports respectively coupled with the input end and the output end of the second key group are the same as N ports respectively coupled with the output end and the input end of the first key group; ports coupled with the input end of each first key group in each group of first expansion units are not completely the same; therefore, the on-off state in each key group can be detected by switching the working mode of the port and the logic signal of the output state under the condition that the IO number is small, the number of the keys of the single-chip microcomputer is expanded, and then the key requirement is met.

Description

Technical Field

[0001] The present invention relates to the technical field of single chip computers, and in particular to a single chip computer key circuit and electronic equipment. Background Art

[0002] Currently commonly used single-chip microcomputer keys include: independent key structure, matrix keyboard, etc., which are widely used in single-chip microcomputer devices and systems.

[0003] In the actual use of single-chip microcomputer equipment, it is often the case that the single-chip microcomputer needs more buttons. At this time, it is necessary to expand the number of buttons of the single-chip microcomputer. If each button is identified by the button polling method, a large amount of IO of the single-chip microcomputer will be occupied, and the IO resources of the single-chip microcomputer are limited. If the current IO resources are relatively scarce, the number of expanded buttons will be insufficient. If the Chinese utility model patent with the publication number of "CN214670202U" and the invention name of "A Single-chip Microcomputer Key Circuit" is adopted, a structure in which a button is connected to the corresponding pin in the single-chip microcomputer through a reverse cutoff is mentioned. The connection between the button and the single-chip microcomputer is realized through this structure, and the structure does not need to scan each button. However, the single-chip microcomputer key expansion realized by the above two methods can only realize more expansion of single-chip microcomputer keys when the number of IO is large. When the number of IO is small, the number of single-chip microcomputer keys that can be expanded in the prior art is limited.

[0004] Therefore, how to expand the number of microcontroller buttons to meet the button demand when the number of IO is small has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0005] The present invention provides a single-chip computer key circuit and an electronic device to solve the problem of how to greatly expand the number of single-chip computer keys to meet key requirements when the number of IOs is small.

[0006] According to a first aspect of the present invention, there is provided a single-chip microcomputer key circuit for expanding the number of keys of a single-chip microcomputer, the single-chip microcomputer comprising 2N ports, N of which are used as input ports, and the remaining N ports are used as output ports, where N is a positive integer; the single-chip microcomputer key circuit comprises at least a first key expansion module;

[0007] The first key expansion module includes A first expansion unit group, each first expansion unit group includes 2 N For the first extension subunits, each pair of the first extension subunits includes a first key group and a second key group; and each of the first key group and the second key group is provided with N groups of key switch units, each group of key switch units includes a plurality of key switches;

[0008] The input ends of the first key group are respectively coupled to N ports among the 2N ports, and the output ends thereof are respectively coupled to the remaining N ports; the input ends of the second key group are respectively coupled to N ports among the 2N ports, and the output ends thereof are respectively coupled to the remaining N ports; and the N ports respectively coupled to the input ends of the second key group are the same as the N ports respectively coupled to the output ends of the first key group, and the N ports respectively coupled to the output ends of the second key group are the same as the N ports respectively coupled to the input ends of the first key group;

[0009] The ports coupled to the input ends of each first key group in each set of first extension units are the same, and the ports coupled to the input ends of the first key groups corresponding to each first extension unit are not completely the same;

[0010] Wherein, the single chip microcomputer is configured as:

[0011] Periodically switching the working mode of the port and the output logic signal to poll each first key group and the second key group, wherein the working mode includes an input port mode and an output port mode; and detecting the logic signals of the N input ports to detect the switch state in each first key group or the second key group;

[0012] The first key group and the second key group are both configured as:

[0013] Based on the working modes of the N ports coupled to its input ends and the output logic signals, it is determined whether to start detecting the states of a number of key switches in the first key group or the second key group, and based on the determination result and the states of a number of key switches in the first key group or the second key group, the logic signals output by the remaining N ports coupled to its output ends are controlled.

[0014] Optionally, the logic signal includes a first level and a second level; the first key group and the second key group are both configured to determine whether to start detecting the states of a plurality of key switches in the first key group or the second key group according to the working modes of the N ports coupled to their input ends and the output logic signals, and control the output states of the remaining N ports coupled to their output ends according to the determination result and the states of the plurality of key switches in the first key group or the second key group, specifically:

[0015] When the N ports coupled to the input end of the first key group or the second key group are all output ports of the single-chip computer and the N ports all output the first level, control the output end thereof to be connected to the remaining N ports to control the output state of the remaining N ports coupled to the output end thereof, and start detecting the states of a plurality of key switches in the first key group or the second key group;

[0016] If any of the key switches in the first key group or the second key group is in a closed state, the port coupled to the key switch is controlled to change from a first level to a second level, or the port coupled to the key switch is controlled to change from a second level to a first level;

[0017] When not all the N ports coupled to the input ends of the first key group or the second key group are output ports of the microcontroller, or when not all the states of the coupled N output ports are at the first level, the output ends are controlled to be in a floating input mode, and detection of the states of several key switches in the first key group or the second key group is prohibited.

[0018] Optionally, the first key group and the second key group include a polling detection module, a key detection module, N pull-up resistors and the N groups of key switch units, each group of key switch units includes branches, where i is a positive integer and i≤N;

[0019] The input end of the polling detection module is coupled to N ports respectively, and the output end thereof is coupled to the enable end of the key detection module. The first unit of the key detection module includes N terminals, which are respectively coupled to the remaining N ports, and the second unit thereof includes N terminals. The first end of each branch is respectively coupled to i terminals of the second unit through i reverse cutoff devices, and the second end thereof is respectively coupled to the terminals of the remaining second units, and the third end thereof is grounded; the first end of the N pull-up resistors is connected to a pull-up voltage, and the second end of the N pull-up resistors is respectively coupled to a first connection point, so as to control any key switch among a plurality of key switches in the first key group or the second key group to be in a closed state, and control the port corresponding to the key switch to change from the second level to the first level, wherein the first connection point is used to characterize the A node between the second end of each branch and the N terminals of the second unit; wherein the number of terminals of the second unit coupled to each group of key switch units is different, and the terminals of the second unit coupled to the first end of each branch in each group of key switch units are not completely the same;

[0020] Wherein, the polling detection module is used to determine whether to start detecting the status of a number of key switches in the key group;

[0021] The key detection module is configured to:

[0022] When starting to detect the status of several key switches in the key group, synchronize the logic signals output by the N coupled input ports and the logic signals output by the N terminals of the second unit. Otherwise, control the N terminals of the second unit to a floating input mode and output a high impedance state.

[0023] Optionally, the branch includes a first-type key switch and a second-type key switch, and the i-th branch includes one first-type key switch and Ni second-type key switches, wherein:

[0024] The first end of the first type of key switch is coupled to the first end of the i inverting cutoff devices, the second end of the inverting cutoff device is coupled to one of the N terminals of the second unit, the first end of the first type of key switch is also coupled to the first ends of the Ni second type of key switches, the second ends of the Ni second type of key switches are coupled to the remaining terminals of the second unit, and the second end of the first type of key switch is grounded.

[0025] Optionally, the reverse cutoff device is a diode, the first end of the first type key switch is coupled to the cathode of the diode, and the anode of the diode is coupled to the terminal of the second unit.

[0026] Optionally, the polling detection module includes an AND gate circuit;

[0027] The input end of the AND gate circuit is coupled to N ports through k inverters, and the output end is coupled to the enable end of the key detection module. In each group of first expansion units, the number of the AND gate circuits coupled to N ports through k inverters is In the AND gate circuits having N ports coupled through the same number of inverters, the ports coupled by the k inverters are not identical to each other, wherein k is an integer and k≤N

[0028] Optionally, the key detection module is a latch.

[0029] Optionally, it further includes a second key expansion module; the second key expansion module is coupled to 2N ports corresponding to any group of first expansion units; the second key expansion module includes 2N groups of second key switch units, each group of second key switch units includes branches, where m is a positive integer and m≤2N;

[0030] The branch includes a third type key switch and a fourth type key switch, and each branch includes one third type key switch and 2N-m fourth type key switches, wherein:

[0031] The first end of the third type key switch is coupled to the first end of m second inverting cutoff devices, the second end of the second inverting cutoff device is coupled to one of the 2N ports, the second end of the third type key switch is respectively coupled to the first end of the 2N-m fourth type key switches, the second end of the 2N-m fourth type key switches is respectively coupled to the remaining ports, and the second end of the third type key switch is also grounded;

[0032] Wherein, in each group of second key switch units, the ports to which the first ends of the third type key switches are coupled are not completely the same.

[0033] Optionally, it further includes a display module, wherein the display module includes a display, a driving circuit module and a pull-up resistor module;

[0034] The first end of the display is coupled to the 2N+1th end of the single-chip microcomputer through the driving circuit module, and the second end of the display is coupled to the pull-up resistor module, and the pull-up resistor module is also coupled to the 2N+2th end of the single-chip microcomputer.

[0035] According to a second aspect of the present invention, there is provided an electronic device, comprising the single chip microcomputer key circuit provided by any one of the first aspect of the present invention.

[0036] The single chip key circuit and the electronic device provided by the present invention, wherein the first key expansion module comprises A first expansion unit group, each first expansion unit group includes 2 N For the first expansion subunits, each pair of first expansion subunits includes a first key group and a second key group, and a number of key switches are respectively arranged in the first key group and the second key group; the input end of each first key group or the second key group is respectively coupled to N ports of the 2N ports, and the output end thereof is respectively coupled to the remaining N ports; and the N ports to which the input end and the output end of the second key group are respectively coupled are the same as the N ports to which the output end and the input end of the first key group are respectively coupled; and the ports coupled to which the input end of each first key group in each group of first expansion units are not exactly the same; thus, the present invention can detect the switch state in each key group by switching the working mode of the port and the logic signal of the output state when the number of IOs is small, thereby realizing the expansion of the number of microcontroller keys and thus meeting the key requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 The schematic diagram of the structure of the single chip key circuit in the embodiment of the present invention is Figure 1 ;

[0039] Figure 2 The schematic diagram of the structure of the single chip key circuit in the first embodiment of the present invention is Figure 1 ;

[0040] Figure 3The schematic diagram of the structure of the single chip key circuit in the first embodiment of the present invention is Figure 2 ;

[0041] Figure 4 It is a schematic diagram of the structure of the single chip computer key circuit in the second embodiment of the present invention;

[0042] Figure 5 It is a schematic diagram of the structure of the single chip computer key circuit in the third embodiment of the present invention;

[0043] Figure 6 The schematic diagram of the structure of the single chip key circuit in the fourth embodiment of the present invention is Figure 1 ;

[0044] Figure 7 The schematic diagram of the structure of the single chip key circuit in the fourth embodiment of the present invention is Figure 2 ;

[0045] Figure 8 Schematic diagram of the structure of a single chip computer key circuit in a fifth embodiment of the present invention;

[0046] Description of reference numerals:

[0047] 10- single chip microcomputer;

[0048] 20-first key expansion module;

[0049] 201-first expansion unit;

[0050] 2011- Polling detection module;

[0051] 2012-Key detection module;

[0052] 2013-Key switch unit;

[0053] CE-enabling end;

[0054] 20111-First AND gate;

[0055] 20112-second AND gate;

[0056] 20113-the third AND gate;

[0057] 30- second key expansion module;

[0058] 301- second key switch unit;

[0059] 40-display module;

[0060] 402-driving circuit module;

[0061] 403-Pull-up resistor module. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0064] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0065] In view of the problem that it is difficult to expand the number of microcontroller keys to meet the key demand in the prior art when the number of IOs is small, the present invention provides a microcontroller key circuit and an electronic device, wherein the first key expansion module includes A first expansion unit, each comprising 2 N For the first expansion subunits, each pair of first expansion subunits includes a first key group and a second key group, and a number of key switches are respectively arranged in the first key group and the second key group; the input end of each first key group or the second key group is respectively coupled to N ports of the 2N ports, and the output end thereof is respectively coupled to the remaining N ports; and the input end and the output end of the second key group are the same as the N ports to which the output end and the input end of the first key group are respectively coupled; and the ports coupled to the input end of each first key group in each group of first expansion units are not exactly the same; thus, the present invention can detect the switch state in each key group by switching the working mode of the port and the logic signal of the output state when the number of IOs is small, thereby realizing the expansion of the number of microcontroller keys and thus meeting the key requirements.

[0066] Please refer to Figure 1The embodiment of the present invention provides a single-chip microcomputer 10 key circuit, which is used to expand the number of keys of the single-chip microcomputer 10. The single-chip microcomputer 10 includes 2N ports, N of which are used as input ports, and the remaining N ports are used as output ports, where N is a positive integer; the single-chip microcomputer 10 key circuit includes at least a first key expansion module 20;

[0067] The first key expansion module 20 includes A group of first expansion units 201, each group of first expansion units 201 includes 2 N For the first extension subunits, each pair of the first extension subunits includes a first key group and a second key group; and each of the first key group and the second key group is provided with N groups of key switch units 2013, and each group of key switch units 2013 includes a plurality of key switches;

[0068] The input ends of the first key group are respectively coupled to N ports among the 2N ports, and the output ends thereof are respectively coupled to the remaining N ports; the input ends of the second key group are respectively coupled to N ports among the 2N ports, and the output ends thereof are respectively coupled to the remaining N ports; and the N ports respectively coupled to the input ends of the second key group are the same as the N ports respectively coupled to the output ends of the first key group, and the N ports respectively coupled to the output ends of the second key group are the same as the N ports respectively coupled to the input ends of the first key group;

[0069] The ports coupled to the input ends of each first key group in each set of first expansion units 201 are the same, but the ports coupled to the input ends of the first key groups corresponding to each first expansion unit 201 are not completely the same;

[0070] Wherein, the single chip computer 10 is configured as:

[0071] Periodically switching the working mode of the port and the output logic signal to poll each first key group and the second key group, wherein the working mode includes an input port mode and an output port mode; and detecting the logic signals of the N input ports to detect the switch state in each first key group or the second key group;

[0072] The first key group and the second key group are both configured as:

[0073] Based on the working modes of the N ports coupled to its input ends and the output logic signals, it is determined whether to start detecting the states of a number of key switches in the first key group or the second key group, and based on the determination result and the states of a number of key switches in the first key group or the second key group, the logic signals output by the remaining N ports coupled to its output ends are controlled.

[0074] In a specific implementation manner, the logic signal includes a first level and a second level; in this case, the first key group and the second key group are configured to determine whether to start detecting the states of a plurality of key switches in the first key group or the second key group according to the working modes of the N ports coupled to their input ends and the output logic signals, and control the output states of the remaining N ports coupled to their output ends according to the determination result and the states of the plurality of key switches in the first key group or the second key group, specifically:

[0075] When the N ports coupled to the input end of the first key group or the second key group are all output ports of the single-chip computer 10, and the N ports all output the first level, control the output end thereof to be connected to the remaining N ports, control the output state of the remaining N ports coupled to the output end thereof, and start detecting the states of a plurality of key switches in the first key group or the second key group;

[0076] If any of the key switches in the first key group or the second key group is in a closed state, the port coupled to the key switch is controlled to change from a first level to a second level, or the port coupled to the key switch is controlled to change from a second level to a first level;

[0077] When the N ports coupled to the input ends of the first key group or the second key group are not all output ports of the single-chip computer 10, or the states of the coupled N output ports are not all at the first level, the output ends are controlled to be in a floating input mode, and the detection of the states of several key switches in the first key group or the second key group is prohibited.

[0078] For an example, please refer to Figure 2 The first key group and the second key group include a polling detection module 2011, a key detection module 2012, N pull-up resistors and the N groups of key switch units 2013. The key detection module 2012 includes a first unit and a second unit. Each group of key switch units 2013 includes branches, where i is a positive integer and i≤N;

[0079] The input end of the polling detection module 2011 is coupled to N ports respectively, and the output end thereof is coupled to the enable end CE of the key detection module 2012. The first unit of the key detection module 2012 includes N terminals, which are respectively coupled to the remaining N ports, and the second unit thereof includes N terminals. The first end of each branch is respectively coupled to i terminals of the second unit through i reverse cutoff devices, and the second end thereof is respectively coupled to the terminals of the remaining second units, and the third end thereof is grounded; the first end of the N pull-up resistors is connected to a pull-up voltage (at Figure 2In the example shown, the two pull-up resistors of the first key group are respectively a first resistor R1 and a second resistor R2, and the two pull-up resistors of the second key group are respectively a third resistor R3 and a fourth resistor R4, and the second ends of the N pull-up resistors are respectively coupled to a first connection point, so as to control the port corresponding to the key switch to change from the second level to the first level when any key switch among the plurality of key switches in the first key group or the second key group is in a closed state, wherein the first connection point is used to represent the A node between the second end of each branch and the N terminals of the second unit; wherein the number of terminals of the second unit coupled to each group of key switch units 2013 is different, and the terminals of the second unit coupled to the first end of each branch in each group of key switch units 2013 are not completely the same;

[0080] The polling detection module 2011 is used to determine whether to start detecting the status of a number of key switches in the key group;

[0081] The key detection module 2012 is configured to:

[0082] When starting to detect the status of several key switches in the key group, synchronize the logic signals output by the N coupled input ports and the logic signals output by the N terminals of the second unit; otherwise, control the N terminals of the second unit to a floating input mode and output a high impedance state to prevent changes in the logic level output by the corresponding coupled ports.

[0083] For an example, please refer to Figure 3 , the key detection module 2012 can be a latch. Of course, the present invention does not limit its specific implementation method, the key detection module 2012 can also be a trigger, a register, etc., as long as it can realize the synchronization of the logic signals output by the N input ports coupled thereto and the logic signals output by the N terminals of the second unit when starting to detect the states of several key switches in the key group, otherwise, the N terminals of the second unit are controlled to be in a floating input mode and output a high impedance state. All of them cannot deviate from the protection of the present invention.

[0084] exist Figure 2 In the example shown, the single-chip computer 10 includes 4 ports. In this case, the first connection point includes two first sub-connection points, which are two nodes between the second ends of the four branches and the two terminals of the second unit. When the number of ports included in the single-chip computer 10 is different, the connection mode of the N pull-up resistors is also different. Figure 4 The example shows a connection mode of the N pull-up resistors in the circuit when the single chip computer 10 includes 6 ports (in Figure 4In the example shown, the three pull-up resistors corresponding to the first key group or the second key group are respectively a first resistor R1, a second resistor R2 and a third resistor). In this case, the first connection point includes three first sub-connection points, which are respectively three nodes between the second ends of the six branches and the three terminals of the second unit.

[0085] Specifically, the branch includes a first type of key switch and a second type of key switch, and the i-th branch includes 1 first type of key switch and Ni second type of key switches, wherein:

[0086] The first end of the first type of key switch is coupled to the first end of the i inverting cutoff devices, the second end of the inverting cutoff device is coupled to one of the N terminals of the second unit, the first end of the first type of key switch is also coupled to the first ends of the Ni second type of key switches, the second ends of the Ni second type of key switches are coupled to the remaining terminals of the second unit, and the second end of the first type of key switch is grounded.

[0087] Now combined Figure 2 and Figure 4 Further explanation of the working modes of the first type of push button switches and the second type of push button switches:

[0088] Please refer to Figure 2 In one example, when the states of the output ports of the single-chip microcomputer 10 coupled to the input ends of the first key group or the second key group are all at the first level, and the input ports of the single-chip microcomputer 10 are all at the first level, if there is an i-th first-type key switch in any group of key switch units 2013 that is in a closed state, the levels of the corresponding i terminals of the second units are pulled low, and the single-chip microcomputer 10 obtains the state of the corresponding key switch through the change of the state of its input port;

[0089] When the states of the output ports of the single-chip microcomputer 10 coupled to the input ends of the first key group or the second key group are all at the first level, the single-chip microcomputer 10 can also configure its N input ports, with j input ports being at the first level and the remaining Nj input ports being at the second level. The single-chip microcomputer 10 obtains the states of the corresponding key switches by changing the states of its input ports, so as to detect the second type of key switches in the branch one by one, where j is a positive integer and j≤N-1.

[0090] For the sake of convenience, the first level is a high level and the second level is a low level. Figure 4, now take monitoring the state of the first second-type key switch of the first branch of the first group of key switch units 2013 as an example for further explanation, the first group of key switch units 2013 includes 3 branches, each branch includes 1 first-type key switch and 2 second-type key switches, on this basis, the terminals of the second unit are set to be the first input port, the second input port and the third input port in sequence:

[0091] When the N ports coupled to the input end of the first key group or the second key group are all output ports of the single-chip computer 10, and the N ports all output the first level, if the first input port of the single-chip computer 10 is configured to be the first level, and the second input port and the third input port of the single-chip computer 10 are both the second level, then if the first second-type key switch of the first branch is in a closed state, the levels of the second input port and the fourth input port of the single-chip computer 10 will be pulled high, and the single-chip computer 10 can obtain that the first second-type key switch of the first branch of the first group of key switch units 2013 is in a closed state through the change of the state of its input port;

[0092] Similarly, by configuring the second input port of the single-chip microcomputer 10 to be the first level, and the first input port and the third input port of the single-chip microcomputer 10 to be the second level, the state of the second second-type key switch of the first branch of the first group of key switch units 2013 can be monitored; by configuring the first input port and the second input port of the single-chip microcomputer 10 to be the first level, and the third input port of the single-chip microcomputer 10 to be the second level, the state of the corresponding second-type key switch of the first branch of the second group of key switch units 2013 can be monitored. For the sake of brevity, it will not be repeated here.

[0093] In one implementation, please refer to Figure 2 , Figure 3 as well as Figure 4 , the reverse cutoff device is a diode, the first end of the first type key switch is coupled to the cathode of the diode, and the anode of the diode is coupled to the terminal of the second unit.

[0094] Of course, the present invention does not limit the type of the inverter cutoff device, and the inverter cutoff device may also be a CMOS inverter, etc. Those skilled in the art may select different devices as the inverter cutoff device as needed.

[0095] The polling detection module 2011 is described in detail as follows:

[0096] In one implementation, please refer to Figure 5 , the polling detection module 2011 includes an AND gate circuit;

[0097] The input end of the AND gate circuit is coupled to N ports through k inverters, and the output end is coupled to the enable end CE of the key detection module 2012. In each group of first expansion units 201, the number of the AND gate circuits coupled to N ports through k inverters is In the AND gate circuits having N ports coupled through the same number of inverters, the ports coupled by the k inverters are not completely the same, wherein k is an integer and k≤N.

[0098] exist Figure 2 In the circuit shown, the AND gate circuit includes a first AND gate 20111 , a first input terminal and a second input terminal of the first AND gate 20111 are respectively coupled to two ports through k inverters, and an output terminal thereof is coupled to the enable terminal CE of the key detection module 2012 .

[0099] exist Figure 4 In the circuit shown in FIG. 1 , the AND gate circuit includes: the first input terminal and the second input terminal of the first AND gate 20111, and the first input terminal and the second input terminal of the second AND gate 20112 are respectively coupled to three ports (in Figure 4 In the example of k=0), the output end of the first AND gate 20111 is coupled to the first input end of the third AND gate 20113, the output end of the second AND gate 20112 is coupled to the second input end of the third AND gate 20113, and the output end of the third AND gate 20113 is coupled to the enable end CE of the key detection module 2012.

[0100] It should be understood that the present invention does not limit the structure of the polling detection module used. In one example, a digital circuit can also be used to monitor the status of its input end coupled to N ports respectively. The specific composition of the polling detection module can be adaptively adjusted according to actual needs. The present invention is not limited to this. As long as the technical concept of the present invention is adopted, it cannot deviate from the protection of the present invention.

[0101] In order to further expand the number of buttons of the single chip computer 10, in a preferred implementation mode, please refer to Figure 6 The single-chip computer 10 key circuit also includes a second key expansion module 30; the second key expansion module 30 is coupled to any group of 2N ports corresponding to the first expansion unit 201; please continue to refer to Figure 7 The second key expansion module 30 includes 2N groups of second key switch units 301, each group of second key switch units 301 includes branches, where m is a positive integer and m≤2N;

[0102] The branch includes a third type key switch and a fourth type key switch, and each branch includes one third type key switch and 2N-m fourth type key switches, wherein:

[0103] The first end of the third type key switch is coupled to the first end of m second inverting cutoff devices, the second end of the second inverting cutoff device is coupled to one of the 2N ports, the second end of the third type key switch is respectively coupled to the first end of the 2N-m fourth type key switches, the second end of the 2N-m fourth type key switches is respectively coupled to the remaining ports, and the second end of the third type key switch is also grounded;

[0104] The ports to which the first ends of the third type of key switches in each group of second key switch units 301 are coupled are not completely the same.

[0105] By the above method, the 2N ports of the single-chip computer 10 can be reused, and the working mode of each branch is the same as Figure 2 or Figure 3 The branches shown work in a similar manner and will not be described again for brevity.

[0106] Therefore, in the single chip computer 10 key circuit provided by the present invention, the total number of key switches that can be expanded is:

[0107]

[0108] in, is the number of key switches that can be expanded by the first key expansion module 20, is the number of key switches that can be expanded by the second key expansion module 30.

[0109] To facilitate the positioning of the closed pushbutton switch, please refer to Figure 8 , the key circuit of the single chip computer 10 further includes a display module 40, and the display module 40 includes a display 401, a driving circuit module 402 and a pull-up resistor module 403;

[0110] The first end of the display 401 is coupled to the 2N+1th end of the single-chip microcomputer 10 through the driving circuit module 402 , and the second end thereof is coupled to the pull-up resistor module 403 , and the pull-up resistor module 403 is also coupled to the 2N+2th end of the single-chip microcomputer 10 .

[0111] In addition, the present invention also provides an electronic device, comprising the single chip computer key circuit in the aforementioned solution of the present invention.

[0112] In summary, the single-chip computer key circuit of the present invention includes: A first expansion unit, each comprising 2N For the first expansion subunits, each pair of first expansion subunits includes a first key group and a second key group, and a number of key switches are respectively arranged in the first key group and the second key group; the input end of each first key group or the second key group is respectively coupled to N ports of the 2N ports, and the output end thereof is respectively coupled to the remaining N ports; and the input end and the output end of the second key group are the same as the N ports to which the output end and the input end of the first key group are respectively coupled; and the ports coupled to the input end of each first key group in each group of first expansion units are not exactly the same; thus, the present invention can detect the switch state in each key group by switching the working mode of the port and the logic signal of the output state when the number of IOs is small, thereby realizing the expansion of the number of microcontroller keys and thus meeting the key requirements.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A single-chip microcomputer key circuit, used to expand the number of keys of a single-chip microcomputer, characterized in that: The single-chip microcomputer includes 2N ports, N of which are used as input ports, and the remaining N ports are used as output ports, where N is a positive integer; the single-chip microcomputer key circuit includes at least a first key expansion module; The first key expansion module includes A group of first expansion units, each group of first expansion units includes 2 N For the first extension subunits, each pair of the first extension subunits includes a first key group and a second key group; and each of the first key group and the second key group is provided with N groups of key switch units, each group of key switch units includes a plurality of key switches; The input ends of the first key group are respectively coupled to N ports among the 2N ports, and the output ends thereof are respectively coupled to the remaining N ports; the input ends of the second key group are respectively coupled to N ports among the 2N ports, and the output ends thereof are respectively coupled to the remaining N ports; The N ports to which the input ends of the second key group are respectively coupled are the same as the N ports to which the output ends of the first key group are respectively coupled, and the N ports to which the output ends of the second key group are respectively coupled are the same as the N ports to which the input ends of the first key group are respectively coupled; The ports coupled to the input ends of each first key group in each set of first extension units are the same, and the ports coupled to the input ends of the first key groups corresponding to each first extension unit are not completely the same; Wherein, the single chip microcomputer is configured as: Periodically switching the working mode of the port and the output logic signal to poll each first key group and the second key group, wherein the working mode includes an input port mode and an output port mode; and detecting the logic signals of the N input ports to detect the switch state in each first key group or the second key group; The first key group and the second key group are both configured as: Based on the working modes of the N ports coupled to its input ends and the output logic signals, it is determined whether to start detecting the states of a number of key switches in the first key group or the second key group, and based on the determination result and the states of a number of key switches in the first key group or the second key group, the logic signals output by the remaining N ports coupled to its output ends are controlled.

2. The single chip computer key circuit according to claim 1, characterized in that: The logic signal includes a first level and a second level; the first key group and the second key group are both configured to determine whether to start detecting the states of a plurality of key switches in the first key group or the second key group according to the working modes of the N ports coupled to their input ends and the output logic signals, and control the output states of the remaining N ports coupled to their output ends according to the determination result and the states of the plurality of key switches in the first key group or the second key group, specifically: When the N ports coupled to the input end of the first key group or the second key group are all output ports of the single-chip computer and the N ports all output the first level, control the output end thereof to be connected to the remaining N ports to control the output state of the remaining N ports coupled to the output end thereof, and start detecting the states of a plurality of key switches in the first key group or the second key group; If any of the key switches in the first key group or the second key group is in a closed state, the port coupled to the key switch is controlled to change from a first level to a second level, or the port coupled to the key switch is controlled to change from a second level to a first level; When not all the N ports coupled to the input ends of the first key group or the second key group are output ports of the microcontroller, or when not all the states of the coupled N output ports are at the first level, the output ends are controlled to be in a floating input mode, and detection of the states of several key switches in the first key group or the second key group is prohibited.

3. The single chip computer key circuit according to claim 2, characterized in that: The first key group and the second key group include a polling detection module, a key detection module, N pull-up resistors and the N groups of key switch units, each group of key switch units includes branches, where i is a positive integer and i≤N; The input end of the polling detection module is coupled to N ports respectively, and the output end thereof is coupled to the enable end of the key detection module. The first unit of the key detection module includes N terminals, which are respectively coupled to the remaining N ports, and the second unit thereof includes N terminals. The first end of each branch is respectively coupled to i terminals of the second unit through i reverse cutoff devices, and the second end thereof is respectively coupled to the terminals of the remaining second units, and the third end thereof is grounded; the first end of the N pull-up resistors is connected to a pull-up voltage, and the second end of the N pull-up resistors is respectively coupled to a first connection point, so as to control any key switch among a plurality of key switches in the first key group or the second key group to be in a closed state, and control the port corresponding to the key switch to change from the second level to the first level, wherein the first connection point is used to characterize the A node between the second end of each branch and the N terminals of the second unit; wherein the number of terminals of the second unit coupled to each group of key switch units is different, and the terminals of the second unit coupled to the first end of each branch in each group of key switch units are not completely the same; Wherein, the polling detection module is used to determine whether to start detecting the status of a number of key switches in the key group; The key detection module is configured to: When starting to detect the status of several key switches in the key group, synchronize the logic signals output by the N coupled input ports and the logic signals output by the N terminals of the second unit. Otherwise, control the N terminals of the second unit to a floating input mode and output a high impedance state.

4. The single chip computer key circuit according to claim 3, characterized in that: The branch includes a first-type key switch and a second-type key switch, and the i-th branch includes 1 first-type key switch and Ni second-type key switches, wherein: The first end of the first type of key switch is coupled to the first end of the i inverting cutoff devices, the second end of the inverting cutoff device is coupled to one of the N terminals of the second unit, the first end of the first type of key switch is also coupled to the first ends of the Ni second type of key switches, the second ends of the Ni second type of key switches are coupled to the remaining terminals of the second unit, and the second end of the first type of key switch is grounded.

5. The single chip computer key circuit according to claim 4, characterized in that: The reverse cutoff device is a diode, the first end of the first type key switch is coupled to the cathode of the diode, and the anode of the diode is coupled to the terminal of the second unit.

6. The single chip computer key circuit according to claim 3, characterized in that: The polling detection modules all include an AND gate circuit; The input end of the AND gate circuit is coupled to N ports through k inverters, and the output end is coupled to the enable end of the key detection module. In each group of first expansion units, the number of the AND gate circuits coupled to N ports through k inverters is In the AND gate circuits having N ports coupled through the same number of inverters, the ports coupled by the k inverters are not completely the same, wherein k is an integer and k≤N.

7. The single chip computer key circuit according to claim 3, characterized in that: The key detection module is a latch.

8. The single chip computer key circuit according to claim 1, characterized in that: The second key expansion module is also included; the second key expansion module is coupled to 2N ports corresponding to any group of first expansion units; the second key expansion module includes 2N groups of second key switch units, each group of second key switch units includes branches, where m is a positive integer and m≤2N; The branch includes a third type key switch and a fourth type key switch, and each branch includes one third type key switch and 2N-m fourth type key switches, wherein: The first end of the third type key switch is coupled to the first end of m second inverting cutoff devices, the second end of the second inverting cutoff device is coupled to one of the 2N ports, the second end of the third type key switch is respectively coupled to the first end of the 2N-m fourth type key switches, the second end of the 2N-m fourth type key switches is respectively coupled to the remaining ports, and the second end of the third type key switch is also grounded; Wherein, in each group of second key switch units, the ports to which the first ends of the third type key switches are coupled are not completely the same.

9. The single chip computer key circuit according to claim 1, characterized in that: Also includes a display module, the display module includes a display, a driving circuit module and a pull-up resistor module; The first end of the display is coupled to the 2N+1th end of the single-chip microcomputer through the driving circuit module, and the second end of the display is coupled to the pull-up resistor module, and the pull-up resistor module is also coupled to the 2N+2th end of the single-chip microcomputer.

10. An electronic device, characterized in that: It comprises the single chip computer key circuit as described in any one of claims 1 to 9.

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