Modeling method, system and device for data transmission between GPU core particles and readable storage medium

Abstract

The invention relates to the technical field of computer structure simulation, in particular to a modeling method, system and device for data transmission between GPU core particles and a readable storage medium, a GPU simulator is configured for each GPU core particle so that each GPU core particle can achieve the core particle function in the independent GPU simulator, and the simulator executes GPU core particle arithmetic logic through GPGPU-Sim; each GPU simulator abstracts each GPU core particle simulator into a corresponding SST component based on an SST structure simulation toolkit, the GPU core particle simulators are connected through an SST Link, the SST Link is used for sending an SST event, and the SST event is received through an event processor in the SST component at the opposite end, so that data transmission between GPU core particles is simulated. According to the method, the data transmission among the GPUs in the multi-GPU system can be simulated, so that a chip designer can accelerate the design progress of the multi-GPU system in a chip design stage, and the system verification cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of computer structure simulation, and in particular to a GPU inter-chip data transmission modeling method, system, device and readable storage medium. Background Art

[0002] With the development of artificial intelligence applications, GPUs have become the main components for providing computing power in the systems designed for current servers and computing centers, and more systems using multiple GPUs as the main computing power have emerged. However, among multiple GPUs in the same PCIe node, if the calculation results or data of GPU0 need to be transmitted to GPU1, the communication between the two GPUs is completely dependent on the CPU, that is, CPU0 first transmits the data to the CPU, and the CPU then transmits the data to GPU0. At this point, it can be seen that the data transmission bandwidth is limited by the CPU bandwidth, and the data delay is also large due to the copy twice. In order to improve the utilization efficiency of multiple GPUs and improve the overall performance of the system, GPU manufacturers provide the function of direct communication between GPUs. For example, NVIDIA has proposed GPU peer to peer (P2P) technology. When users need to use this P2P technology, they need to use a series of API interfaces provided by CUDA. However, GPGPU-Sim, the most commonly used GPU simulator in the industry, does not support the simulation of these CUDA functions. For this reason, there is an urgent need for a modeling method for data transmission between GPUs to simulate data transmission between GPUs in a multi-GPU system. Summary of the invention

[0003] To this end, the present invention provides a method, system, device and readable storage medium for modeling data transmission between GPU core particles, and implements modeling and simulation of data transmission between GPU core particles of a multi-GPU system based on an SST framework and a GPGPU-Sim simulator.

[0004] According to the design scheme provided by the present invention, on the one hand, a GPU inter-chip data transmission modeling method is provided, comprising: A GPU simulator is configured for each GPU core particle, so that each GPU core particle realizes the core particle function in an independent GPU simulator, and the simulator uses GPGPU-Sim to execute the GPU core particle operation logic; Based on the SST structure simulation toolkit, each GPU simulator abstracts each GPU core simulator into a corresponding SST component, connects each GPU core simulator through SST Link, uses SST Link to send SST events and receives SST events through the event processor in the peer SST component to simulate data transmission between GPU cores.

[0005] As a GPU core-to-core data transmission modeling method of the present invention, each GPU core simulator is further abstracted into a corresponding SST component, including: Use the SST component code to instantiate the GPU core simulator, create and inherit the GPU type of the SST component, and create a clock function and an SST component external Link interface. The clock function is used to manage the clocks of all SST components of the SST structural simulation toolkit. An event processing function is registered for the Link of each GPU core simulator corresponding to the SST component, and the event processing function is used to process the SST event transmitted to the corresponding component of the GPU core simulator through the SST Link.

[0006] As a GPU inter-chip data transmission modeling method of the present invention, further, using SST Link to send SST events to simulate the data transmission between GPU core particles, including: Ariel is used as a master device connected to multiple GPU simulators to detect the specified function call in the program using the Ariel PIN instrumentation tool, wherein the specified function is the cudaMemcpyPeer function; When a specified function call is detected, the specified function call is converted into an SST event and sent to the corresponding SST component of the GPU simulator; After the corresponding component of the GPU simulator receives the SST event, it uses the cudaMemcpy function of Device To Host to extract the SST event data and store the data in the SST component, and uses the cudaMemcpy function of Host To Device to send the data to the SST component of the peer GPU simulator.

[0007] In another aspect, the present invention further provides a GPU inter-chiplet data transmission modeling system, comprising: a chiplet simulation configuration module and a component instantiation module, wherein: A core particle simulation configuration module is used to configure a GPU simulator for each GPU core particle so that each GPU core particle implements the core particle function in an independent GPU simulator, and the simulator uses GPGPU-Sim to execute the GPU core particle operation logic; The component instantiation module is used for each GPU simulator to abstract each GPU core simulator into a corresponding SST component based on the SST structure simulation toolkit, connect each GPU core simulator through SST Link, use SST Link to send SST events and receive SST events through the event processor in the opposite SST component to simulate data transmission between GPU cores.

[0008] In another aspect, the present invention further provides an electronic device, comprising: at least one processor, and a memory coupled to the at least one processor; The memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method as described above.

[0009] In yet another aspect, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed, the method described above can be implemented.

[0010] Beneficial effects of the present invention: The present invention utilizes a master control simulator to detect a CUDA function for calling inter-GPU communication in a user program, adds an SST component for instantiating GPGPU-sim in an SST framework to realize data transmission between GPU simulators, and uses multiple GPGPU-Sim simulators to simulate a cudaMemcpyPeer function for data transmission between GPUs, so that chip designers can simulate and model a system with multiple GPUs during the chip design stage to test and verify the performance of the system, thereby accelerating the design time of the system and reducing the system verification cost. The present invention has good application prospects in the field of chip design and verification testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a schematic diagram of the modeling process of data transmission between GPU core particles in the embodiment; Figure 2 This is a schematic diagram of GPGPU-Sim accessing the SST framework in the embodiment; Figure 3 Ariel is used as the master simulator of GPGPU-Sim in the embodiment; Figure 4 This is an illustration of running multiple GPGPU-Sim simulators under the SST framework in the embodiment. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solutions and advantages of the present invention clearer and more understandable, the present invention is further described in detail below in conjunction with the accompanying drawings and technical solutions.

[0013] For the modeling and simulation of data transmission between GPUs in a multi-GPU system, the embodiment of the present invention, see Figure 1 As shown, a GPU inter-chip data transmission modeling method is provided, including: S101, configuring a GPU simulator for each GPU core particle, so that each GPU core particle implements the core particle function in an independent GPU simulator, and the simulator uses GPGPU-Sim to execute the GPU core particle operation logic; S102. Each GPU simulator abstracts each GPU core simulator into a corresponding SST component based on the SST structure simulation toolkit, connects each GPU core simulator through SST Link, uses SST Link to send SST events and receives SST events through the event processor in the opposite SST component to simulate data transmission between GPU cores.

[0014] Specifically, each GPU core simulator is abstracted into a corresponding SST component, which can be designed to include: Use the SST component code to instantiate the GPU core simulator, create and inherit the GPU type of the SST component, and create a clock function and an SST component external Link interface. The clock function is used to manage the clocks of all SST components of the SST structural simulation toolkit. An event processing function is registered for the Link of each GPU core simulator corresponding to the SST component, and the event processing function is used to process the SST event transmitted to the corresponding component of the GPU core simulator through the SST Link.

[0015] like Figure 2 As shown in the figure, in the SST framework, each individual simulator is abstracted as an SST component. SST components are connected through SST Links, and SST components can send SST events to the SST components on the other end through SST Links. Create an SST component for GPGPU-Sim, which will instantiate a GPGPU-Sim simulator. The component contains an SST event handler to receive events from SST. After receiving the SST event, the component will interpret it and convert it into a C\C++ function call to GPGPU-Sim.

[0016] Among them, using SST Link to send SST events to simulate data transmission between GPU core particles may include: The local host is used as a master device connected to multiple GPU simulators to use the specified function call in the master device detection program, wherein the specified function is the cudaMemcpyPeer function; When a specified function call is detected, the specified function call is converted into an SST event and sent to the corresponding SST component of the GPU simulator; After the corresponding component of the GPU simulator receives the SST event, it uses the cudaMemcpy function of Device To Host to extract the SST event data and store the data in the SST component, and uses the cudaMemcpy function of Host To Device to send the data to the SST component of the peer GPU simulator.

[0017] As a slave device, GPU needs a master device to control it. Generally speaking, this master device is a CPU. In GPGPU-Sim simulator, it uses the local host as the master device. Figure 3 As shown, in the SST framework, there is an x86 CPU simulator: Ariel. In this embodiment, the CPU simulator can be used as the master simulator. Ariel can detect CUDA function calls in the program through Intel's PIN plugging tool. When it detects a CUDA function call, it can be converted into an SST event and sent to the SST component of GPGPU-Sim to implement the call to GPGPU-Sim. Through the Ariel simulator, the user's use of the cudaMemcpyPeer function can be detected, and multiple GPGPU-Sim SST components can be supported to be connected to the Ariel component.

[0018] Specifically, data transmission between GPU simulators, such as Figure 4 As shown, the GPGPU-Sim simulator itself does not support direct Device To Device data transmission functions between GPUs such as cudaMemcpyPeer, and only supports Host ToDevice and Device To Host cudaMemcpy. In the implementation of this case, through the Ariel simulator, users are supported to use the cudaMemcpyPeer function in the program. After detecting the cudaMemcpyPeer function, the Ariel simulator sends an SST event to the SST component of GPGPU-Sim created in the present invention. After receiving the data, the SST component of GPGPU-Sim will first use the Device To Host cudaMemcpy function on the GPU component of src to extract the data, but will not further send it to the Ariel component as the HOST, but will store it in the SST component of GPGPU-Sim, and then use the Host To Device cudaMemcpy function on the SST component of dest GPGPU-Sim to send the data to another GPGPU-Sim simulator, so as to realize data transmission between GPUs by running multiple GPGPU-sim simulators under the SST framework.

[0019] Furthermore, based on the above method, an embodiment of the present invention also provides a GPU inter-chiplet data transmission modeling system, comprising: a chiplet simulation configuration module and a component instantiation module, wherein: A core particle simulation configuration module is used to configure a GPU simulator for each GPU core particle so that each GPU core particle implements the core particle function in an independent GPU simulator, and the simulator uses GPGPU-Sim to execute the GPU core particle operation logic; The component instantiation module is used for each GPU simulator to abstract each GPU core simulator into a corresponding SST component based on the SST structure simulation toolkit, connect each GPU core simulator through SST Link, use SST Link to send SST events and receive SST events through the event processor in the opposite SST component to simulate data transmission between GPU cores.

[0020] When instantiating the SST component for the GPU simulator, add the SST component code of GPGPU-Sim in the sst-element\src\sst\elements directory, create a GPU type that inherits SST:Compenet, create a clockTic function, through which the SST framework manages the clocks of all SST components, create an external link interface for the GPGPU-Sim component, and register an event handling function for the link of the GPGPU-Sim component to handle the SST events transmitted to the GPGPU-Sim component through the link.

[0021] When the master simulator detects the program calling the CUDA function for inter-GPU communication, you can add monitoring of the cudaMemcpyPeer function in the InstrumentRoutine function in the fesimple.cc file of the front-end PIN tool of the Ariel simulator. After monitoring the cudaMemcpyPeer call, use the RTN_Replace function to replace it with the call of the instrumented function mapped_cudaMemcpyPeer. In the mapped_cudaMemcpyPeer function, encapsulate the cuda message and send it to the Ariel backend code. In the processNextEvent function of the Ariel backend arielcore.cc, add a case of the cudaMemcpyPeer event type, and send the event to the SST component of the GPGPU-Sim of the GPU of the src in cudaMemcpyPeer through the SST Link.

[0022] The specific process of implementing data transmission between GPU simulators using the GPGPU-Sim component under the SST framework can be described as follows: Step 1: Add a case of the cudaMemcpyPeer event type to the handleCudaCall function in the gpuInterface.cc file of the SST component of GPGPU-Sim.

[0023] Step 2: In the cudaMemcpyPeer event processing function, execute the cudaMemcpy call of Device To Host on the GPGPU-Sim simulator of src.

[0024] Step 3: After the src GPGPU-Sim simulator is executed, the data is transmitted back to the SST component of the src GPGPU-Sim.

[0025] Step 4: After receiving the data, the SST component of src GPGPU-Sim does not send it to the Host, but encapsulates the data into the cudaMemcpyPeer event.

[0026] Step 5: Send the event to the SST component of dest GPGPU-Sim through SST Link.

[0027] Step 6: After receiving the event, the SST component of dest GPGPU-Sim executes the cudaMemcpy call of HostTo Device on dest GPGPU-Sim.

[0028] Step 7: The GPGPU-Sim simulator of dest performs the data copy operation.

[0029] Step 8: This completes the data transmission operation between the two GPGPU-Sim simulators without passing through the Host, through the cudaMemcpyPeer function.

[0030] Running multiple GPGPU-Sim simulators based on the SST framework supports users to use the cudaMemcpyPeer function to simulate the behavior of direct data transmission between multiple GPU simulators to verify the performance of multi-GPU systems. This can greatly improve system design efficiency and effectively reduce test verification costs.

[0031] Furthermore, an embodiment of the present invention further provides an electronic device, including: at least one processor, and a memory coupled to the at least one processor; The memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method as described above.

[0032] Furthermore, an embodiment of the present invention also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed, the method described above can be implemented.

[0033] Unless otherwise specifically stated, the relative steps, numerical expressions and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0034] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0035] The units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation is not considered to be beyond the scope of the present invention.

[0036] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits, and accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software function modules. The present invention is not limited to any specific form of combination of hardware and software.

[0037] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A GPU inter-chip data transmission modeling method, characterized in that: Include: A GPU simulator is configured for each GPU core particle, so that each GPU core particle realizes the core particle function in an independent GPU simulator, and the simulator uses GPGPU-Sim to execute the GPU core particle operation logic; Based on the SST structure simulation toolkit, each GPU simulator abstracts each GPU core simulator into a corresponding SST component, connects each GPU core simulator through SST Link, uses SST Link to send SST events and receives SST events through the event processor in the peer SST component to simulate data transmission between GPU cores.

2. The GPU inter-chiplet data transmission modeling method according to claim 1, characterized in that: Each GPU core simulator is abstracted into a corresponding SST component, including: Use the SST component code to instantiate the GPU core simulator, create a GPU type that inherits the SST component, and create a clock function and an SST component external Link interface. The clock function is used to manage the clocks of all SST components of the SST structural simulation toolkit. An event processing function is registered for the Link of each GPU core simulator corresponding to the SST component, and the event processing function is used to process the SST event transmitted to the corresponding component of the GPU core simulator through the SST Link.

3. The GPU inter-chiplet data transmission modeling method according to claim 1 or 2, characterized in that: Use SSTLink to send SST events to simulate data transfer between GPU cores, including: Ariel is used as a master device connected to multiple GPU simulators to detect the specified function call in the program using the Ariel PIN instrumentation tool, wherein the specified function is the cudaMemcpyPeer function; When a specified function call is detected, the specified function call is converted into an SST event and sent to the corresponding SST component of the GPU simulator; After the corresponding component of the GPU simulator receives the SST event, it uses the cudaMemcpy function of Device To Host to extract the SST event data and store the data in the SST component, and uses the cudaMemcpy function of Host To Device to send the data to the SST component of the peer GPU simulator.

4. A GPU inter-chiplet data transmission modeling system, characterized in that: Contains: core particle simulation configuration module and component instantiation module, among which, A core particle simulation configuration module is used to configure a GPU simulator for each GPU core particle so that each GPU core particle implements the core particle function in an independent GPU simulator, and the simulator uses GPGPU-Sim to execute the GPU core particle operation logic; The component instantiation module is used for each GPU simulator to abstract each GPU core simulator into a corresponding SST component based on the SST structure simulation toolkit, connect each GPU core simulator through SST Link, use SST Link to send SST events and receive SST events through the event processor in the opposite SST component to simulate data transmission between GPU cores.

5. An electronic device, characterized in that: include: at least one processor, and a memory coupled to the at least one processor; The memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method according to any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the method according to any one of claims 1 to 3 can be implemented.

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