Memory cell, memory array, terminal and operating method

Abstract

The invention provides a memory unit, a memory array, a terminal and an operation method, and the memory unit comprises a volatile in-memory calculation module and a nonvolatile in-memory calculation module. The volatile in-memory calculation module comprises a static random access structure or a dynamic random access structure; and the nonvolatile in-memory calculation module comprises a switching tube and at least one memristor, and the switching tube and the memristor are connected in series and then are connected between the two data ends of the static random access structure or between the data end of the dynamic random access structure and the reference ground. According to the memory unit, the memory array and the operation method provided by the invention, the problem that the dynamic transmission power consumption and the static standby power consumption of the existing random access memory unit are high is effectively relieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a memory unit, a memory array, a terminal and an operation method. Background Art

[0002] The development of large models and artificial intelligence has generated unprecedented data processing volume, which has put forward higher requirements on the speed and energy consumption of data processing. However, when existing general-purpose processors, graphics processors and even neural network processors perform data processing based on static random access memory (SRAM) and dynamic random access memory (DRAM), there are problems of high dynamic power consumption during the operation process and high static power consumption during the standby process. In addition, the speed delay during the data transmission process of the traditional von Neumann architecture also hinders the further improvement of computing power. The combination of volatile SRAM, DRAM and non-volatile memristors provides an idea for reducing static power consumption; however, how to optimize the storage unit structure and achieve more efficient operation is still a technical problem that technicians in this field need to explore and solve.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a memory cell, a memory array, a terminal and an operation method for solving the problems of high dynamic transmission power consumption and high static standby power consumption of the existing random access memory cells.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a memory unit, including a volatile in-memory computing module and a non-volatile in-memory computing module, wherein:

[0006] The volatile in-memory computing module includes a static random access structure or a dynamic random access structure; the non-volatile in-memory computing module includes a switch tube and at least one memristor, which are connected in series between two data ends of the static random access structure or between the data end and a reference ground of the dynamic random access structure.

[0007] Optionally, the static random access structure includes a first gate tube, a second gate tube and a data latch unit, wherein: the gate of the first gate tube is connected to the word line, the source of the first gate tube is connected to the first bit line, the drain of the first gate tube is connected to the first end of the data latch unit and serves as the first data end of the static random access structure; the gate of the second gate tube is connected to the word line, the source of the second gate tube is connected to the second bit line, and the drain of the second gate tube is connected to the second end of the data latch unit and serves as the second data end of the static random access structure.

[0008] Optionally, the data latch unit includes a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein: the gate of the first PMOS tube is connected to the gate of the first NMOS tube and connected to the second end of the data latch unit, the source of the first PMOS tube is connected to the power supply voltage, the drain of the first PMOS tube is connected to the drain of the first NMOS tube and serves as the first end of the data latch unit, and the source of the first NMOS tube is connected to the reference ground; the gate of the second PMOS tube is connected to the gate of the second NMOS tube and connected to the first end of the data latch unit, the source of the second PMOS tube is connected to the power supply voltage, the drain of the second PMOS tube is connected to the drain of the second NMOS tube and serves as the second end of the data latch unit, and the source of the second NMOS tube is connected to the reference ground.

[0009] Optionally, the dynamic random access structure includes a control tube and a capacitor, wherein: the gate of the control tube is connected to the word line, the source of the control tube is connected to the bit line and serves as the data end of the dynamic random access structure, the drain of the control tube is connected to the upper plate of the capacitor, and the lower plate of the capacitor is connected to the reference ground.

[0010] Optionally, when the number of the memristors is one, the memristor is connected to the source or drain of the switch tube; when the number of the memristors is greater than one, the memristor is connected to the source and / or drain of the switch tube; wherein the gate of the switch tube is connected to the control line.

[0011] Optionally, the memristor includes a magnetic memristor, a resistive memristor, a phase-change memristor, a flash memory memristor or a ferroelectric memristor, and the memristor has two or more resistance states.

[0012] The present invention further provides a memory array, comprising a plurality of memory blocks, each of which is arranged in an array in rows and columns, wherein the memory block comprises at least one memory unit as described in any one of the above.

[0013] Optionally, the storage block includes two memory cells, wherein the two memory cells are arranged in a mirror image to store complementary data information.

[0014] Optionally, when the volatile in-memory computing module includes a static random access structure, the two memory units share a control line, a word line and a second bit line; when the volatile in-memory computing module includes a dynamic random access structure, the two memory units share a control line and a word line.

[0015] The present invention also provides a terminal, comprising a processor and a memory array as described in any one of the above items.

[0016] The present invention further provides a method for operating the memory unit as described in any one of the above items, comprising:

[0017] Controlling the volatile in-memory computing module to be turned on, and controlling the non-volatile in-memory computing module to be turned off, so that the memory unit operates in a high-speed computing mode;

[0018] Controlling the volatile in-memory computing module to start, and controlling the non-volatile in-memory computing module to start, so that the memory unit works in a collaborative storage mode;

[0019] The volatile in-memory computing module is controlled to be turned off, and the non-volatile in-memory computing module is controlled to be turned on, so that the memory unit operates in a memristor mode.

[0020] Optionally, the volatile in-memory computing module includes a static random access structure, and the static random access structure includes a first strobe tube, a second strobe tube and a data latch unit:

[0021] In the high-speed computing mode, power is supplied to the data latch unit, the switch tube is turned off through the control line, and the first selection tube and the second selection tube are turned on through the word line. At this time, the memory unit works in a 6T mode, and the data latch unit is read and written through the first bit line and the second bit line;

[0022] In the collaborative storage mode, power is supplied to the data latch unit, the switch tube is turned on through the control line, and the first gating tube and the second gating tube are turned off through the word line. At this time, the memory unit works in a 5T1M mode, and based on the voltage difference across the data latch unit, the data in the data latch unit is written into the memristor;

[0023] In the memristor mode, the data latch unit is powered off, the switch tube is turned on through the control line, and the first selection tube and the second selection tube are turned on through the word line. At this time, the memory unit works in 3T1M mode, and the memristor is read and written through the first bit line and the second bit line.

[0024] Optionally, in the collaborative storage mode, after data is written into the memristor, it also includes: powering off the data latch unit, turning on the first and second gating tubes through the word line, and performing a read operation on the memristor through the first and second bit lines.

[0025] Optionally, the volatile in-memory computing module includes a dynamic random access structure, and the dynamic random access structure includes a control tube and a capacitor:

[0026] In the high-speed computing mode, the switch tube is turned off through the control line, and the control tube is turned on through the word line. At this time, the memory unit works in a 1T1C mode, and the capacitor is read and written through the bit line;

[0027] In the collaborative storage mode, the switch tube is turned on through the control line, and the control tube is turned on through the word line. At this time, the memory unit works in a 2T1C1M mode, and the data in the capacitor is written into the memristor based on the voltage difference across the capacitor;

[0028] In the memristor mode, the switch tube is turned on through the control line and the control tube is turned off through the word line. At this time, the memory unit works in 1T1M mode and the memristor is read and written through the bit line.

[0029] Optionally, in the collaborative storage mode, after data is written into the memristor, the method further includes: turning off the control transistor through a word line, and performing a read operation on the memristor through a bit line.

[0030] Optionally, in the memristor mode, when performing a read and write operation on the memristor:

[0031] If the voltage difference applied to both ends of the memory cell is less than the critical voltage of the memristor, a read operation is performed on the memristor without changing the resistance state of the memristor;

[0032] If the voltage difference applied to both ends of the memory cell is a positive value of the power supply voltage, setting the memristor to a first resistance state;

[0033] If the voltage difference applied across the memory cell is a negative value of the power supply voltage, placing the memristor in a second resistance state;

[0034] If the voltage difference applied to the two ends of the memory unit is between the absolute value of the power supply voltage and the critical voltage of the memristor, the memristor is set to a third resistance state, wherein the third resistance state is between the first resistance state and the second resistance state.

[0035] As described above, the memory unit, memory array, terminal and operation method of the present invention, through the design of volatile in-memory computing modules and non-volatile in-memory computing modules, use a minimum number of devices and control lines to realize three operating modes in one memory unit, namely, high-speed computing mode, collaborative storage mode and memristor mode. This can not only improve the data transmission speed, reduce the dynamic transmission power consumption during the calculation process and the static power consumption during the standby process, but also save area and interface resources, and is more suitable for modern large-scale integrated circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the structure of a memory unit in the first embodiment of the present invention.

[0037] Figure 2 It is a schematic diagram showing the memory unit in the first embodiment of the present invention working in the high-speed computing mode.

[0038] Figure 3 It is a schematic diagram showing the memory unit working in the cooperative storage mode in the first embodiment of the present invention.

[0039] Figure 4 It is a schematic diagram showing the memory unit working in the memristor mode in the first embodiment of the present invention.

[0040] Figure 5 Shown is a timing diagram of related signals of a memory unit in different working modes in the first embodiment of the present invention.

[0041] Figure 6 Shown is a structural schematic diagram of a memory array in Embodiment 1 of the present invention.

[0042] Figure 7 Shown is another structural schematic diagram of the memory array in the first embodiment of the present invention.

[0043] Figure 8 It is a schematic diagram of the structure of a memory unit in the second embodiment of the present invention.

[0044] Fig. 9 It is a schematic diagram showing the memory unit in the second embodiment of the present invention working in the high-speed computing mode.

[0045] Fig.10 It is a schematic diagram showing the memory unit in the second embodiment of the present invention working in the cooperative storage mode.

[0046] Fig.11 It is a schematic diagram showing the memory unit in the second embodiment of the present invention working in the memristor mode.

[0047] Fig.12It shows a timing diagram of related signals of the memory unit in different working modes in the second embodiment of the present invention.

[0048] Fig.13 Shown is a structural schematic diagram of a memory array in the second embodiment of the present invention.

[0049] Fig.14 Shown is another structural schematic diagram of a memory array in the second embodiment of the present invention.

[0050] Component number description

[0051] 10 Memory Array

[0052] 100 storage blocks

[0053] 110 Memory Cells

[0054] 111 Volatile In-Memory Computing Module

[0055] 111a Data latch unit

[0056] 112 Non-volatile in-memory computing module DETAILED DESCRIPTION

[0057] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] See also Figures 1 to 14 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0059] Embodiment 1

[0060] like Figure 1 As shown, this embodiment provides a memory unit 110, including a volatile in-memory computing module 111 and a non-volatile in-memory computing module 112; wherein, the volatile in-memory computing module 111 of this embodiment includes a static random access structure.

[0061] In one embodiment, the static random access structure includes a first gate transistor RS1, a second gate transistor RS2 and a data latch unit 111a.

[0062] The gate of the first selection tube RS1 is connected to the word line WL, the source of the first selection tube RS1 is connected to the first bit line BL1, the drain of the first selection tube RS1 is connected to the first end of the data latch part 111a and serves as the first data end of the static random access structure, recorded as the Q end, also known as the Q point, wherein the Q end (Q point) coincides with the first end of the data latch part 111a.

[0063] The gate of the second selection tube RS2 is connected to the word line WL, the source of the second selection tube RS2 is connected to the second bit line BL2, the drain of the second selection tube RS2 is connected to the second end of the data latch part 111a and serves as the second data end of the static random access structure, recorded as the QB end, also known as the QB point, wherein the QB end (QB point) coincides with the second end of the data latch part 111a.

[0064] The data latching unit 111a implements data latching based on a bistable circuit. In one example, the data latching unit 111a includes a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, and a second NMOS tube MN2, wherein the first PMOS tube MP1 and the first NMOS tube MN1 constitute a first inverter, the second PMOS tube MP2 and the second NMOS tube MN2 constitute a second inverter, and the first inverter and the second inverter are connected end to end to implement data latching; at this time, the static random access structure of this embodiment is a 6TSRAM structure, that is, the static random access structure of this embodiment includes six transistors, wherein the six transistors refer to the first selection tube RS1, the second selection tube RS2, the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube MN1, and the second NMOS tube MN2. Specifically, the gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1 and connected to the second end of the data latch part 111a, the source of the first PMOS transistor MP1 is connected to the power supply voltage VDD, the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 and serves as the first end of the data latch part 111a, and the source of the first NMOS transistor MN1 is connected to the reference ground; the gate of the second PMOS transistor MP2 is connected to the gate of the second NMOS transistor MN2 and connected to the first end of the data latch part 111a, the source of the second PMOS transistor MP2 is connected to the power supply voltage VDD, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2 and serves as the second end of the data latch part 111a, and the source of the second NMOS transistor MN2 is connected to the reference ground. It should be noted that in this embodiment, the PMOS transistor refers to a P-type metal oxide semiconductor field effect transistor, and the NMOS transistor refers to an N-type metal oxide semiconductor field effect transistor.

[0065] The non-volatile in-memory computing module 112 includes a switch tube SW and at least one memristor M, which are connected in series between two data terminals of the static random access structure.

[0066] When the number of memristors M is one:

[0067] In one embodiment, the gate of the switch tube SW is connected to the control line CL, the source of the switch tube SW is connected to the first data end of the static random access structure, i.e., the Q end, via the memristor M, and the drain of the switch tube SW is connected to the second data end of the static random access structure, i.e., the QB end; at this time, the memristor M is connected to the source of the switch tube SW.

[0068] In another embodiment, the gate of the switch tube SW is connected to the control line CL, the source of the switch tube SW is connected to the first data end of the static random access structure, that is, the Q end, and the drain of the switch tube SW is connected to the second data end of the static random access structure, that is, the QB end, via the memristor M; at this time, the memristor M is connected to the drain of the switch tube SW.

[0069] When the number of memristors M is greater than one:

[0070] In one embodiment, the gate of the switch tube SW is connected to the control line CL, the source of the switch tube SW is connected to the first data end of the static random access structure, i.e., the Q end, through each memristor M in turn, and the drain of the switch tube SW is connected to the second data end of the static random access structure, i.e., the QB end; at this time, each memristor M is connected to the source of the switch tube SW in series.

[0071] In another embodiment, the gate of the switch tube SW is connected to the control line CL, the source of the switch tube SW is connected to the first data end of the static random access structure, that is, the Q end, and the drain of the switch tube SW is connected to the second data end of the static random access structure, that is, the QB end, via each memristor M in turn; at this time, each memristor M is connected to the drain of the switch tube SW in series.

[0072] In another embodiment, the gate of the switch tube SW is connected to the control line CL, the source of the switch tube SW is connected to the first data terminal of the static random access structure via at least one memristor M, that is, the Q terminal, and the drain of the switch tube SW is connected to the second data terminal of the static random access structure via at least one memristor M, that is, the QB terminal; at this time, each memristor M is divided into two parts, some memristors M are connected to the source of the switch tube SW in series, and some memristors M are connected to the drain of the switch tube SW in series. The number of memristors M connected to the source of the switch tube SW is recorded as the first number, and the number of memristors M connected to the drain of the switch tube SW is recorded as the second number, then: the first number is greater than or equal to one, the second number is greater than or equal to one, and the first number can be greater than the second number, or less than the second number, or even equal to the second number, without limitation.

[0073] Among them, the memristor M has two or more resistance states, that is, the types of resistance states of the memristor M are greater than or equal to 2, so that in the memristor mode, multiple weights or data are calculated by the resistance values ​​corresponding to multiple resistance states to realize in-memory calculation. In practical applications, there are two commonly used adjustment methods to adjust the types of resistance states. The first adjustment method is to adjust the types of resistance states by adjusting the material of the storage medium in the memristor M, and the second adjustment method is to adjust the types of resistance states by adjusting the number of memristors M (connecting each memristor M in series, and the type of resistance state after adjustment is the sum of the types of resistance states of each memristor M). Of course, it is also feasible to combine the above two adjustment methods; however, for the case where the number of memristors M is one, the resistance state can only be adjusted by the above first adjustment method, and for the case where the number of memristors M is greater than one, the resistance state can be adjusted by at least one of the above two adjustment methods. In one example, the memristor M includes but is not limited to a magnetic memristor, a resistive memristor, a phase change memristor, a flash memory memristor or a ferroelectric memristor.

[0074] like Figures 2 to 4 As shown, this embodiment also provides an operation method of a memory unit 110, including a high-speed computing mode, a collaborative storage mode and a memristor mode; wherein the memory unit 110 is implemented using the structure described above.

[0075] For high-speed computing mode:

[0076] like Figure 2 As shown, the volatile in-memory computing module 111 (a static random access structure in this embodiment) is controlled to be turned on, and the non-volatile in-memory computing module 112 is controlled to be turned off, so that the memory unit 110 works in the high-speed computing mode. Specifically, power is supplied to the data latch unit 111a to turn on the static random access structure, the switch tube SW is turned off through the control line CL, the non-volatile in-memory computing module 112 is turned off, the first selection tube RS1 and the second selection tube RS2 are turned on through the word line WL, and the data latch unit 111a is read and written through the first bit line BL1 and the second bit line BL2; at this time, the memory unit 110 works in the high-speed computing mode in a 6T mode, that is, the memory unit 110 works in the high-speed computing mode in a six-transistor mode, wherein the six transistors refer to the first selection tube RS1, the second selection tube RS2, the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube MN1 and the second NMOS tube MN2. In this mode, since the switch tube SW is turned off and the memristor M is in an open circuit, the static random access structure can maintain independent operation without interference, avoiding the problem of asymmetric load. At the same time, when the static random access structure performs read and write operations, there is no leakage path between the memristor M and the static random access structure, which can reduce leakage current and thus reduce static power consumption.

[0077] In one example, the static random access structure is turned on by providing the power supply voltage VDD to the data latch unit 111a, and the switch tube SW is turned off by setting the control line CL to a low voltage, so that the non-volatile memory calculation module 112 is turned off. At this time, the memristor M maintains a high resistance state; the first selection tube RS1 and the second selection tube RS2 are turned on by setting the word line WL to a high voltage, and the data latch unit 111a is read and written by controlling the voltage of the first bit line BL1 and the second bit line BL2. Figure 5 Taking the read and write timing shown in the time period T0-T1 as an example, the read and write stages are demonstrated through four timing pulses; in the first two write pulse cycles, the control line CL is set to a low voltage, the word line WL is set to a high voltage, the first bit line BL1 is set to a high voltage, and the second bit line BL2 is set to a low voltage, so that the data "1" is written to the Q point, that is, written into the data latch 111a; in the last two read pulse cycles, the control line CL maintains a low voltage, the word line WL maintains a high voltage, the first bit line BL1 and the second bit line BL2 are simultaneously set to a high voltage, and the data "1" is read from the data latch 111a through the charge change on the bit line. It should be noted that Figure 5 This is just an example and does not limit the correspondence between the two bit line voltages and data in the read and write operations. In fact, it is also feasible to design the voltages of the two bit lines to correspond to writing data "0" and reading data "0", which is completely defined by the user.

[0078] For collaborative storage mode:

[0079] like Figure 3As shown, the volatile in-memory calculation module 111 (a static random access structure in this embodiment) is controlled to be turned on, and the non-volatile in-memory calculation module 112 is controlled to be turned on, so that the memory unit 110 works in the cooperative storage mode. Specifically, power is supplied to the data latch unit 111a to turn on the static random access structure, the switch tube SW is turned on through the control line CL, the non-volatile in-memory calculation module 112 is turned on, the first selection tube RS1 and the second selection tube RS2 are turned off through the word line WL, and the data in the data latch unit 111a is written into the memristor M based on the voltage difference across the data latch unit 111a; at this time, the memory unit 110 works in the cooperative storage mode in a 5T1M manner, that is, the memory unit 110 works in the cooperative storage mode in a five-transistor one-memristor manner, wherein the five transistors refer to the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube MN1, the second NMOS tube MN2 and the switch tube SW. Furthermore, after writing the data into the memristor M, the data latch unit 111a is powered off to turn off the static random access structure, the first gate tube RS1 and the second gate tube RS2 are turned on through the word line WL, and the memristor M is read through the first bit line BL1 and the second bit line BL2. In this mode, the data in the static random access structure can be written into the memristor M through self-backup for power-off preservation. Compared with the traditional von Neumann architecture that needs to be transmitted to the peripheral device through the memory and bus for data storage and backup, this mode can greatly reduce the time and distance of data transmission, realize the reduction of standby static energy consumption, data transfer energy consumption and delay, and has the advantages of low delay and low energy loss.

[0080] In one example, the power supply voltage VDD is provided to the data latch 111a to enable the static random access structure, the control line CL is set to a high voltage to turn on the switch tube SW, and the non-volatile memory calculation module 112 is turned on, and the word line WL is set to a low voltage to turn off the first selection tube RS1 and the second selection tube RS2, thereby preventing the external environment from applying stimulation to the memory unit 110; the data latch 111a maintains data storage, at this time, the data is stored at the Q point, and at the same time, the non-volatile memory calculation module 112 is turned on because the switch tube SW is turned on, and the data latch 111a and the non-volatile memory calculation module 112 form a path, and because The voltage difference between the Q point and the QB point is +VDD or -VDD, so the data stored in the data latch 111a can be written into the memristor M to complete self-backup; for example, when data "1" is stored in the data latch unit 111a, the Q point is a high voltage, the QB point is a low voltage, the voltage difference between the Q point and the QB point is +VDD, and the memristor M is set to a low resistance state, indicating that the data "1" is written into the memristor M. When data "0" is stored in the data latch unit 111a, the Q point is a low voltage, the QB point is a high voltage, the voltage difference between the Q point and the QB point is -VDD, and the memristor M is set to a high resistance state, indicating that the data "0" is written into the memristor M. After the self-backup is completed, the data latch unit 111a is powered off to turn off the static random access structure. At this time, the data can still be kept in the memristor M to achieve power-off preservation; when reading data, the first and second selection transistors RS1 and RS2 are turned on by setting the word line WL to a high voltage, and the memristor M is read by controlling the voltage of the first and second bit lines BL1 and BL2. Figure 5 Taking the read and write timing shown in the time period T1 to T2 as an example, the read and write stages are demonstrated through four timing pulses; wherein, in the first two write pulse cycles, power is supplied to the data latch unit 111a, the control line CL is set to a high voltage, and the word line WL is set to a low voltage. Since the voltage difference between the Q point and the QB point is +VDD, the memristor M is set to a low resistance state, thereby realizing that the data "1" in the data latch unit 111a is written into the memristor M; in the second two read pulse cycles, the data latch unit 111a is powered off, the control line CL maintains a high voltage, the word line WL changes from a low voltage to a high voltage, the second bit line BL2 is set to a low voltage and the first bit line BL1 is set to a read voltage (the read voltage is lower than the critical voltage of the memristor M), and the data "1" is read from the memristor M.

[0081] For memristor mode:

[0082] like Figure 4As shown, the volatile in-memory computing module 111 (in this embodiment, a static random access structure, specifically a data latch unit 111a) is controlled to be turned off, and the non-volatile in-memory computing module 112 is controlled to be turned on, so that the memory unit 110 works in the memristor mode. Specifically, the data latch unit 111a is powered off to turn off the static random access structure, the switch tube SW is turned on through the control line CL, the non-volatile in-memory computing module 112 is turned on, the first selection tube RS1 and the second selection tube RS2 are turned on through the word line WL, and the memristor M is read and written through the first bit line BL1 and the second bit line BL2; at this time, the memory unit 110 works in the memristor mode in a 3T1M mode, that is, the memory unit 110 works in the memristor mode in a three-transistor one-memristor mode, wherein the three transistors refer to the first selection tube RS1, the second selection tube RS2 and the switch tube SW. Furthermore, when the memristor M is read and written through the first bit line BL1 and the second bit line BL2: if the voltage difference applied to the two ends of the memory cell 110 is less than the critical voltage of the memristor M, then the memristor M is read, that is, the resistance value of the memristor M is read without changing the resistance state of the memristor M; if the voltage difference applied to the two ends of the memory cell 110 is a positive value of the power supply voltage, that is, +VDD, then the memristor M is set to a first resistance state, for example, a low resistance state, corresponding to a resistance value of RL; if the voltage difference applied to the two ends of the memory cell 110 is a positive value of the power supply voltage, that is, +VDD, then the memristor M is set to a first resistance state, for example, a low resistance state, corresponding to a resistance value of RL; is a negative value of the power supply voltage, i.e., -VDD, then the memristor M is set to the second resistance state, for example, the high resistance state, and the corresponding resistance value is RH; if the voltage difference applied to both ends of the memory cell 110 is between the absolute value of the power supply voltage and the critical voltage of the memristor M, the memristor M is set to the third resistance state, for example, the intermediate resistance state, and the corresponding resistance value is RM, wherein the third resistance state is between the first resistance state and the second resistance state, and the resistance value satisfies the formula RM=RL+(RH-RL) / N, where N is the type of resistance state of the memristor M. In this mode, the resistance state of the memristor M can be modulated through the first bit line BL1 and the second bit line BL2 to achieve the adjustment and calculation of different weights or data in the memory; in addition, there is no need to bear the dynamic and static power consumption when the static random access structure works, which is conducive to further energy saving.

[0083] In one example, the data latch unit 111a is powered off to turn off the static random access structure, and the switch tube SW is turned on by setting the control line CL to a high voltage to turn on the non-volatile memory calculation module 112; the first selection tube RS1 and the second selection tube RS2 are turned on by setting the word line WL to a high voltage, and the data read and write operations are performed on the memristor M by controlling the voltage of the first bit line BL1 and the second bit line BL2. Figure 5Taking the read and write timing shown in the time period T2 to T3 as an example, the read and write stages are demonstrated through four timing pulses; in the first two write pulse cycles, the control line CL is set to a high voltage, the word line WL is set to a high voltage, the first bit line BL1 is set to a high voltage, and the second bit line BL2 is set to a low voltage, and the memristor M is set to a low resistance state, so that the data "1" is written into the memristor M; in the last two read pulse cycles, the control line CL maintains a high voltage, the word line WL maintains a high voltage, the second bit line BL2 is set to a high voltage, and the first bit line BL1 is set to a read voltage (the read voltage is lower than the critical voltage of the memristor M), and the data "1" is read from the memristor M. It should be noted that in the write pulse cycle, the second bit line BL2 is usually set to a low voltage, and by providing different values ​​of write voltage to the first bit line BL1, the memristor M can have different resistance states.

[0084] In actual applications, the memory unit 110 can be adapted to different application scenarios by switching between the above three working modes, so as to meet the working requirements of the cloud and the edge; for example, in computing and storage intensive operations such as large-scale training in the cloud, a high-speed computing mode can be used, and in applications where the system is in standby or the local array is dormant, a collaborative storage mode can be used; in applications such as the edge that have special requirements for low power consumption and miniaturization, a memristor mode can be used; of course, different working modes can also be used in the same application scenario. For example, in computing and storage intensive operations such as large-scale training in the cloud, both a high-speed computing mode and a collaborative storage mode can be used.

[0085] like Figure 6 and Figure 7 As shown, this embodiment also provides a memory array 10, including a plurality of memory blocks 100, each memory block 100 is arranged in an array in rows and columns; wherein the memory block 100 includes at least one memory cell 110, and the memory cell 110 is implemented using the structure described above. Expanding and integrating the memory block 100 in a two-dimensional plane can adapt to the application scenario of large-scale integrated circuits, which is conducive to improving storage capacity.

[0086] In one embodiment, Figure 6As shown, the memory block 100 includes a memory cell 110; in this case, the memory array 10 can be regarded as including a plurality of memory cells 110, for example, including (m*n) memory cells 110, wherein the (m*n) memory cells 110 are arranged in an array according to m columns and n rows, wherein each memory cell 110 in the same row shares a control line CL and a word line WL, and each memory cell 110 in the same column shares a first bit line BL1 and a second bit line BL2. In the above embodiment, for any memory cell 110, mode switching control and read / write operation control are performed through four lines, namely, the control line CL, the word line WL, the first bit line BL1 and the second bit line BL2.

[0087] In another embodiment, if Figure 7 As shown, the memory block 100 includes two memory cells 110. In this case, the memory array 10 can be regarded as including a number of memory blocks 100, for example, including (m*n) memory blocks 100, wherein the (m*n) memory blocks 100 are arranged in an array according to m columns and n rows; wherein the two memory cells 110 are arranged in a mirror image and are used to store complementary data information. In one example, for any memory block 100, the two memory cells 110 share a control line CL, a word line WL, and a second bit line BL2, that is, any memory block 100 corresponds to a control line CL, a word line WL, two first bit lines BL1, and a second bit line BL2, a total of five lines. For the convenience of distinction, 1 and 3 are used to mark the two first bit lines respectively in the figure. In the above embodiment, for each storage block 100 in the memory array 10, each storage block 100 in the same row shares a control line CL and a word line WL, and each storage block 100 in the same column shares two first bit lines BL1 and a second bit line; for each memory cell 110 in the storage block 100, mode switching control and read / write operation control are performed through four lines, namely, the control line CL, the word line WL, the first bit line BL1, and the second bit line BL2. Mirroring the two memory cells 110 in the storage block 100 is conducive to improving the integration density and the read margin. For example, in the memristor mode, the two memory cells 110 in the mirrored arrangement can be respectively set to opposite resistance states (a high resistance state and a low resistance state) through two complementary memristors M, thereby increasing the read margin.

[0088] This embodiment also provides a terminal suitable for in-memory computing, including a processor and a memory array 10; wherein the memory array 10 is implemented using the structure described above and is used to store data or computer programs; the processor is used to read data from the memory array 10 or execute the computer program stored in the memory array 10.

[0089] In one embodiment, the processor may be a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), an AI (Artificial Intelligence), an NPU (Neural Network Processing Unit), an ISP (Image Signal Processor), a DPU (Display Processing Unit), a VPU (Video Processing Unit), a DSP (Digital Signal Processing) data processing core, etc. It may also be a processor chip used in some scenarios such as large-scale data computing. Of course, the above are only examples and should not be a limitation to the present application.

[0090] Embodiment 2

[0091] like Figure 8 As shown, this embodiment provides a memory unit 110, including a volatile in-memory computing module 111 and a non-volatile in-memory computing module 112; wherein, the volatile in-memory computing module 111 of this embodiment includes a dynamic random access structure.

[0092] In one embodiment, the dynamic random access structure includes a control transistor TC and a capacitor C. Among them: the gate of the control transistor TC is connected to the word line WL, the source of the control transistor TC is connected to the bit line BL and serves as the data end of the dynamic random access structure, recorded as the Q end, also known as the Q point, the drain of the control transistor TC is connected to the upper plate of the capacitor C, and the lower plate of the capacitor C is connected to the reference ground.

[0093] The non-volatile in-memory computing module 112 includes a switch tube SW and at least one memristor M, which are connected in series between the data terminal of the dynamic random access structure and a reference ground.

[0094] When the number of memristors M is one:

[0095] In one embodiment, the gate of the switch tube SW is connected to the control line CL, the source of the switch tube SW is connected to the data end of the dynamic random access structure, that is, the Q end, via the memristor M, and the drain of the switch tube SW is connected to the reference ground; at this time, the memristor M is connected to the source of the switch tube SW.

[0096] In another embodiment, the gate of the switch tube SW is connected to the control line CL, the source of the switch tube SW is connected to the data end of the dynamic random access structure, that is, the Q end, and the drain of the switch tube SW is connected to the reference ground via the memristor M; at this time, the memristor M is connected to the drain of the switch tube SW.

[0097] When the number of memristors M is greater than one:

[0098] In one embodiment, the gate of the switch tube SW is connected to the control line CL, the source of the switch tube SW is connected to the data end of the dynamic random access structure, that is, the Q end, through each memristor M in turn, and the drain of the switch tube SW is connected to the reference ground; at this time, each memristor M is connected to the source of the switch tube SW in series.

[0099] In another embodiment, the gate of the switch tube SW is connected to the control line CL, the source of the switch tube SW is connected to the data end of the dynamic random access structure, that is, the Q end, and the drain of the switch tube SW is connected to the reference ground via each memristor M in turn; at this time, each memristor M is connected to the drain of the switch tube SW in series.

[0100] In another embodiment, the gate of the switch tube SW is connected to the control line CL, the source of the switch tube SW is connected to the data end of the dynamic random access structure, that is, the Q end, via at least one memristor M, and the drain of the switch tube SW is connected to the reference ground via at least one memristor M; at this time, each memristor M is divided into two parts, some memristors M are connected to the source of the switch tube SW in series, and some memristors M are connected to the drain of the switch tube SW in series. The number of memristors M connected to the source of the switch tube SW is recorded as the first number, and the number of memristors M connected to the drain of the switch tube SW is recorded as the second number, then: the first number is greater than or equal to one, the second number is greater than or equal to one, and the first number can be greater than the second number, or less than the second number, or even equal to the second number, without limitation.

[0101] Among them, the memristor M has two or more resistance states, that is, the type of resistance state of the memristor M is greater than or equal to 2, so that in the memristor mode, multiple weights or data are calculated by the resistance values ​​corresponding to multiple resistance states to realize in-memory calculation. In practical applications, there are two commonly used adjustment methods to adjust the type of resistance state. The first adjustment method is to adjust the type of resistance state by adjusting the material of the storage medium in the memristor M, and the second adjustment method is to adjust the type of resistance state by adjusting the number of memristors M (connecting each memristor M in series, and the type of resistance state after adjustment is the sum of the types of resistance states of each memristor M). Of course, it is also feasible to combine the above two adjustment methods; however, for the case where the number of memristors M is one, the resistance state can only be adjusted by the above first adjustment method, and for the case where the number of memristors M is greater than one, the resistance state can be adjusted by at least one of the above two adjustment methods. In one example, the memristor M includes but is not limited to a magnetic memristor, a resistive memristor, a phase change memristor, a flash memory memristor or a ferroelectric memristor.

[0102] like Figures 9 to 11 As shown, this embodiment also provides an operation method of a memory unit 110, including a high-speed computing mode, a collaborative storage mode and a memristor mode; wherein the memory unit 110 is implemented using the structure described in the second embodiment.

[0103] For high-speed computing mode:

[0104] like Fig. 9 As shown, the volatile in-memory computing module 111 (a dynamic random access structure in this embodiment) is controlled to be turned on, and the non-volatile in-memory computing module 112 is controlled to be turned off, so that the memory unit 110 works in a high-speed computing mode. Specifically, the control tube TC is turned on through the word line WL to turn on the dynamic random access structure, the switch tube SW is turned off through the control line CL to turn off the non-volatile in-memory computing module 112, and the capacitor C is read and written through the bit line BL; at this time, the memory unit 110 works in a high-speed computing mode in a 1T1C manner, that is, the memory unit 110 works in a high-speed computing mode in a one-transistor-one-capacitor manner, where one transistor refers to the control tube TC. In this mode, since the switch tube SW is turned off, the memristor M is in an open circuit, so the dynamic random access structure can maintain independent operation without interference, avoiding the problem of asymmetric load. At the same time, when the dynamic random access structure performs read and write operations, there is no leakage path between the memristor M and the dynamic random access structure, which can reduce leakage current and thus reduce static power consumption.

[0105] In one example, the control tube TC is turned on by setting the word line WL to a high voltage, so that the dynamic random access structure is turned on, and the switch tube SW is turned off by setting the control line CL to a low voltage, so that the non-volatile memory calculation module 112 is turned off. At this time, the memristor M maintains a high resistance state unchanged; data reading and writing operations are performed on the capacitor C through the bit line BL. For example, during the write operation, the capacitor C is charged by setting the voltage of the bit line BL to +VDD to write data "1", and the capacitor C is discharged by setting the voltage of the bit line BL to -VDD to write data "0". During the read operation, the data "0" or data "1" stored in the capacitor C is read by setting the bit line BL to a read voltage (the read voltage is less than the absolute value of the power supply voltage). Fig.12 Taking the read and write timing shown in the time period T0-T1 as an example, the read and write stages are demonstrated through four timing pulses; wherein, in the first two write pulse cycles, the control line CL is set to a low voltage, the word line WL is set to a high voltage, and the bit line BL is set to a high voltage, so that the data "1" is written into the capacitor C; in the last two read pulse cycles, the control line CL maintains a low voltage, the word line WL maintains a high voltage, the bit line BL is set to a read voltage, and the data "1" is read from the capacitor C.

[0106] For collaborative storage mode:

[0107] like Fig.10 As shown, the volatile in-memory computing module 111 (a dynamic random access structure in this embodiment) is controlled to be turned on, and the non-volatile in-memory computing module 112 is controlled to be turned on, so that the memory unit 110 works in the cooperative storage mode. Specifically, the control tube TC is turned on through the word line WL to turn on the dynamic random access structure, and the switch tube SW is turned on through the control line CL to turn on the non-volatile in-memory computing module 112, and the data in the capacitor C is written into the memristor M based on the voltage difference across the capacitor; at this time, the memory unit 110 works in the cooperative storage mode in a 2T1C1M manner, that is, the memory unit 110 works in the cooperative storage mode in a two-transistor, one-capacitor, and one-memristor manner, wherein the two transistors refer to the control tube TC and the switch tube SW. Further, after the data is written into the memristor M, the control tube TC is turned off through the word line WL to turn off the dynamic random access structure, and the memristor M is read through the bit line BL. In this mode, the data in the dynamic random access structure can be written into the memristor M through self-backup for power-off preservation. Compared with the traditional von Neumann architecture that needs to be transmitted to the peripherals through the memory and bus for data storage and backup, this mode can greatly reduce the time and distance of data transmission, achieve the reduction of standby static energy consumption, data transfer energy consumption and delay, and has the advantages of low latency and low energy loss.

[0108] In one example, the control tube TC is turned on by setting the word line WL to a high voltage, so that the dynamic random access structure is turned on, and the switch tube SW is turned on by setting the control line CL to a high voltage, so that the non-volatile memory calculation module 112 is turned on, and no excitation or floating is applied to the bit line BL; the capacitor C maintains data storage, and the dynamic random access structure is turned on because the control tube TC is turned on, and the data is stored at the Q point. At the same time, the non-volatile memory calculation module 112 is turned on because the switch tube SW is turned on, and the dynamic random access structure and the non-volatile memory calculation module 112 are connected. 2 forms a path, and because the voltage difference between the Q point and the reference ground is +VDD or -VDD, the data stored in the capacitor C can be written into the memristor M to complete the self-backup; for example, when the data "1" is stored in the capacitor C, the voltage difference between the Q point and the reference ground is +VDD, and the memristor M is set to a low resistance state, indicating that the data "1" is written into the memristor M. When the data "0" is stored in the capacitor C, the voltage difference between the Q point and the reference ground is -VDD, and the memristor M is set to a high resistance state, indicating that the data "0" is written into the memristor M. After the self-backup is completed, the control tube TC is turned off by setting the word line WL to a low voltage, so that the dynamic random access structure is turned off. At this time, the data can still be kept in the memristor M to achieve power-off preservation, and the memristor M can be read directly through the bit line BL later. Fig.12 Taking the read and write timing shown in the time period T1 to T2 as an example, the read and write stages are demonstrated through four timing pulses; wherein, in the first two write pulse cycles, the control line CL is set to a high voltage, and the word line WL is set to a high voltage. Since the voltage difference between the Q point and the reference ground is +VDD, the memristor M is set to a low resistance state, and the data "1" is written into the memristor M; in the last two read pulse cycles, the control line CL maintains a high voltage, and the word line WL changes from a high voltage to a low voltage, and the bit line BL is set to a read voltage (the read voltage is lower than the critical voltage of the memristor M), and the data "1" is read from the memristor M.

[0109] For memristor mode:

[0110] like Fig.11As shown, the volatile in-memory computing module 111 (a dynamic random access structure in this embodiment) is controlled to be turned off, and the non-volatile in-memory computing module 112 is controlled to be turned on, so that the memory unit 110 works in the memristor mode. Specifically, the control tube TC is turned off through the word line WL to turn off the dynamic random access structure, the switch tube SW is turned on through the control line CL to turn on the non-volatile in-memory computing module 112, and the memristor M is read and written through the bit line BL; at this time, the memory unit 110 works in the memristor mode in a 1T1M mode, that is, the memory unit 110 works in the memristor mode in a one-transistor one-memristor mode, where one transistor refers to the switch tube SW. Furthermore, when the memristor M is read and written through the bit line BL: if the voltage difference applied to the two ends of the memory cell 110 is less than the critical voltage of the memristor M, then the memristor M is read, that is, the resistance value of the memristor M is read without changing the resistance state of the memristor M; if the voltage difference applied to the two ends of the memory cell 110 is a positive value of the power supply voltage, that is, +VDD, then the memristor M is set to a first resistance state, for example, a low resistance state, corresponding to a resistance value of RL; if the voltage difference applied to the two ends of the memory cell 110 is a positive value of the power supply voltage, that is, +VDD, then the memristor M is set to a first resistance state, for example, a low resistance state, corresponding to a resistance value of RL; If the voltage difference applied to the memory cell 110 is between the absolute value of the power supply voltage and the critical voltage of the memristor M, the memristor M is set to the third resistance state, for example, the middle resistance state, and the corresponding resistance value is RM, wherein the third resistance state is between the first resistance state and the second resistance state, and the resistance value satisfies the formula RM=RL+(RH-RL) / N, where N is the type of resistance state of the memristor M. In this mode, the resistance state of the memristor M can be modulated through the bit line BL to realize the adjustment and calculation of different weights or data in the memory; in addition, there is no need to bear the dynamic and static power consumption when the dynamic random access structure is working, which is conducive to further energy saving.

[0111] In one example, the control tube TC is turned off by setting the word line WL to a low voltage, so that the dynamic random access structure is turned off, and the switch tube SW is turned on by setting the control line CL to a high voltage, so that the non-volatile memory calculation module 112 is turned on, and the data reading and writing operation is performed on the memristor M by controlling the voltage of the bit line BL. The relevant voltage control is as described above and will not be repeated here. Fig.12Taking the read and write timing shown in the time period T2 to T3 as an example, the read and write stages are demonstrated through four timing pulses; in the first two write pulse cycles, the control line CL is set to a high voltage, the word line WL is set to a low voltage, and the bit line BL is set to a high voltage, and the memristor M is set to a low resistance state, so that the data "1" is written into the memristor M; in the last two read pulse cycles, the control line CL maintains a high voltage, the word line WL maintains a low voltage, and the bit line BL is set to a read voltage (the read voltage is lower than the critical voltage of the memristor M), and the data "1" is read from the memristor M. It should be noted that in the write pulse cycle, by providing different values ​​of write voltage to the bit line BL, the memristor M can have different resistance states.

[0112] In actual applications, the memory unit 110 can be adapted to different application scenarios by switching between the above three working modes, so as to meet the working requirements of the cloud and the edge; for example, in computing and storage intensive operations such as large-scale training in the cloud, a high-speed computing mode can be used, and in applications where the system is in standby or the local array is dormant, a collaborative storage mode can be used; in applications such as the edge that have special requirements for low power consumption and miniaturization, a memristor mode can be used; of course, different working modes can also be used in the same application scenario. For example, in computing and storage intensive operations such as large-scale training in the cloud, both a high-speed computing mode and a collaborative storage mode can be used.

[0113] like Fig.13 and Fig.14 As shown, this embodiment further provides a memory array 10, including a plurality of memory blocks 100, each memory block 100 is arranged in an array in rows and columns; wherein the memory block 100 includes at least one memory cell 110, and the memory cell 110 is implemented using the structure described in the second embodiment. Expanding and integrating the memory block 100 in a two-dimensional plane can adapt to the application scenario of large-scale integrated circuits, which is conducive to improving the storage capacity.

[0114] In one embodiment, Fig.13 As shown, the memory block 100 includes a memory cell 110; in this case, the memory array 10 can be regarded as including a plurality of memory cells 110, for example, including (m*n) memory cells 110, wherein the (m*n) memory cells 110 are arranged in an array according to m columns and n rows, wherein the memory cells 110 in the same row share a control line CL and a word line WL, and the memory cells 110 in the same column share a bit line BL. In the above embodiment, for any memory cell 110, mode switching control and read / write operation control are performed through the three lines of the control line CL, the word line WL, and the bit line BL.

[0115] In another embodiment, if Fig.14As shown, the memory block 100 includes two memory cells 110. In this case, the memory array 10 can be regarded as including a number of memory blocks 100, for example, including (m*n) memory blocks 100, wherein the (m*n) memory blocks 100 are arranged in an array according to m columns and n rows; wherein the two memory cells 110 are arranged in a mirror image and are used to store complementary data information. In one example, for any memory block 100, the two memory cells 110 share a control line CL and a word line WL, that is, any memory block 100 corresponds to a control line CL, a word line WL and two bit lines BL, a total of four lines. For the convenience of distinction, 1 and 2 are used in the figure to mark the two bit lines respectively. In the above embodiment, for each storage block 100 in the memory array 10, each storage block 100 in the same row shares a control line CL and a word line WL, and each storage block 100 in the same column shares two bit lines; for each memory cell 110 in the storage block 100, mode switching control and read / write operation control are performed through three lines: a control line CL, a word line WL, and a bit line BL. Mirroring the two memory cells 110 in the storage block 100 is conducive to improving the integration density and the read margin. For example, in the memristor mode, the two memory cells 110 in the mirror arrangement can be set to opposite resistance states (a high resistance state and a low resistance state) through two complementary memristors M, thereby increasing the read margin.

[0116] This embodiment also provides a terminal suitable for in-memory computing, including a processor and a memory array 10; wherein the memory array 10 is implemented using the structure described above and is used to store data or computer programs; the processor is used to read data from the memory array 10 or execute the computer program stored in the memory array 10.

[0117] In one embodiment, the processor may be a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), an AI (Artificial Intelligence), an NPU (Neural Network Processing Unit), an ISP (Image Signal Processor), a DPU (Display Processing Unit), a VPU (Video Processing Unit), a DSP (Digital Signal Processing) data processing core, etc. It may also be a processor chip used in some scenarios such as large-scale data computing. Of course, the above are only examples and should not be a limitation to the present application.

[0118] In summary, a memory unit, a memory array, a terminal and an operation method of the present invention, through the design of a volatile in-memory computing module and a non-volatile in-memory computing module, use a minimum number of devices and control lines, and realize three working modes in one memory unit, namely, a high-speed computing mode, a collaborative storage mode and a memristor mode, which can not only improve the data transmission speed, reduce the dynamic transmission power consumption during the operation process and the static power consumption during the standby process, but also save area and interface resources, and are more suitable for modern large-scale integrated circuit design. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0119] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A memory cell, characterized in that: It includes a volatile in-memory computing module and a non-volatile in-memory computing module, wherein: The volatile in-memory computing module includes a static random access structure or a dynamic random access structure; the non-volatile in-memory computing module includes a switch tube and at least one memristor, which are connected in series between two data ends of the static random access structure or between the data end and a reference ground of the dynamic random access structure.

2. The memory unit according to claim 1, characterized in that The static random access structure includes a first gate tube, a second gate tube and a data latch unit, wherein: the gate of the first gate tube is connected to the word line, the source of the first gate tube is connected to the first bit line, the drain of the first gate tube is connected to the first end of the data latch unit and serves as the first data end of the static random access structure; the gate of the second gate tube is connected to the word line, the source of the second gate tube is connected to the second bit line, and the drain of the second gate tube is connected to the second end of the data latch unit and serves as the second data end of the static random access structure.

3. The memory unit according to claim 2, characterized in that The data latch unit includes a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein: the gate of the first PMOS tube is connected to the gate of the first NMOS tube and connected to the second end of the data latch unit, the source of the first PMOS tube is connected to the power supply voltage, the drain of the first PMOS tube is connected to the drain of the first NMOS tube and serves as the first end of the data latch unit, and the source of the first NMOS tube is connected to the reference ground; the gate of the second PMOS tube is connected to the gate of the second NMOS tube and connected to the first end of the data latch unit, the source of the second PMOS tube is connected to the power supply voltage, the drain of the second PMOS tube is connected to the drain of the second NMOS tube and serves as the second end of the data latch unit, and the source of the second NMOS tube is connected to the reference ground.

4. The memory unit according to claim 1, characterized in that The dynamic random access structure includes a control tube and a capacitor, wherein: the gate of the control tube is connected to the word line, the source of the control tube is connected to the bit line and serves as the data end of the dynamic random access structure, the drain of the control tube is connected to the upper plate of the capacitor, and the lower plate of the capacitor is connected to the reference ground.

5. The memory cell according to claim 1, wherein: When the number of the memristors is one, the memristor is connected to the source or drain of the switch tube; when the number of the memristors is greater than one, the memristor is connected to the source and / or drain of the switch tube; wherein the gate of the switch tube is connected to the control line.

6. The memory unit according to claim 1 or 5, characterized in that The memristor includes a magnetic memristor, a resistive memristor, a phase-change memristor, a flash memory memristor or a ferroelectric memristor, and the memristor has two or more resistance states.

7. A memory array, characterized in that: It comprises a plurality of storage blocks, each of which is arranged in an array in rows and columns, wherein the storage block comprises at least one memory unit according to any one of claims 1 to 6.

8. The memory array according to claim 7, wherein: The storage block includes two memory cells, wherein the two memory cells are arranged in a mirror image and are used to store complementary data information.

9. The memory array according to claim 8, wherein: When the volatile in-memory computing module includes a static random access structure, the two memory units share a control line, a word line and a second bit line; when the volatile in-memory computing module includes a dynamic random access structure, the two memory units share a control line and a word line.

10. A terminal, characterized in that: The method comprises a processor and a memory array as claimed in any one of claims 7 to 9.

11. A method for operating a memory cell according to any one of claims 1 to 6, characterized in that: include: Controlling the volatile in-memory computing module to be turned on, and controlling the non-volatile in-memory computing module to be turned off, so that the memory unit operates in a high-speed computing mode; Controlling the volatile in-memory computing module to start, and controlling the non-volatile in-memory computing module to start, so that the memory unit works in a collaborative storage mode; The volatile in-memory computing module is controlled to be turned off, and the non-volatile in-memory computing module is controlled to be turned on, so that the memory unit operates in a memristor mode.

12. The method for operating a memory cell according to claim 11, characterized in that: When the volatile in-memory computing module includes a static random access structure, and the static random access structure includes a first strobe tube, a second strobe tube and a data latch unit: In the high-speed computing mode, power is supplied to the data latch unit, the switch tube is turned off through the control line, and the first selection tube and the second selection tube are turned on through the word line. At this time, the memory unit works in a 6T mode, and the data latch unit is read and written through the first bit line and the second bit line; In the collaborative storage mode, power is supplied to the data latch unit, the switch tube is turned on through the control line, and the first gating tube and the second gating tube are turned off through the word line. At this time, the memory unit works in a 5T1M mode, and based on the voltage difference across the data latch unit, the data in the data latch unit is written into the memristor; In the memristor mode, the data latch unit is powered off, the switch tube is turned on through the control line, and the first selection tube and the second selection tube are turned on through the word line. At this time, the memory unit works in 3T1M mode, and the memristor is read and written through the first bit line and the second bit line.

13. The method for operating a memory cell according to claim 12, characterized in that: In the collaborative storage mode, after data is written into the memristor, the method further includes: powering off the data latch unit, turning on the first and second gating tubes through the word line, and performing a read operation on the memristor through the first and second bit lines.

14. The method for operating a memory cell according to claim 11, characterized in that: When the volatile in-memory computing module includes a dynamic random access structure, and the dynamic random access structure includes a control tube and a capacitor: In the high-speed computing mode, the switch tube is turned off through the control line, and the control tube is turned on through the word line. At this time, the memory unit works in a 1T1C mode, and the capacitor is read and written through the bit line; In the collaborative storage mode, the switch tube is turned on through the control line, and the control tube is turned on through the word line. At this time, the memory unit works in a 2T1C1M mode, and the data in the capacitor is written into the memristor based on the voltage difference across the capacitor; In the memristor mode, the switch tube is turned on through the control line and the control tube is turned off through the word line. At this time, the memory unit works in 1T1M mode and the memristor is read and written through the bit line.

15. The method for operating a memory cell according to claim 14, characterized in that: In the collaborative storage mode, after the data is written into the memristor, the method further includes: turning off the control transistor through the word line, and performing a read operation on the memristor through the bit line.

16. The method for operating a memory cell according to any one of claims 12 to 15, characterized in that: In the memristor mode, when the memristor is read and written: If the voltage difference applied to both ends of the memory cell is less than the critical voltage of the memristor, a read operation is performed on the memristor without changing the resistance state of the memristor; If the voltage difference applied to both ends of the memory cell is a positive value of the power supply voltage, setting the memristor to a first resistance state; If the voltage difference applied across the memory cell is a negative value of the power supply voltage, placing the memristor in a second resistance state; If the voltage difference applied to the two ends of the memory unit is between the absolute value of the power supply voltage and the critical voltage of the memristor, the memristor is set to a third resistance state, wherein the third resistance state is between the first resistance state and the second resistance state.

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