DDR4 function test system and method
By designing the DDR4 functional test system, using the FPGA module to connect with DDR4, sending and receiving test signals to evaluate storage performance, the problem that existing test devices cannot evaluate DDR4 storage performance is solved, and a comprehensive evaluation and rapid judgment of DDR4 storage performance is achieved.
Patent Information
- Application Number
- CN202411601043.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-11
- Publication Date
- 2025-03-07
AI Technical Summary
The existing DDR4 memory function test device cannot fully evaluate the storage performance of DDR4, and can only test whether the module is working normally.
A DDR4 functional test system is designed, and it is connected to the DDR4 to be tested using the FPGA module. By sending an input test signal and receiving the output test signal, the stored data information of the DDR4 is obtained, thereby evaluating its storage performance.
It realizes a comprehensive evaluation of DDR4 storage performance, can quickly judge the storage performance of DDR4, and improves the universality and adaptability of the test system.
Smart Images
Figure CN119580814A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of memory function testing, and in particular to a DDR4 function testing system and method. Background Art
[0002] DDR4 (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory) is a double data rate fourth generation synchronous dynamic random access memory card, a storage medium used in computer systems. DDR4 needs to be performance tested after production, but the current testing equipment can only test whether each module on DDR4 can work normally, but cannot evaluate the storage performance of DDR4. Summary of the invention
[0003] In view of this, the purpose of this application is to propose a DDR4 functional test system and method to evaluate the storage performance of DDR4.
[0004] Based on the above purpose, the present application provides a DDR4 function test system, including:
[0005] An FPGA module, wherein the FPGA module is connected to the DDR4 to be tested, and is used to obtain a test information instruction, send an input test signal to the DDR4 to be tested based on the test information instruction, obtain an output test signal from the DDR4 to be tested, and obtain DDR4 storage data information based on the input test signal and the output test signal;
[0006] A configuration circuit module is connected to the FPGA module to support the normal operation of the FPGA module.
[0007] Optionally, the configuration circuit module includes:
[0008] Pull-up resistors are used to keep the FPGA module pins in a high level state;
[0009] Button, used to manually reset the FPGA module;
[0010] DIP switch, used to select the configuration mode or parameters of the FPGA module;
[0011] Relay, used to switch the configuration path of the FPGA module;
[0012] Magnetic beads, used for power isolation of some pins of FPGA modules;
[0013] Clock, which provides timing signals for the operation of FPGA modules;
[0014] LED lights to display the high and low level status of the FPGA module pins.
[0015] Optionally, a host computer platform is also included, which is connected to the FPGA module to send the test information instruction to the FPGA module and receive and display the DDR4 storage data information from the FPGA module.
[0016] Optionally, it also includes a power supply module for supplying power to the FPGA module, the configuration circuit module and the DDR4 to be tested.
[0017] Optionally, the power supply module is divided into a first power supply module and a second power supply module, the first power supply module supplies power to the FPGA module and the configuration circuit module, and the second power supply module supplies power to the DDR4 to be tested.
[0018] Optionally, the first power supply module includes a first external power supply and a first voltage conversion module, and the first voltage conversion module is connected to the FPGA module and the configuration circuit module.
[0019] Optionally, the second power supply module includes a second external power supply and a second voltage conversion module, and the second voltage conversion module is connected to the DDR4 to be tested.
[0020] Based on the same inventive concept, the present disclosure also provides a DDR4 function test method, which is applied to the function test system mentioned in the claim, and the method comprises the following steps:
[0021] The host computer platform sends the test information instruction to the FPGA module;
[0022] The FPGA module obtains the test information instruction from the host computer platform, sends an input test signal to the DDR4 to be tested based on the test information instruction and obtains an output test signal from the DDR4 to be tested, and obtains DDR4 storage data information based on the input test signal and the output test signal;
[0023] The host computer platform receives and displays the DDR4 storage data information from the FPGA module.
[0024] As can be seen from the above, a DDR4 functional test system provided by the present application includes an FPGA module, which is connected to the DDR4 to be tested to obtain test information instructions, sends an input test signal to the DDR4 to be tested based on the test information instructions and obtains an output test signal from the DDR4 to be tested, and obtains DDR4 storage data information based on the input test signal and the output test signal, and obtains the DDR4 storage data information according to the FPGA module, thereby quickly judging the storage performance of the DDR4 to be tested. In addition, the FPGA module is highly programmable, so the FPGA module can be adjusted according to different models of DDR4 or test scenarios, thereby greatly improving the versatility and adaptability of the test system. The FPGA module also has high-speed processing capabilities and can complete a large number of test tasks for DDR4 in a short time, and the test efficiency is relatively high; the DDR4 functional test system also includes a configuration circuit module, which is connected to the FPGA module to support the normal operation of the FPGA module and avoid FPGA module operation errors. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0026] Figure 1 A block diagram of a test system according to an embodiment of the present application;
[0027] Figure 2 This is a flow chart of the testing method of the embodiment of the present application. DETAILED DESCRIPTION
[0028] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0029] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0030] Based on the background, DDR4 (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory), that is, double data rate fourth generation synchronous dynamic random access memory card, is an indispensable storage medium for contemporary computer systems. Its performance is directly related to the operating efficiency and data processing capabilities of the entire system. Compared with its predecessors, DDR4 memory has achieved significant improvements in data transmission rate, power consumption control, and capacity expansion, providing strong support for application scenarios such as high-performance computing, big data processing, and graphics rendering.
[0031] However, after DDR4 is produced, it is far from enough to rely solely on existing test equipment for basic functional testing. These traditional test equipment mainly focuses on verifying whether each module on DDR4 (such as control logic, data bus, address bus, etc.) can work normally according to the design specifications to ensure that there are no hardware failures or connection problems. However, this test method cannot fully evaluate the storage performance of DDR4.
[0032] In order to solve the above problems, the present application provides a DDR4 functional test system including an FPGA module, which is connected to the DDR4 to be tested to obtain test information instructions, sends an input test signal to the DDR4 to be tested based on the test information instructions and obtains an output test signal from the DDR4, and obtains DDR4 storage data information based on the input test signal and the output test signal, and obtains the DDR4 storage data information according to the FPGA module to quickly judge the storage performance of the DDR4.
[0033] The following is combined with Figure 1-2 The embodiments of the present application will be described in detail.
[0034] A DDR4 functional test system, such as Figure 1 As shown, including:
[0035] An FPGA module, wherein the FPGA module is connected to the DDR4 to be tested, and is used to obtain a test information instruction, send an input test signal to the DDR4 to be tested based on the test information instruction, obtain an output test signal from the DDR4 to be tested, and obtain DDR4 storage data information based on the input test signal and the output test signal;
[0036] A configuration circuit module is connected to the FPGA module to support the normal operation of the FPGA module.
[0037] Specifically, the FPGA module is the core module of the DDR4 functional test system. The FPGA module can obtain test information instructions from the test software or external controller. The test information instructions include data read and write speed test instructions, data stability test instructions, and data timing test instructions. Based on the obtained test information instructions, the FPGA module generates a series of customized input test signals. These input test signals are transmitted to the DDR4 storage module to trigger its internal read and write operations and other functions. The DDR4 storage module outputs test signals, and the FPGA module obtains the output test signals in real time. By comparing the input test signals and the output test signals, the FPGA module can calculate the storage data information of the DDR4 storage module, thereby obtaining key performance indicators such as actual storage capacity, read and write speeds, and data integrity.
[0038] In this embodiment, the FPGA module is used to obtain test information instructions, send an input test signal to the DDR4 to be tested based on the test information instructions and obtain an output test signal from the DDR4, and obtain DDR4 storage data information based on the input test signal and the output test signal. The DDR4 storage data information is obtained according to the FPGA module, so as to quickly judge the storage performance of the DDR4. The DDR4 functional test system also includes a configuration circuit module, which is connected to the FPGA module to support the normal operation of the FPGA module and avoid FPGA module operation errors.
[0039] In some embodiments, the configuration circuit module includes:
[0040] Pull-up resistors are used to keep the FPGA module pins in a high level state;
[0041] Button, used to manually reset the FPGA module;
[0042] DIP switch, used to select the configuration mode or parameters of the FPGA module;
[0043] Relay, used to switch the configuration path of the FPGA module;
[0044] Magnetic beads, used for power isolation of some pins of FPGA modules;
[0045] Clock, which provides timing signals for the operation of FPGA modules;
[0046] LED lights to display the high and low level status of the FPGA module pins.
[0047] Specifically, the pull-up resistor is connected between the FPGA module pin and the power supply to keep the FPGA module pin in a high-level state, prevent electrical instability caused by the pin being suspended, and ensure that the FPGA module can run stably during the test; the button is used to manually reset the FPGA module. When the FPGA module falls into an abnormal state for some reason, the tester can quickly restore its normal working state by pressing the button, thereby improving the reliability of the FPGA module; the dip switch is used to select the configuration mode or parameters of the FPGA module to adapt to different models of DDR4 storage modules or test scenarios; the relay is used to switch the configuration path of the FPGA module. By controlling the open and closed state of the relay, the tester It can flexibly switch between multiple configuration paths, thereby realizing fast switching and testing of different configuration schemes of the FPGA module; magnetic beads are used to isolate the power supply of some pins of the FPGA module to protect the FPGA module from interference from the external environment, ensuring that the FPGA module can stably and accurately receive and process signals during the test; the clock provides timing signals for the operation of the FPGA module to ensure that the FPGA module can perform test tasks according to the preset timing requirements; the LED light displays the high and low level states of the FPGA module pins. By observing the on and off states of the LED light, the tester can intuitively understand the working status of the FPGA module during the test, which helps to quickly locate and solve potential problems and improve test efficiency.
[0048] In this embodiment, the configuration circuit module provides a stable, flexible and easy-to-monitor working environment for the FPGA module by integrating multiple electronic components. These components work together to ensure that the DDR4 functional test system can perform test tasks efficiently and accurately.
[0049] In some embodiments, Figure 1 As shown, a DDR4 functional test system also includes a host computer platform, which is connected to the FPGA module to send the test information instruction to the FPGA module and receive and display the DDR4 storage data information from the FPGA module.
[0050] Specifically, the host computer platform establishes a connection with the FPGA module through a serial port through a specific communication protocol, and sends test information instructions to it, including but not limited to data read and write speed test instructions, data stability test instructions, data timing test instructions, etc., which are used to comprehensively test the various storage functions of DDR4. The host computer receives and displays the DDR4 storage data information from the FPGA module, parses and processes the storage data information, and then displays it on the user interface in an intuitive manner (such as charts, waveforms, logs, etc.) for testers to analyze and evaluate.
[0051] In this embodiment, by sending test information instructions to the FPGA module and receiving and displaying DDR4 storage data information from the FPGA module, the host computer platform can achieve a comprehensive analysis of the DDR4 storage module and provide strong support for DDR4 storage performance optimization.
[0052] In some embodiments, Figure 1 As shown, a DDR4 functional test system also includes a power supply module for supplying power to the FPGA module, the configuration circuit module and the DDR4 to be tested;
[0053] In addition, the power supply module is divided into a first power supply module and a second power supply module, the first power supply module supplies power to the FPGA module and the configuration circuit module, and the second power supply module supplies power to the DDR4 to be tested.
[0054] Specifically, the first power supply module and the second power supply module are connected to a filtering circuit to prevent power supply fluctuations and noise of the first power supply module and the second power supply module from affecting the test system. The first power supply module and the second power supply module are also connected to a protection tube. When an abnormal situation such as overvoltage occurs in the first power supply module and the second power supply module, the protection tube cuts off the power output to prevent the FPGA module, the configuration circuit module and the DDR4 to be tested from being damaged.
[0055] In this embodiment, the FPGA module and the DDR4 to be tested are powered separately so that the power supplies of the FPGA module and the DDR4 to be tested can be independently controlled, thereby facilitating the adjustment of the power supply parameters of the two modules separately as needed to meet different test requirements. The separate power supplies of the FPGA module and the DDR4 to be tested avoid interference between the power supplies and improve the overall reliability of the test system.
[0056] In some embodiments, the first power supply module includes a first external power supply and a first voltage conversion module, and the first voltage conversion module is connected to the FPGA module and the configuration circuit module.
[0057] In addition, the second power supply module includes a second external power supply and a second voltage conversion module, and the second voltage conversion module is connected to the DDR4 to be tested.
[0058] Specifically, five circuits are provided between the first voltage conversion module and the FPGA module, and these five circuits provide power for the FPGA module and the configuration circuit module. Exemplarily, the voltage of the first power supply module is 12V, and the voltages of these five circuits are 0.85V, 1.8V, 3.3V, 1.2V and 5V, respectively, to ensure the normal operation of the FPGA module and the configuration circuit module.
[0059] In addition, three circuits are provided between the second voltage conversion module and the DDR4 to be tested to supply power to the DDR4 to be tested. For example, the voltage of the second power supply module is 12V, and the voltages of these three circuits are 1.2V, 1.2V and 2.5V respectively. These three circuits can also be powered by independent power supplies 1, 2 and 3 respectively to meet the normal operation of the DDR4 to be tested.
[0060] In this embodiment, the design of the first power supply module and the second power supply module fully considers the specific power requirements of the FPGA module, the configuration circuit module and the DDR4 to be tested, and ensures the stable operation of each module through precise voltage conversion and distribution.
[0061] Based on the same inventive concept, corresponding to any of the above embodiments, the present application also provides a DDR4 functional test method, which is applied to the above functional test system, such as Figure 2 As shown, the method comprises the following steps:
[0062] S101, the host computer platform sends the test information instruction to the FPGA module;
[0063] S102, the FPGA module obtains the test information instruction from the host computer platform, sends an input test signal to the DDR4 to be tested based on the test information instruction and obtains an output test signal from the DDR4 to be tested, and obtains DDR4 storage data information based on the input test signal and the output test signal;
[0064] S103, the host computer platform receives and displays the DDR4 storage data information from the FPGA module.
[0065] Specifically, the first power supply module supplies power to the FPGA module and the configuration circuit module through the first external power supply and the first voltage conversion module, and the second power supply module supplies power to the DDR4 to be tested through the second external power supply and the second voltage conversion module. After the FPGA module, the configuration circuit module and the DDR4 to be tested are powered on, the user inputs test information instructions and operation instructions on the host computer platform, and the host computer platform sends the test information instructions to the FPGA module. These test information instructions include but are not limited to data read and write speed test instructions, data stability test instructions, and data timing test instructions. The FPGA module generates a series of customized input test signals based on the obtained test information instructions. These input test signals are transmitted to the DDR4 storage module to trigger its internal read and write operations and other functions. The DDR4 storage module outputs a test signal, and the FPGA module obtains the output test signal in real time. By comparing the input test signal and the output test signal, the FPGA module can calculate the storage data information of the DDR4 storage module. The host computer receives and displays the DDR4 storage data information from the FPGA module, parses and processes the storage data information, and then displays it on the user interface in an intuitive manner (such as a chart, a waveform chart, a log, etc.) for analysis and evaluation by testers.
[0066] In this embodiment, the DDR4 functional testing method is easy to operate and has high testing efficiency, and is convenient for large-scale testing of DDR4.
[0067] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.
[0068] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0069] It is understandable that before using the technical solutions of each embodiment of the present disclosure, the type, scope of use, usage scenarios, etc. of the personal information involved will be informed to the user in an appropriate manner, and the user's authorization will be obtained.
[0070] For example, in response to receiving an active request from a user, a prompt message is sent to the user to clearly remind the user that the operation requested to be performed will require obtaining and using the user's personal information. Thus, the user can independently choose whether to provide personal information to software or hardware such as an electronic device, application, server, or storage medium that performs the operation of the technical solution of the present disclosure according to the prompt message.
[0071] As an optional but non-limiting implementation, in response to receiving the user's active request, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. In addition, the pop-up window may also carry a selection control for the user to choose "agree" or "disagree" to provide personal information to the electronic device.
[0072] It is understandable that the above notification and the process of obtaining user authorization are merely illustrative and do not constitute a limitation on the implementation of the present disclosure. Other methods that meet relevant laws and regulations may also be applied to the implementation of the present disclosure.
[0073] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.
[0074] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.
[0075] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
[0076] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the present application.
Claims
1. A DDR4 functional test system, characterized in that: include: An FPGA module, wherein the FPGA module is connected to the DDR4 to be tested, and is used to obtain a test information instruction, send an input test signal to the DDR4 to be tested based on the test information instruction, obtain an output test signal from the DDR4 to be tested, and obtain DDR4 storage data information based on the input test signal and the output test signal; A configuration circuit module is connected to the FPGA module to support the normal operation of the FPGA module.
2. A DDR4 functional test system according to claim 1, characterized in that: The configuration circuit module comprises: Pull-up resistors are used to keep the FPGA module pins in a high level state; Button, used to manually reset the FPGA module; DIP switch, used to select the configuration mode or parameters of the FPGA module; Relay, used to switch the configuration path of the FPGA module; Magnetic beads, used for power isolation of some pins of FPGA modules; Clock, which provides timing signals for the operation of FPGA modules; LED lights to display the high and low level status of the FPGA module pins.
3. A DDR4 functional test system according to claim 1, characterized in that: It also includes a host computer platform, which is connected to the FPGA module and is used to send the test information instruction to the FPGA module, and receive and display the DDR4 storage data information from the FPGA module.
4. A DDR4 functional test system according to claim 3, characterized in that: It also includes a power supply module for supplying power to the FPGA module, the configuration circuit module and the DDR4 to be tested.
5. A DDR4 functional test system according to claim 4, characterized in that: The power supply module is divided into a first power supply module and a second power supply module, the first power supply module supplies power to the FPGA module and the configuration circuit module, and the second power supply module supplies power to the DDR4 to be tested.
6. A DDR4 functional test system according to claim 5, characterized in that: The first power supply module includes a first external power supply and a first voltage conversion module, and the first voltage conversion module is connected to the FPGA module and the configuration circuit module.
7. A DDR4 functional test system according to claim 6, characterized in that: The second power supply module includes a second external power supply and a second voltage conversion module, and the second voltage conversion module is connected to the DDR4 to be tested.
8. A DDR4 function test method, applied to the function test system according to any one of claims 3 to 7, characterized in that: The method comprises the following steps: The host computer platform sends the test information instruction to the FPGA module; The FPGA module obtains the test information instruction from the host computer platform, sends an input test signal to the DDR4 to be tested based on the test information instruction and obtains an output test signal from the DDR4 to be tested, and obtains DDR4 storage data information based on the input test signal and the output test signal; The host computer platform receives and displays the DDR4 storage data information from the FPGA module.