Low-voltage large-current protection switch

Abstract

The invention relates to the technical field of low-voltage large-current circuit protection, in particular to a low-voltage large-current protection switch. Comprising a current sampling circuit, an autonomous power-up circuit and a switch control circuit. The current sampling circuit comprises a triode geminate transistor and a triode Q3; the autonomous power-up circuit comprises a triode Q4, an emitting electrode of the triode Q4 is connected with a power supply, a base electrode of the triode Q4 is connected with a collector electrode of the triode Q3, and the collector electrode of the triode Q4 is grounded; the switch control circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube Q7 and a triode Q5, the PMOS tube Q7 is arranged on the power distribution bus, and a collector electrode of the triode Q5 is connected with the power distribution bus and a grid electrode of the PMOS tube Q7; the base electrode of the triode Q5 is connected with the collector electrode of the triode Q4, and the emitter electrode of the triode Q5 is grounded. According to the invention, a low turn-on voltage MOSFET is used as a main switch element, and when the current on a power distribution bus increases instantly, a fault circuit power supply can be cut off in an instantaneous response; in addition, the system can be automatically powered up and restarted.

Description

Technical Field

[0001] The invention relates to the technical field of low-voltage and high-current circuit protection, and in particular to a low-voltage and high-current protection switch. Background Art

[0002] At present, large-scale integrated circuits are increasingly used in satellite communications, space exploration, remote sensing and mapping, and other fields. With the rapid development of modern science and technology, these applications have put forward higher requirements on the performance of integrated circuits, so the scale of large-scale integrated circuits has continued to expand and the process has become more and more advanced. However, as the scale of integrated circuits continues to expand, in order to reduce power consumption and increase integration, its core voltage has gradually decreased to DC 0.8V or even lower, but at the same time, the operating current has become larger and larger, and some integrated circuits can reach 20A or even higher under transient conditions.

[0003] In the space environment, especially under the extreme conditions of satellite products, integrated circuits face severe challenges from single event effects (SEE) from cosmic rays. Single event events can cause a sudden change in the charge state inside the integrated circuit, which in turn triggers the single event lockup (SEL) phenomenon. In the single event lockup state, the current of the integrated circuit will far exceed its rated value, causing permanent damage to the circuit components and even threatening the safe and stable operation of the entire satellite system.

[0004] Due to the lack of effective protection switches for low-voltage and high-current conditions on the current market, the power input design of most satellite large-scale integrated circuits does not integrate switch control functions and does not have the ability to automatically protect after a fault. This means that when single-particle lock occurs, the system cannot handle it automatically and can only eliminate the single-particle lock phenomenon by powering off and then powering on the entire machine after a single-machine current telemetry abnormality.

[0005] This traditional operation mode has obvious inherent defects. First, the protection is not timely enough, the response time of the whole system is long, and the system cannot quickly isolate the faulty part. Second, the fault handling method is to power off the single machine, which has a great impact. Third, it does not have the ability to power on autonomously after the fault is handled. Summary of the invention

[0006] The present invention provides a low-voltage, high-current protection switch, which aims to solve the problems of slow fault response, large impact of fault handling method and lack of autonomous power-on capability in the prior art by adopting a low turn-on voltage MOSFET as a main switch element, setting a current sampling circuit to sample the path current, driving the MOSFET to switch, and setting an autonomous power-on circuit to realize power-on restart after the load is powered off.

[0007] To achieve the above object, the technical solution of the present invention is: The present invention provides a low-voltage high-current protection switch, including a current sampling circuit, an autonomous power-on circuit and a switch control circuit; The current sampling circuit can sample the current flowing through the distribution bus, and includes a transistor pair and a transistor Q3, wherein the transistor pair includes a transistor Q1 and a transistor Q2; The autonomous power-on circuit comprises a transistor Q4, the emitter of the transistor Q4 is connected to a power source, the base of the transistor Q4 is connected to the collector of the transistor Q3, and the collector of the transistor Q4 is grounded; The switch control circuit includes a PMOS tube Q7 and a transistor Q5. The PMOS tube Q7 is arranged on a distribution bus. The collector of the transistor Q5 is connected to the distribution bus through a series resistor R9*. The collector of the transistor Q5 is also connected to the gate of the PMOS tube Q7 through a series resistor R10*. The base of the transistor Q5 is connected to the collector of the transistor Q4, and the emitter of the transistor Q5 is grounded.

[0008] Further, the base of the transistor Q2 is respectively connected to the collector of the transistor Q1, the base of the transistor Q1 and one end of the resistor R4, and the other end of the resistor R4 is grounded; the collector of the transistor Q2 is respectively connected to one end of the resistor R5 and the base of the transistor Q3, and the other end of the resistor R5 is grounded; the emitter of the transistor Q3 is connected to the end of the resistor R2 away from the power supply, and the collector of the transistor Q3 is connected in series with a resistor R6* and a resistor R7* in sequence, and the end of the resistor R7* away from the transistor Q3 is grounded.

[0009] Furthermore, the transistor Q1, the transistor Q2 and the transistor Q3 are all PNP transistors.

[0010] Furthermore, the transistor Q4 is a PNP transistor.

[0011] Furthermore, the emitter of the transistor Q4 is also connected to one end of the capacitor C8 and one end of the capacitor C9 respectively, the other end of the capacitor C8 and the other end of the capacitor C9 are both grounded, and the capacitor C8 and the capacitor C9 are connected in parallel.

[0012] Furthermore, the base of the transistor Q4 is also connected to one end of a capacitor C6*, and the other end of the capacitor C6* is grounded.

[0013] Furthermore, the collector of the transistor Q4 is grounded via a series resistor R8*.

[0014] Furthermore, the PMOS tube Q7 is a PMOS tube with a conduction voltage of 0.7V, and the transistor Q5 is an NPN transistor.

[0015] Furthermore, the gate of the PMOS tube Q7 is also connected to one end of a capacitor C11*, and the other end of the capacitor C11* is connected to a power distribution bus.

[0016] Furthermore, the base of the transistor Q5 is connected to one end of the capacitor C7, and the other end of the capacitor C7 is grounded.

[0017] The beneficial effects achieved by the present invention are: The present invention adopts a low turn-on voltage MOSFET as the main switch element. The turn-on voltage is low and no external drive power supply is required. The opening and closing of the distribution bus can be controlled by the switch control circuit. When the current on the distribution bus increases instantaneously, the power supply of the fault circuit can be cut off instantaneously to isolate the fault circuit, effectively protect the circuit and prevent further deterioration.

[0018] The present invention adopts a current sampling circuit to sample the path current. When the load current increases abnormally, the current sampling circuit outputs a control signal to drive the MOSFET to shut down, cut off the distribution bus, and stop outputting to the load, with a rapid response. Moreover, the current sampling circuit adopts a packaged transistor pair, which can save space and simplify the design on the one hand, and can also ensure the forward current transfer ratio h of the common emitter of the two internal transistors on the other hand. FE It is relatively consistent and can ensure the accuracy of the current sampling circuit.

[0019] The present invention adopts an autonomous power-on circuit to realize power-on restart of the load after the load is shut down due to overcurrent, thereby ensuring that the integrated circuit can be restarted after being affected by single particle lock, thereby eliminating the influence of single particle lock. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0021] Figure 1 The input voltage and output voltage of the power distribution bus of the present invention, the V of the PMOS tube Q7, and the output voltage of the power distribution bus of the present invention are as follows: gs And the output voltage waveform of the current sampling circuit.

[0022] Figure 2 The input voltage and output voltage of the power distribution bus of the present invention, the V of the PMOS tube Q7, and the V gs And the output voltage waveform of the current sampling circuit.

[0023] Figure 3 When the power distribution bus exceeds 20A and enters the hiccup protection mode, the power distribution bus input voltage and output voltage, and the V gs And the output voltage waveform of the current sampling circuit.

[0024] Figure 4 When the present invention exits the hiccup protection mode and returns to normal, the input voltage and output voltage of the power distribution bus, and the V gs And the output voltage waveform of the current sampling circuit.

[0025] Figure 5 It is a circuit schematic diagram of the present invention.

[0026] Figure 6 It is the output voltage and current experimental waveform diagram of the present invention during overcurrent protection. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0029] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if the meaning of "and / or" appearing in the full text is to include three parallel schemes, taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0030] like Figure 5As shown, the present invention provides a low-voltage high-current protection switch, including a current sampling circuit, an autonomous power-on circuit and a switch control circuit; The current sampling circuit is based on the improvement of the current mirror and can measure the current I flowing through the distribution bus. typ Sampling is performed to mirror the current of the distribution bus and control the autonomous power-on circuit, thereby controlling the on and off of the switch control circuit; when I typ When the fault is large, the distribution bus is instantly controlled to shut down and the faulty circuit is isolated. In addition, the present invention can continuously try to power on and restart, and the path enters the hiccup protection mode until the single-particle locking fault is eliminated and normal output is restored without manual intervention.

[0031] One end of the distribution bus is connected to a power supply with a power supply voltage of VCC, and the other end is connected to a load circuit; the end of the distribution bus close to the power supply is grounded through capacitors C4, C3 and C2 in sequence, and capacitors C2, C3 and C4 are connected in parallel. The functions of capacitors C2, C3 and C4 are to filter, decouple and stabilize the supply voltage.

[0032] The current sampling circuit includes a power sampling resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6*, a resistor R7*, a capacitor C1, a capacitor C5, a transistor pair and a transistor Q3. The transistor pair includes a transistor Q1 and a transistor Q2. The transistor pair is essentially two transistors that have been screened. FE The power sampling resistor R1 is connected in series with the power distribution bus and arranged after the capacitor C2, so as to facilitate the current sampling circuit to collect the current of the power distribution bus; the capacitor C1 is connected in parallel with the power sampling resistor R1 to stabilize the voltage across the power sampling resistor R1 to prevent fluctuation due to interference; one end of the resistor R2 is connected to the end of the power sampling resistor R1 close to the power supply, and the other end is respectively connected to one end of the capacitor C5, the emitter of the transistor Q1 and the emitter of the transistor Q3; one end of the resistor R3 is connected to the end of the power sampling resistor R1 far away from the power supply, and the other end is respectively connected to the other end of the capacitor C5 and the emitter of the transistor Q2.

[0033] The purpose of the transistor pair is to ensure that the forward current transfer ratio of the common emitter of the two internal transistors is h FEThe transistor Q2 is relatively consistent, and the accuracy of the current sampling circuit can be guaranteed; the base of the transistor Q2 is respectively connected to the collector of the transistor Q1, the base of the transistor Q1 and one end of the resistor R4, and the other end of the resistor R4 is grounded; the collector of the transistor Q2 is respectively connected to one end of the resistor R5 and the base of the transistor Q3, and the other end of the resistor R5 is grounded; the emitter of the transistor Q3 is connected to the end of the resistor R2 away from the power supply, and the collector of the transistor Q3 is connected in series with resistors R6* and R7* in sequence, and the end of the resistor R7* away from the transistor Q3 is grounded. The resistors R6* and R7* are connected in series, one is to limit the current between the emitter and the collector of the transistor Q3 to prevent the transistor Q3 from being damaged, and the other is to enable the autonomous power-on circuit to obtain the output voltage U of the current sampling circuit s , U s It is related to the sum of the resistance values ​​of resistors R6* and R7*; the collector of the transistor Q3 is the output end of the current sampling circuit, and the output voltage is U s , the calculation formula for converting current into voltage signal is:

[0034] Furthermore, the transistor Q1, the transistor Q2 and the transistor Q3 are all PNP transistors, and the on-state voltages are all about 0.7V.

[0035] The autonomous power-on circuit includes a transistor Q4, the emitter of which is connected to a power supply, the base of which is connected to the collector of the transistor Q3, and the collector of which is grounded; the transistor Q4 is controlled by the output voltage of the current sampling circuit, and the collector of the transistor Q4 is the output end of the autonomous power-on circuit.

[0036] Furthermore, the transistor Q4 is a PNP transistor, and its on-state voltage is about 0.7V.

[0037] Furthermore, the emitter of the transistor Q4 is also connected to one end of the capacitor C8 and one end of the capacitor C9 respectively, the other end of the capacitor C8 and the other end of the capacitor C9 are both grounded, and the capacitor C8 and the capacitor C9 are connected in parallel.

[0038] Furthermore, the base of the transistor Q4 is also connected to one end of the capacitor C6*, the other end of the capacitor C6* is grounded, and the capacitor C6* is connected in parallel with the resistor R6* and the resistor R7*; the capacitor C6* can limit the bandwidth to prevent the voltage at the base of the transistor Q4 from being affected by high-frequency electromagnetic interference, and amplify the interference signal and transmit it to the subsequent circuit.

[0039] Furthermore, the collector of the transistor Q4 is grounded via a series resistor R8*, and the resistor R8* is used for current limiting protection to prevent excessive current between the emitter and collector of the transistor Q4 from damaging the transistor Q4.

[0040] The switch control circuit includes a PMOS tube Q7 and a transistor Q5. The PMOS tube Q7 is arranged on the power distribution bus. The source of the PMOS tube Q7 is connected to the end of the power sampling resistor R1 away from the power supply, and the drain of the PMOS tube Q7 is connected to the load circuit; the collector of the transistor Q5 is connected to the power distribution bus through a series resistor R9*, and the collector of the transistor Q5 is also connected to the gate of the PMOS tube Q7 through a series resistor R10*; the resistor R9* is used to protect the transistor Q5 to prevent the transistor Q5 from being damaged due to excessive current, and the resistor R10* is used to protect the PMOS tube Q7 to prevent the PMOS tube Q7 from being damaged due to excessive current; the base of the transistor Q5 is connected to the collector of the transistor Q4, and the emitter of the transistor Q5 is grounded.

[0041] Furthermore, the PMOS tube Q7 is a PMOS tube with a conduction voltage of about 0.7V, and the transistor Q5 is an NPN transistor with a conduction voltage of about 0.7V.

[0042] Furthermore, the gate of the PMOS tube Q7 is also connected to one end of a capacitor C11*, and the other end of the capacitor C11* is connected to a power distribution bus. The function of the capacitor C11* is to filter and stabilize the voltage.

[0043] Furthermore, the base of the transistor Q5 is connected to one end of the capacitor C7, the other end of the capacitor C7 is grounded, and the capacitor C7 is connected in parallel with the resistor R8*; the capacitor C7 can limit the bandwidth to prevent the base of the transistor Q5 from being affected by high-frequency electromagnetic interference, and amplify the interference signal and transmit it to the subsequent circuit.

[0044] When the power is initially turned on, the distribution bus current I typ Less than the overcurrent protection current value I max , assuming the bus voltage is 0.8V, the power distribution output can be achieved, such as Figure 1 shown.

[0045] The “*” in the resistor R6* or capacitor C6* means that the size of the resistor or capacitor needs to be adjusted according to the actual application conditions to select a suitable resistor or capacitor, and the others are the same.

[0046] Under normal working conditions, the power supply voltage is VCC, and the circuit detects the current flowing through the power sampling resistor R1 through the current sampling circuit. The current I typ Less than the overcurrent protection current value I maxWhen the output voltage U of the current sampling circuit s Less than (VCC-0.7)V, that is, the base voltage V of the PNP transistor Q4 BE (the voltage of the base (B) relative to the emitter (E)) is greater than 0.7V, the transistor Q4 is turned on; when the transistor Q4 is turned on, the V BE When the transistor Q5 is turned on, the gate voltage of the PMOS tube Q7 will be pulled down, and the gate voltage V GS Will be less than the PMOS tube conduction voltage V th , the PMOS tube Q7 is turned on, and the switch circuit realizes the power distribution output, such as Figure 2 shown.

[0047] When a single-event lock occurs in an integrated circuit, the distribution bus current I typ Increase, current I typ Greater than the overcurrent protection current value I max At this time, a low-voltage, high-current protection switch is required for overcurrent protection. At this time, the output voltage U s Greater than (VCC-0.7)V, that is, V of PNP transistor Q4 BE When the transistor Q4 is turned off, the V BE When the transistor Q5 is turned off, the gate voltage of the PMOS tube Q7 is equal to the power supply voltage, and the gate voltage V GS Will be greater than the PMOS tube conduction voltage V th , the PMOS tube Q7 is turned off, the switch circuit stops distributing power output, the locked integrated circuit is powered off, and the faulty load circuit is quickly isolated.

[0048] After the switch circuit stops outputting, the distribution bus current I typ drops to 0, the current sampling circuit outputs a voltage U s Restore to below (VCC-0.7)V, that is, the base voltage V BE When the transistor Q4 is turned on, the V BE When the transistor Q5 is turned on, the gate voltage of the PMOS tube Q7 will be pulled down, and the gate voltage V GS Will be less than the PMOS tube conduction voltage V th, the PMOS tube Q7 resumes conduction, and the switch circuit distributes power output; when the single-particle lockout fault is not eliminated, the above overcurrent protection automatic power-off and self-opening process will be repeated, and the path will enter the hiccup protection mode until the single-particle lockout fault is eliminated and normal output is restored, such as Figure 3 , Figure 4 shown.

[0049] Figure 6 This is the actual measured waveform of the experiment using the circuit of the present invention. The measured value of CH2 is the output voltage, and the measured value of CH4 is the current I typ When the switch performs overcurrent protection, the experimental waveform is basically consistent with the simulation result.

[0050] The above descriptions are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A low voltage and high current protection switch, characterized in that: It includes a current sampling circuit, an autonomous power-on circuit and a switch control circuit; The current sampling circuit can sample the current flowing through the distribution bus, and includes a transistor pair and a transistor Q3, wherein the transistor pair includes a transistor Q1 and a transistor Q2; The autonomous power-on circuit comprises a transistor Q4, the emitter of the transistor Q4 is connected to a power source, the base of the transistor Q4 is connected to the collector of the transistor Q3, and the collector of the transistor Q4 is grounded; The switch control circuit includes a PMOS tube Q7 and a transistor Q5. The PMOS tube Q7 is arranged on a distribution bus. The collector of the transistor Q5 is connected to the distribution bus through a series resistor R9*. The collector of the transistor Q5 is also connected to the gate of the PMOS tube Q7 through a series resistor R10*. The base of the transistor Q5 is connected to the collector of the transistor Q4, and the emitter of the transistor Q5 is grounded.

2. A low voltage and high current protection switch according to claim 1, characterized in that: The base of the transistor Q2 is respectively connected to the collector of the transistor Q1, the base of the transistor Q1 and one end of the resistor R4, and the other end of the resistor R4 is grounded; the collector of the transistor Q2 is respectively connected to one end of the resistor R5 and the base of the transistor Q3, and the other end of the resistor R5 is grounded; the emitter of the transistor Q3 is connected to the end of the resistor R2 away from the power supply, and the collector of the transistor Q3 is connected in series with a resistor R6* and a resistor R7* in sequence, and the end of the resistor R7* away from the transistor Q3 is grounded.

3. A low voltage and high current protection switch according to claim 2, characterized in that: The transistor Q1 , the transistor Q2 and the transistor Q3 are all PNP transistors.

4. A low voltage and high current protection switch according to claim 1, characterized in that: The transistor Q4 is a PNP transistor.

5. A low voltage and high current protection switch according to claim 1, characterized in that: The emitter of the transistor Q4 is also connected to one end of the capacitor C8 and one end of the capacitor C9 respectively, the other end of the capacitor C8 and the other end of the capacitor C9 are both grounded, and the capacitor C8 and the capacitor C9 are connected in parallel.

6. A low voltage and high current protection switch according to claim 1, characterized in that: The base of the transistor Q4 is also connected to one end of a capacitor C6*, and the other end of the capacitor C6* is grounded.

7. A low voltage and high current protection switch according to claim 1, characterized in that: The collector of the transistor Q4 is grounded via a series resistor R8*.

8. A low voltage and high current protection switch according to claim 1, characterized in that: The PMOS tube Q7 is a PMOS tube with a conduction voltage of 0.7V, and the transistor Q5 is an NPN transistor.

9. A low voltage and high current protection switch according to claim 1, characterized in that: The gate of the PMOS tube Q7 is also connected to one end of a capacitor C11*, and the other end of the capacitor C11* is connected to a power distribution bus.

10. A low voltage and high current protection switch according to claim 1, characterized in that: The base of the transistor Q5 is connected to one end of the capacitor C7, and the other end of the capacitor C7 is grounded.

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