Digital delay chain control circuit and method
By calibrating in the digital delay chain control circuit, the calibration parameters of the reference delay chain are mapped to the working delay chain and their accuracy parameters are obtained, the problem of instability of delay control value is solved, and the requirements for hardware circuits are reduced and delay accuracy are guaranteed.
Patent Information
- Application Number
- CN202311142541.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-05
- Publication Date
- 2025-03-07
AI Technical Summary
The existing digital delay chain control method is not stable enough when facing temperature and voltage changes, which may lead to data transmission errors and require too strict hardware circuits.
By performing calibration before the working delay chain starts working, the first calibration parameter is obtained using the reference delay chain measurement, and map it into the second calibration parameter of the working delay chain, and at the same time, the accuracy parameters of the working delay chain are obtained and its delay parameters are determined to achieve precise control.
The requirements for hardware circuits are reduced, the accuracy of the working delay chain is ensured, and the convenience and flexibility of adjustment operations are improved by adjusting the step size parameters, and the delay control value sudden changes caused by abnormal sampling results are prevented.
Smart Images
Figure CN119582812A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuit technology, and in particular to a digital delay chain control circuit and method. Background Art
[0002] Digital delay chains play an important role in high-speed and high-precision analog-to-digital converters, high-precision phase-locked loops, and chips with high clock delay requirements. For example, they can adjust the mismatch between multiple clocks. When multiple clocks have clock offset errors due to different paths or unreasonable wiring, the performance of the circuit controlled by the clock will be greatly reduced, and even in some applications that do not allow clock overlap, the circuit will malfunction due to clock offset errors. Therefore, it is necessary to accurately and controllably adjust the clock.
[0003] The structure of the digital delay chain is as follows Figure 1 As shown, there are mainly two parts, including a fine adjustment circuit 11 and a coarse adjustment circuit 12. The coarse adjustment circuit 12 is implemented by connecting logic gates in series, and each series connection increases the delay by about 10ps; the fine adjustment circuit 11 is implemented by multiple transmission gates driving the same circuit node, and the unit accuracy is about 4ps. The digital delay chain adjusts the delay by changing the delay control value 10, adjusting the number of logic gates or open transmission gates selected by the data selection module 14 through the decoding circuit 13.
[0004] When the time accuracy requirement reaches the ps level, such as DDR (double data rate synchronous dynamic random-access memory, double rate SDRAM) and TDC (Time-to-Digital Converters, time digital conversion) technology, the influence of temperature and voltage changes on the propagation speed of the signal in the circuit cannot be ignored. In this regard, an existing simple solution is to set a reference delay chain, calculate the average unit accuracy of the reference delay chain by continuously measuring the known clock frequency signal, and then use the obtained average unit accuracy to convert and determine the delay control value that needs to be set for the working delay chain.
[0005] During initialization, the control unit will continuously send a test delay control value to the reference delay chain, and each test delay control value sent is different, until a test delay control value sent once causes the lock signal of the reference delay chain to jump. At this time, it means that the test delay control value is the most suitable test delay control value for the reference delay chain in the current state, and the delay reference clock frequency of the reference delay chain and the working clock frequency of the working delay chain are in an integer ratio relationship, such as: 1:1, 2:1, 4:1, etc. Correspondingly, the calculation process of the delay control value is briefly described as follows: let the initial delay control value of the reference delay chain be Rset, the initial latest control value of the reference delay chain be Rnew, the initial delay control value of the working delay chain be Wset, and the latest delay control value of the working delay chain be Wnew; according to the proportional relationship, it can be concluded that Rnew / Rset=Wnew / Wset, and then it can be deduced that Wnew=Rnew*Wset / Rset. In order to prevent sampling errors, the binary method is used to gradually approach the target delay control value, that is, the target value of the working delay chain updated each time is Wtar=Wset+(Wnew-Wset) / 2. This approach is simple and efficient, does not require adding too much complex control logic, and saves chip area. However, this method has the following disadvantages: First, the delay of the change of adjacent delay control values of the digital delay chain is not evenly distributed. If the operating frequency of the reference delay chain is set to 1:1, 2:1, 4:1 of the working clock frequency of the working delay chain, the requirements for the hardware circuit to generate all clock signals with completely matched frequencies are too strict. Secondly, the binary method is not stable enough. If a large transient deviation occurs in a certain sampling, it will cause a large error in the delay control value of a certain time period, which may cause data transmission errors. Summary of the invention
[0006] The embodiment of the present invention provides a digital delay chain control circuit and method to reduce the requirements on the hardware circuit and ensure the accuracy of the working delay chain.
[0007] On the one hand, an embodiment of the present invention provides a digital delay chain control circuit, the circuit comprising: a control module, a clock generation module, a reference module, and a working module respectively connected to the control module; the reference module comprises a reference delay chain; the working module comprises a working delay chain;
[0008] The clock generation module is used to provide multiple clock signals with fixed frequencies that do not change with temperature and voltage;
[0009] The control module is used to calibrate the working delay chain before it starts working, and in the calibration stage, according to the multiple clock signals provided by the clock generation module, obtain the first calibration parameter based on the reference delay chain through the reference module, and obtain the precision parameter of the working delay chain through the working module, and determine the second calibration parameter based on the working delay chain according to the first calibration parameter and the precision parameter of the working delay chain; and is also used to use the second calibration parameter as the delay parameter of the working delay chain after the working delay chain starts working;
[0010] The working module is used to input a working signal, delay the working signal according to the delay parameter, and output a delayed working signal during the working delay chain working phase.
[0011] Optionally, the control module selects two first clock signals and a second clock signal that are closest to the target operating frequency from the multiple reference clock signals in turn as reference signals during the calibration phase, uses the reference module to obtain a first reference delay value corresponding to the first clock signal and a second reference delay value corresponding to the second clock signal, and determines the first calibration parameter according to the first reference delay value and the second reference delay value.
[0012] Optionally, the reference module further comprises: a first multiplexer, a first phase controller, an inherent delay channel, and a first phase detector;
[0013] The first multiplexer is used to input a plurality of clock signals of fixed frequencies and output one of the clock signals;
[0014] The first phase controller is used to perform frequency division and phase shift on the clock signal output by the first multiplexer, and output a first phase-shifted signal and a second phase-shifted signal;
[0015] The inherent delay channel is used to perform a fixed delay on the first phase-shifted signal and output a first delayed signal;
[0016] The reference delay chain is used to perform an adjustable delay on the second phase-shifted signal and output a second delayed signal;
[0017] The first phase detector is used to output a first detection signal according to the first delayed signal and the second delayed signal;
[0018] The control module adjusts the delay value of the reference delay chain to obtain a first reference delay value when the first detection signal corresponding to the first clock signal jumps, and a second reference delay value when the first detection signal corresponding to the second clock signal jumps.
[0019] Optionally, the first phase detector is a D flip-flop, the clock input terminal of the D flip-flop inputs the second delay signal, the data input terminal of the D flip-flop inputs the first delay signal, and the Q output terminal of the D flip-flop outputs the first detection signal.
[0020] Optionally, the control module adjusts the delay value of the reference delay chain to obtain a first reference delay value when the first detection signal corresponding to the first clock signal jumps, and a second reference delay value when the first detection signal corresponding to the second clock signal jumps.
[0021] Optionally, the control module selects a clock signal closest to the target operating frequency from the multiple reference clock signals as a calibration signal during the calibration phase, and obtains the accuracy parameter of the working delay chain by adjusting the delay value of the working module.
[0022] Optionally, the working module further includes: a second multiplexer, a second phase controller, a signal switching module, and a second phase detector;
[0023] The second multiplexer is used to input a plurality of clock signals of fixed frequencies and output one of the clock signals;
[0024] The second phase controller is used to perform frequency division and phase shifting on the clock signal output by the second multiplexer, and output a third phase-shifted signal and a fourth phase-shifted signal;
[0025] The signal switching module is used to transmit the third phase-shifted signal to the working delay chain during the calibration phase; and transmit the working signal to the working delay chain during the working phase;
[0026] The working delay chain is used to delay the signal output by the signal switching module and output a third delay signal or a working delay signal;
[0027] The second phase detector is used to output a second detection signal according to the third delayed signal and the fourth phase-shifted signal;
[0028] The control module adjusts the delay value of the working delay chain to obtain the working delay value when the second detection signal corresponding to the calibration signal generates a jump, and uses the working delay value as the accuracy parameter of the working delay chain.
[0029] Optionally, the second phase detector is a D flip-flop, the clock input terminal of the D flip-flop inputs the fourth phase-shifted signal, the data input terminal of the D flip-flop inputs the third delayed signal, and the Q output terminal of the D flip-flop outputs the second detection signal.
[0030] Optionally, the circuit also includes: a calculation module, used to obtain the first reference delay value and the second reference delay value from the control module, calculate the first calibration parameter based on the first reference delay value and the second reference delay value, and return the first calibration parameter to the control module.
[0031] Optionally, the control module is also used to determine the delay parameters of the reference delay chain using the first clock signal and the second clock signal during the calibration phase; during the working delay chain working phase, detect and update the delay parameters of the reference delay chain in real time, and update the delay parameters of the working delay chain according to the updated delay parameters of the reference delay chain.
[0032] On the other hand, an embodiment of the present invention further provides a digital delay chain control method, the method comprising:
[0033] Before the working delay chain starts working, it is calibrated. The calibration process includes:
[0034] Acquiring a first calibration parameter based on a reference delay chain;
[0035] Mapping the first calibration parameter to a second calibration parameter based on a working delay chain;
[0036] Obtaining the accuracy parameters of the working delay chain;
[0037] Determining a delay parameter of the working delay chain according to the second calibration parameter and the accuracy parameter;
[0038] After the working delay chain starts to work, the working signal input by the working delay chain is delayed according to the delay parameter to output a delayed working signal.
[0039] Optionally, acquiring a first calibration parameter based on a reference delay chain includes:
[0040] Selecting in sequence a first clock signal and a second clock signal which are closest to the target operating frequency as reference signals;
[0041] Acquire a first reference delay value corresponding to the first clock signal and a second reference delay value corresponding to the second clock signal by using a reference delay chain;
[0042] The first calibration parameter is determined according to the first reference delay value and the second reference delay value.
[0043] Optionally, the obtaining the accuracy parameter of the working delay chain includes:
[0044] Select a clock signal that is closest to the target operating frequency as the calibration signal;
[0045] By adjusting the delay value of the working delay chain, the accuracy parameter of the working delay chain is obtained.
[0046] Optionally, the method further comprises:
[0047] Determining the delay parameters of the reference delay chain using the first clock signal and the second clock signal during the calibration phase;
[0048] During the working delay chain working phase, the delay parameters of the reference delay chain are detected and updated in real time, and the delay parameters of the working delay chain are updated according to the updated delay parameters of the reference delay chain.
[0049] The digital delay chain control circuit and method provided by the embodiment of the present invention can determine the calibration parameters of all signals covering the target working frequency range by using clock signals of two clock frequencies, and can determine the delay parameters of the working delay chain by mapping the first calibration parameter based on the reference delay chain to the second calibration parameter based on the working delay chain and obtaining the accuracy parameter of the working delay chain. By using the scheme of the present invention, the requirements for the hardware circuit can be reduced while obtaining the delay accuracy of the target range.
[0050] Furthermore, by setting different adjustment step parameters for different application scenarios, the convenience of the adjustment operation and the flexibility of the solution are effectively improved, and it can prevent the delay control value from suddenly changing and failing to work normally due to abnormal sampling results. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] Figure 1 It is a schematic diagram of the structure of an existing digital delay chain;
[0052] Figure 2 is a structural schematic diagram of a digital delay chain control circuit provided by an embodiment of the present invention;
[0053] Figure 3 is a schematic diagram of a structure of a reference module and its relationship with a control module in an embodiment of the present invention;
[0054] Figure 4 It is a schematic diagram of a structure of a working module and its relationship with a control module in an embodiment of the present invention;
[0055] Figure 5 is a flow chart of a digital delay chain control method provided by an embodiment of the present invention;
[0056] Figure 6 This is another flow chart of the digital delay chain control method provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0057] The principle and spirit of the present invention will be described below with reference to the exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way.
[0058] In view of the problems of complex control structure and unstable delay control value of digital delay chain in the prior art, the embodiment of the present invention provides a digital delay chain control circuit and method. Before the working delay chain starts working, a first calibration parameter based on the reference delay chain is measured by the reference delay chain, and then the first calibration parameter is mapped to a second calibration parameter based on the working delay chain, and the precision parameter of the working delay chain is obtained by measurement. In this way, after the working delay chain starts working, its delay parameter can be adjusted according to the second calibration parameter and the precision parameter of the working delay chain, and the delay parameter is used to achieve precise control of the working delay chain, ensure the precision of the working delay chain, and achieve precise delay of the working signal.
[0059] like Figure 2 , which is a structural schematic diagram of a digital delay chain control circuit provided by an embodiment of the present invention.
[0060] The digital delay chain control circuit comprises: a control module 20, a clock generation module 30, a reference module 40 and a working module 50 respectively connected to the control module 20. The reference module 40 comprises a reference delay chain 401, and the working module 50 comprises a working delay chain 501.
[0061] The clock generation module 30 is used to provide multiple clock signals with fixed frequencies that do not change with temperature and voltage;
[0062] The control module 20 is used to calibrate the working delay chain 501 before it starts working. During the calibration phase, according to the multiple clock signals provided by the clock generation module 30, the reference module 40 measures and obtains a first calibration parameter based on the reference delay chain 401, maps the first calibration parameter to a second calibration parameter based on the working delay chain 501, and measures and obtains a precision parameter of the working delay chain 501 through the working module 50; and is also used to determine the delay parameter of the working delay chain 501 according to the second calibration parameter and the precision parameter after the working delay chain 501 starts working;
[0063] The working module 50 is used to input a working signal, delay the working signal according to the delay parameter, and output a delayed working signal during the working delay chain 501 working phase.
[0064] During the calibration stage, the control module 20 selects two first clock signals f1 and second clock signals f2 that are closest to the target operating frequency from the multiple reference clock signals in turn as reference signals, uses the reference module to obtain a first reference delay value corresponding to the first clock signal f1 and a second reference delay value corresponding to the second clock signal, and obtains a first calibration parameter based on the first reference delay value and the second reference delay value.
[0065] It should be noted that the first clock signal f1 and the second clock signal f2 may be clock signals with a frequency lower than or higher than the target operating frequency, respectively.
[0066] like Figure 3 FIG. 1 is a schematic diagram showing a structure of a reference module and its relationship with a control module in an embodiment of the present invention.
[0067] In this embodiment, the reference module 40 includes: a reference delay chain 401, an inherent delay channel 402, a first multiplexer 403, a first phase controller 404, and a first phase detector 405. The inherent delay channel 402 can be a path with a certain delay formed by connecting a number of logic gates in series.
[0068] In this embodiment:
[0069] The first multiplexer 403 is used to input a plurality of clock signals with fixed frequencies, and select one of the clock signals as a reference signal to output to the first phase controller 404;
[0070] The first phase controller 404 is used to perform frequency division and phase shifting on the reference signal, and output a first phase shifted signal a and a second phase shifted signal b. The phases of the first phase shifted signal a and the second phase shifted signal b may be the same or differ by 90 degrees.
[0071] It should be noted that, in another non-limiting embodiment, the above-mentioned first multiplexer 403 and the first phase controller 404 can also be used as an independent module. For the convenience of description, the independent module is called a signal processing module. That is to say, the signal processing module divides the frequency and shifts the phase of the reference signal, and outputs the first phase-shifted signal a and the second phase-shifted signal b to the inherent delay channel 402 and the reference delay chain respectively.
[0072] Accordingly, the inherent delay channel 402 performs a fixed delay on the first phase-shifted signal a and outputs a first delayed signal;
[0073] The reference delay chain 401 delays the second phase-shifted signal b and outputs a second delayed signal.
[0074] The first phase detector 405 is used for outputting a first detection signal according to the first delayed signal and the second delayed signal.
[0075] like Figure 3 As shown, the first phase detector 405 can adopt a D flip-flop, and the second delayed signal output by the reference delay chain 401 is used as the clock signal of the D flip-flop, and the first delayed signal output by the inherent delay channel 402 is input into the D input terminal of the D flip-flop, and the Q output terminal of the D flip-flop outputs the detection information and feeds it back to the control module 20.
[0076] In this embodiment, the control module 20 needs to adjust the delay control value of the reference delay chain 401 until a transition edge is detected in the detection signal output from the Q output terminal, and obtain the reference delay value Cset of the reference delay chain at this time.
[0077] Accordingly, the control module 20 calibrates the working delay chain before it starts working, and the calibration process is as follows: select two first clock signals f1 and second clock signals f2 that are closest to the target working frequency from the multiple reference clock signals as reference signals, and obtain the corresponding first reference delay value Cset_1 and second reference delay value Cset_2 for the first clock signal f1 and second clock signal f2 respectively. The first reference delay value Cset_1 and the second reference delay value Cset_2 can be specifically determined in the following manner:
[0078] refer to Figure 3 For the above-mentioned first clock signal f1, the first phase controller 404 is used to shift its phase, and the two phase-shifted signals are respectively input into the inherent delay channel 402 and the reference delay chain 401. The delay value of the reference delay chain 401 is adjusted through the control module 20. When the first detection signal output by the D trigger 405 jumps, the delay value of the reference delay chain 401 corresponding to the jump is the first reference delay value Cset_1.
[0079] Similarly, for the above-mentioned second clock signal f2, its phase is shifted by the first phase controller 404, and the two phase-shifted signals are respectively input into the inherent delay channel 402 and the reference delay chain 401, and the delay value of the reference delay chain 401 is adjusted by the control module 20. When the first detection signal output by the D trigger 405 jumps, the delay value of the reference delay chain 401 corresponding to the jump is the second reference delay value Cset_2.
[0080] Then, the first calibration accuracy U[i] based on the reference delay chain is determined according to the first reference delay value Cset_1 and the second reference delay value Cset_2. The first calibration accuracy U[i] refers to the average unit accuracy delay based on the reference delay chain, which can be specifically calculated using the following formula:
[0081]
[0082] The first calibration parameter is calculated based on the first calibration accuracy U[i], that is, Wherein, T is the target delay value of the working delay chain.
[0083] Considering the error between the working delay chain and the reference delay chain, it is also necessary to map the first calibration parameter determined based on the reference delay chain to the second calibration parameter of the working delay chain.
[0084] Specifically, it can be done by Figure 2 The working module 50 in the embodiment measures and obtains the precision parameter Walign[i] of the working delay chain 501; then, according to the first calibration parameter and the measured precision parameter of the working delay chain 501, the second calibration parameter Z[i] based on the working delay chain is determined, and the calculation formula is as follows:
[0085]
[0086] The second calibration parameter Z[i] is the delay parameter required for the working delay chain 501. Accordingly, after the calibration is completed, the working stage is entered. In the working stage, the working module 50 inputs the working signal and delays the working signal according to the delay parameter, and outputs the delayed working signal.
[0087] In one non-limiting embodiment, Figure 2 The digital delay chain control circuit provided by the embodiment of the present invention shown may further include: a calculation module (not shown), used to obtain the above-mentioned first reference delay value Cset_1 and the second reference delay value Cset_2 from the control module 20, and calculate the above-mentioned first calibration parameter based on the first reference delay value Cset_1 and the second reference delay value Cset_2, and then return the first calibration parameter to the control module 20.
[0088] Combine the following Figure 4 The structure of the working module shown details the process of determining the accuracy parameter Walign[i] of the working delay chain 501.
[0089] Reference Figure 4 , Figure 4 A schematic diagram of the structure of a working module in an embodiment of the present invention is shown.
[0090] The working module 50 includes: a working delay chain 501, a second multiplexer 503, a second phase controller 504, a signal switching module 505, and a second phase detector 502. Among them, another functional delay channel 60 is passed between the second phase controller 504 and the second phase detector 502.
[0091] It should be noted that the other function delay channel 506 and Figure 3The inherent delay channel 402 is different from the inherent delay channel 402 in the reference module 40, which is a channel with a fixed delay specially set for calibration test in the reference module 40, and can be implemented by a corresponding delay module; Figure 4 The other functional delay channel 60 is a delay channel formed by other functional modules in the FPGA other than the digital delay chain control circuit provided by the present invention. No matter what kind of functional module, all have a fixed delay, so they can play the same role.
[0092] In this embodiment, the second multiplexer 503 is used to input a plurality of clock signals with fixed frequencies and output one of the clock signals;
[0093] The second phase controller 504 is used to perform frequency and phase shifting on the clock signal output by the second multiplexer 503, and output a third phase shifted signal c and a fourth phase shifted signal d;
[0094] The signal switching module 505 is used to transmit the third phase-shifted signal c to the working delay chain 501 during the calibration phase; and transmit the working signal to the working delay chain 501 during the working phase;
[0095] The working delay chain 501 is used to delay the signal output by the signal switching module 505, and output a third delay signal or a working delay signal; the third delay signal is the delay signal output by the working delay chain 501 in the calibration phase, and the working delay signal is the delay signal output by the working delay chain 501 in the working phase.
[0096] The other function delay channel 60 delays the fourth phase-shifted signal d and outputs a fourth delayed signal to the second phase detector 502 .
[0097] The second phase detector 502 is used for outputting a second detection signal according to the third delayed signal and the fourth delayed signal.
[0098] Similarly, the second phase detector 502 in this embodiment can also adopt a D flip-flop. Figure 4 The clock input terminal of the D flip-flop inputs the fourth delay signal, the data input terminal of the D flip-flop inputs the third delay signal, and the Q output terminal of the D flip-flop outputs the second detection signal.
[0099] It should be noted that in a specific application, the third delayed signal and the fourth delayed signal may be interchanged, that is, the third delayed signal is input into the clock input terminal of the second phase detector 502 , and the fourth delayed signal is input into the data input terminal of the second phase detector 502 .
[0100] Correspondingly, the control module 20 adjusts the delay control value of the working delay chain 501 to obtain the delay control value when the second detection signal corresponding to the calibration signal jumps, and uses the delay control value as the accuracy parameter Walign[i] of the working delay chain 501.
[0101] It should be noted that in another non-limiting embodiment of the digital delay chain control circuit of the present invention, after the working delay chain starts working, the control module 20 can also use the reference module 40 to perform real-time calibration on the working delay chain 501, update the second calibration parameters, and obtain updated second calibration parameters; and update the delay parameters of the working delay chain 501 according to the updated second calibration parameters and the accuracy parameters.
[0102] In addition, it should be noted that, in a specific application, there may be multiple working delay chains, that is, multiple working delay channels. Accordingly, the delay parameters of each working delay channel may be determined in turn in the above manner.
[0103] The digital delay chain control circuit provided by the embodiment of the present invention can determine the calibration parameters of all signals covering the target working frequency range by using clock signals of two clock frequencies, and can determine the delay parameters of the working delay chain by mapping the first calibration parameter based on the reference delay chain to the second calibration parameter based on the working delay chain and obtaining the accuracy parameter of the working delay chain. By using the scheme of the present invention, the requirements for the hardware circuit can be reduced while obtaining the delay accuracy of the target range.
[0104] Furthermore, in another non-limiting embodiment of the digital delay chain control circuit of the present invention, the above-mentioned control module 20 is also used to determine the delay parameter Rset[i] of the reference delay chain using the first clock signal f1 or the second clock signal f2 during the calibration phase; in the working delay chain working phase, the delay parameter Rset[i] of the reference delay chain is detected and updated in real time, and the delay parameter Wset[i] of the working delay chain is updated according to the updated delay parameter Rnew[i] of the reference delay chain.
[0105] The way in which the delay parameter Rset[i] of the reference delay chain is determined during the calibration phase is similar to the way in which the accuracy parameter Wset[i] of the working delay chain is determined.
[0106] Combine the following Figure 3 The structural diagram of the reference module shown takes the first clock signal f1 as an example of the reference signal to illustrate in detail the process of determining the delay parameter Rset[i] of the reference delay chain.
[0107] Reference Figure 3, the first clock signal f1 is input to the first phase controller 404. One of the two phase-shifted signals corresponding to the first clock signal f1 or the second clock signal f2 output by the first phase controller 404 is input to the clock input terminal of the first phase detector 405 through the reference delay chain 401, and the other phase-shifted signal is input to the data input terminal of the first phase detector 405. The control module 20 adjusts the delay control value of the reference delay chain 401, and obtains the delay control value of the reference delay chain 401 when the signal at the Q output terminal of the first phase detector 405 jumps. This delay control value is the precision parameter of the reference delay chain 401. According to this precision parameter, the calibration parameter Rset[i] based on the reference delay chain is then calculated using the above formula (1).
[0108] Since Figure 2 the working delay chain 501 and the reference delay chain 401 in it are each independently controlled by the control module 20 and are not affected by each other. Therefore, during the working stage of the working delay chain, the control module 20 can detect and update the calibration parameter of the reference delay chain in real time, and obtain the updated calibration parameter Rnew[i] based on the reference delay chain. The measurement process of Rnew[i] is the same as that of Rset[i], which will not be elaborated here.
[0109] To facilitate the delay parameter Wset[i] of the working delay chain, in the embodiment of the present invention, a variable of adjustment step step can be introduced, and a marker parameter flag[i] for indicating parameter update is calculated based on the delay parameter Rset[i] before update and the delay parameter Rnew[i] after update of the reference delay chain. The calculation formula is as follows:
[0110]
[0111] If flag[i]>1, it indicates that the delay control value (i.e., the delay parameter Wset[i]) of the working delay chain needs to be adjusted; otherwise, no adjustment is made.
[0112] It should be noted that step, as a proportional adjustment factor, can be set by the user to achieve adjustment according to different application scenarios. The specific adjustment method is as follows:
[0113] If flag[i]>1 for the working delay chain and Rnew[i]>Rset[i], then Rset[i]=Rset[i]+1 and Wset[i]=Wset[i]+1; if flag[i]>1 for the working delay chain and Rnew[i]<Rset[i], then Rset[i]=Rset[i]-1 and Wset[i]=Wset[i]-1;
[0114] If flag[i]≤1 of the working delay chain, Rset[i] and Wset[i] remain unchanged.
[0115] By configuring the step parameters for different application scenarios, on the one hand, the flexibility of the solution can be effectively improved, so that the solution of the present invention can be better applied to different scenarios. For example, if the temperature and voltage of the application scenario change greatly, the step value can be increased; if the temperature and voltage of the application scenario are relatively stable, the default step value is updated, and the default step value can be a value selected in advance through testing; on the other hand, this gradual accumulation or subtraction adjustment method will not cause sudden changes, so it can effectively prevent the sampling results from being abnormal (such as signal jitter, phase detector output detection result errors, etc.) causing the delay control value to suddenly change and fail to work normally.
[0116] It should be noted that, in practical applications, there may be multiple working delay chains, and the target operating frequencies of different working delay chains may be the same or different. The calibration of these different working delay chains can be calibrated one by one based on the same reference delay chain. The only difference is that the frequency of the clock signal selected during calibration should be a clock signal close to the target operating frequency of the working delay to be calibrated, and the calibration process is exactly the same.
[0117] Accordingly, an embodiment of the present invention further provides a digital delay chain control method. Figure 5 , Figure 5 : is a flow chart of a digital delay chain control method provided by an embodiment of the present invention, the method comprising the following steps:
[0118] In step 501, before the working delay chain starts working, it is calibrated. The calibration process includes the following steps:
[0119] Step 511, obtaining a first calibration parameter based on a reference delay chain;
[0120] Step 512, mapping the first calibration parameter to a second calibration parameter based on a working delay chain;
[0121] Step 513, obtaining the accuracy parameter of the working delay chain;
[0122] Step 514, determining a delay parameter of the working delay chain according to the second calibration parameter and the accuracy parameter;
[0123] In step 502, after the working delay chain starts to work, the working signal input by the working delay chain is delayed according to the delay parameter to output a delayed working signal.
[0124] In the above step 511, the first calibration parameter may be determined specifically according to the following process:
[0125] (1) selecting in sequence a first clock signal and a second clock signal which are closest to the target operating frequency as reference signals;
[0126] (2) using a reference delay chain to obtain a first reference delay value corresponding to the first clock signal and a second reference delay value corresponding to the second clock signal;
[0127] (3) Determine the first calibration parameter according to the first reference delay value and the second reference delay value.
[0128] In the above step 513, the precision parameter of the working delay chain may be obtained in the following manner:
[0129] (1) Select a clock signal that is closest to the target operating frequency as the calibration signal;
[0130] (2) By adjusting the delay value of the working delay chain, the accuracy parameter of the working delay chain is obtained.
[0131] like Figure 6 As shown, in another non-limiting embodiment of the method of the present invention, the following steps may also be included:
[0132] In step 515, the delay parameters of the reference delay chain are determined using the first clock signal and the second clock signal during the calibration phase;
[0133] In step 503, during the working delay chain working phase, the delay parameters of the reference delay chain are detected and updated in real time, and the delay parameters of the working delay chain are updated according to the updated delay parameters of the reference delay chain.
[0134] The updating process of the delay parameters mentioned above can be found in the description of the digital delay chain control circuit embodiment of the present invention, which will not be described in detail here.
[0135] The digital delay chain control method provided by the embodiment of the present invention uses clock signals of two clock frequencies to determine the calibration parameters of all signals covering the target working frequency range, and maps the first calibration parameter based on the reference delay chain to the second calibration parameter based on the working delay chain, and obtains the accuracy parameter of the working delay chain, thereby determining the delay parameter of the working delay chain. By using the scheme of the present invention, the requirements for the hardware circuit can be reduced, while the delay accuracy of the target range can be obtained.
[0136] Furthermore, in another non-limiting embodiment of the digital delay chain control method of the present invention, by introducing the variable of adjustment step size step, the adjustment operation can be made simple, convenient and efficient, which greatly effectively improves the flexibility of the scheme and prevents the situation in which the delay control value suddenly changes and cannot work normally due to abnormal sampling results.
[0137] In a specific implementation, each module / unit included in each device or product described in the above embodiments may be a software module / unit or a hardware module / unit, or may be partly a software module / unit and partly a hardware module / unit.
[0138] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.
[0139] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A digital delay chain control circuit, characterized in that: The circuit comprises: a control module, a clock generation module, a reference module and a working module respectively connected to the control module; the reference module comprises a reference delay chain; the working module comprises a working delay chain; The clock generation module is used to provide multiple clock signals with fixed frequencies that do not change with temperature and voltage; The control module is used to calibrate the working delay chain before it starts working, and in the calibration stage, according to the multiple clock signals provided by the clock generation module, obtain the first calibration parameter based on the reference delay chain through the reference module, and obtain the precision parameter of the working delay chain through the working module, and determine the second calibration parameter based on the working delay chain according to the first calibration parameter and the precision parameter of the working delay chain; and is also used to use the second calibration parameter as the delay parameter of the working delay chain after the working delay chain starts working; The working module is used to input a working signal, delay the working signal according to the delay parameter, and output a delayed working signal during the working delay chain working phase.
2. The digital delay chain control circuit according to claim 1, characterized in that: During the calibration phase, the control module sequentially selects two first clock signals and a second clock signal that are closest to the target operating frequency from the multiple reference clock signals as reference signals, uses the reference module to obtain a first reference delay value corresponding to the first clock signal and a second reference delay value corresponding to the second clock signal, and determines the first calibration parameter according to the first reference delay value and the second reference delay value.
3. The digital delay chain control circuit according to claim 2, characterized in that: The reference module further includes: a first multiplexer, a first phase controller, an inherent delay channel, and a first phase detector; The first multiplexer is used to input a plurality of clock signals of fixed frequencies and output one of the clock signals; The first phase controller is used to perform frequency division and phase shift on the clock signal output by the first multiplexer, and output a first phase-shifted signal and a second phase-shifted signal; The inherent delay channel is used to perform a fixed delay on the first phase-shifted signal and output a first delayed signal; The reference delay chain is used to perform an adjustable delay on the second phase-shifted signal and output a second delayed signal; The first phase detector is used to output a first detection signal according to the first delayed signal and the second delayed signal; The control module adjusts the delay value of the reference delay chain to obtain a first reference delay value when the first detection signal corresponding to the first clock signal jumps, and a second reference delay value when the first detection signal corresponding to the second clock signal jumps.
4. The digital delay chain control circuit according to claim 3, characterized in that: The first phase detector is a D flip-flop, the clock input terminal of the D flip-flop inputs the second delay signal, the data input terminal of the D flip-flop inputs the first delay signal, and the Q output terminal of the D flip-flop outputs the first detection signal.
5. The digital delay chain control circuit according to claim 3, characterized in that: The control module adjusts the delay value of the reference delay chain to obtain a first reference delay value when the first detection signal corresponding to the first clock signal jumps, and a second reference delay value when the first detection signal corresponding to the second clock signal jumps.
6. The digital delay chain control circuit according to claim 2, characterized in that: The control module selects a clock signal closest to the target operating frequency from the multiple reference clock signals as a calibration signal during the calibration phase, and obtains the accuracy parameter of the working delay chain by adjusting the delay value of the working module.
7. The digital delay chain control circuit according to claim 3, characterized in that: The working module also includes: a second multiplexer, a second phase controller, a signal switching module, and a second phase detector; The second multiplexer is used to input a plurality of clock signals of fixed frequencies and output one of the clock signals; The second phase controller is used to perform frequency division and phase shifting on the clock signal output by the second multiplexer, and output a third phase-shifted signal and a fourth phase-shifted signal; The signal switching module is used to transmit the third phase-shifted signal to the working delay chain during the calibration phase; and transmit the working signal to the working delay chain during the working phase; The working delay chain is used to delay the signal output by the signal switching module and output a third delay signal or a working delay signal; The second phase detector is used to output a second detection signal according to the third delayed signal and the fourth phase-shifted signal; The control module adjusts the delay value of the working delay chain to obtain the working delay value when the second detection signal corresponding to the calibration signal generates a jump, and uses the working delay value as the accuracy parameter of the working delay chain.
8. The digital delay chain control circuit according to claim 7, characterized in that: The second phase detector is a D flip-flop, the clock input terminal of the D flip-flop inputs the fourth phase-shifted signal, the data input terminal of the D flip-flop inputs the third delayed signal, and the Q output terminal of the D flip-flop outputs the second detection signal.
9. The digital delay chain control circuit according to claim 3, characterized in that: The circuit further comprises: A calculation module is used to obtain the first reference delay value and the second reference delay value from the control module, calculate the first calibration parameter according to the first reference delay value and the second reference delay value, and return the first calibration parameter to the control module.
10. The digital delay chain control circuit according to any one of claims 2 to 9, characterized in that: The control module is also used to determine the delay parameters of the reference delay chain using the first clock signal and the second clock signal during the calibration phase; in the working delay chain working phase, the delay parameters of the reference delay chain are detected and updated in real time, and the delay parameters of the working delay chain are updated according to the updated delay parameters of the reference delay chain.
11. A digital delay chain control method, characterized in that: The method comprises: Before the working delay chain starts working, it is calibrated. The calibration process includes: Acquiring a first calibration parameter based on a reference delay chain; Mapping the first calibration parameter to a second calibration parameter based on a working delay chain; Obtaining the accuracy parameters of the working delay chain; Determining a delay parameter of the working delay chain according to the second calibration parameter and the accuracy parameter; After the working delay chain starts to work, the working signal input by the working delay chain is delayed according to the delay parameter to output a delayed working signal.
12. The digital delay chain control method according to claim 11, characterized in that: The obtaining of a first calibration parameter based on a reference delay chain comprises: Selecting in sequence a first clock signal and a second clock signal which are closest to the target operating frequency as reference signals; Acquire a first reference delay value corresponding to the first clock signal and a second reference delay value corresponding to the second clock signal by using a reference delay chain; The first calibration parameter is determined according to the first reference delay value and the second reference delay value.
13. The digital delay chain control method according to claim 12, characterized in that: The step of obtaining the accuracy parameter of the working delay chain includes: Select a clock signal that is closest to the target operating frequency as the calibration signal; By adjusting the delay value of the working delay chain, the accuracy parameter of the working delay chain is obtained.
14. The digital delay chain control method according to claim 12 or 13, characterized in that: The method further comprises: Determining the delay parameters of the reference delay chain using the first clock signal and the second clock signal during the calibration phase; During the working delay chain working phase, the delay parameters of the reference delay chain are detected and updated in real time, and the delay parameters of the working delay chain are updated according to the updated delay parameters of the reference delay chain.