Manufacturing method of power MOSFET device and power MOSFET device

Abstract

The invention relates to a manufacturing method of a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and the power MOSFET device. In the manufacturing method, the MOSFET device is of an N type; the manufacturing method comprises a step of forming a shield gate structure, and in the step of forming the shield gate structure, after a step of growing a gate oxide layer, a step of growing and removing high-stress silicon nitride is added, specifically, firstly, a silicon nitride film is deposited on the gate oxide layer and an IPO oxide layer in a PECVD mode, and then annealing is carried out; secondly, completely removing the silicon nitride film; and after the step of growing and removing the high-stress silicon nitride, a step of growing gate polycrystalline silicon is carried out.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a manufacturing method for reducing the internal resistance of a low-voltage power MOSFET device. Background Art

[0002] Power MOSFET devices are widely used in switching applications, playing the role of power conversion and control, providing the required voltage and current for various electrical equipment and instruments. However, with the improvement of device structure and the progress and development of process technology, the continued reduction of internal resistance has encountered bottlenecks, which directly affects the further improvement of the efficiency of systems using power MOSFET.

[0003] According to the research and comparison in this field, the proportion of internal resistance distribution of devices with different voltage levels is different. For high-voltage MOSFET devices (maximum breakdown voltage greater than 200V), more than 70% of the internal resistance comes from epitaxy; while for low-voltage MOSFET devices (such as MOSFET devices with a maximum breakdown voltage of about 50V), channel resistance is the main component of internal resistance. Especially for advanced low-voltage shielded gate MOSFET devices used in DrMOS (Driver MOSFET Integrated Circuit), the proportion of epitaxial resistance and substrate resistance (wafer thickness less than 70 microns) is lower, which further highlights the importance of reducing channel resistance.

[0004] In order to reduce the channel resistance of low-voltage power MOSFET devices, the usual approach is to reduce the channel length or improve the surface state of the silicon gate contact surface through the process. However, such an approach will cause channel penetration leakage and the degree of reduction in internal resistance is limited. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention discloses a method for manufacturing a power MOSFET device and a power MOSFET device.

[0006] The technical solution adopted by the present invention is as follows:

[0007] A method for manufacturing a power MOSFET device, wherein the MOSFET device is of N type; the method comprises the step of forming a shielded gate structure, wherein in the step of forming the shielded gate structure, after the step of growing a gate oxide layer, a step of growing and removing high stress silicon nitride is added, specifically:

[0008] First, a silicon nitride film is deposited on the gate oxide layer and the IPO oxide layer by PECVD, and then annealed;

[0009] Secondly, the silicon nitride film is completely removed;

[0010] After the high stress silicon nitride growth and cleaning steps, a gate polysilicon growth step is performed.

[0011] A further technical solution is: after silicon nitride is deposited by PECVD, a rapid annealing process is used in a nitrogen environment, with an annealing temperature ranging from 1000°C to 1050°C and a time of 0.5msec to 2sec.

[0012] A further technical solution is to use a phosphoric acid solution to remove the silicon nitride film.

[0013] Its further technical solution is: in the process of depositing silicon nitride film by PECVD, the temperature range is 360℃±10℃, the ratio of reaction gas ammonia NH3 and silane SiN4 is 1.05-1.15, the reaction pressure is 600mToor, the RF frequency is 13MHz, and the power is 12W±10%.

[0014] A further technical solution is as follows: the manufacturing method further comprises growing an N-type epitaxial layer on the substrate; and forming a shielding gate structure in the N-type epitaxial layer.

[0015] A further technical solution is: the step of forming the shielding grid structure further includes:

[0016] forming grooves;

[0017] depositing source polysilicon in the trench to backfill the trench;

[0018] Etching the source polysilicon; etching the target thickness of the source polysilicon in the groove by photolithography and etching, wherein the thickness of the etched source polysilicon is less than the depth of the groove;

[0019] Depositing a dielectric layer; depositing a dielectric layer in the trench, backfilling the trench, and then performing photolithography and etching to etch away excess dielectric layer to form an IPO oxide layer;

[0020] growing a gate oxide layer;

[0021] performing the high stress silicon nitride growth and removal steps;

[0022] Gate polysilicon is grown to backfill the trench and form a shielding gate structure in the trench.

[0023] A further technical solution is: after the step of forming the shielding grid structure, the manufacturing method further comprises:

[0024] P-type impurities are injected into both sides of the trench, and annealed to form a body region; then, N-type impurities are injected into the body region through a photolithography process to form a source region;

[0025] Then, the steps of forming contact holes and depositing metal are performed: depositing a contact hole dielectric layer, followed by photolithography and etching to form contact holes, and depositing contact hole metal; and then depositing source metal.

[0026] A power MOSFET device manufactured according to the manufacturing method of a power MOSFET device as described in any of the above items, comprising a shielded gate structure formed in a trench, the shielded gate structure comprising gate polysilicon and source polysilicon; a field oxide layer is formed between the source polysilicon and the inner wall of the trench, and a gate oxide layer is formed between the gate polysilicon and the inner wall of the trench; an IPO oxide layer is formed between the source polysilicon and the gate polysilicon; in an epitaxial layer corresponding to the position of the gate oxide layer, a strained silicon layer is provided in close contact with the outer side wall of the trench; the lattice spacing of the strained silicon layer is wider than the lattice spacing of other silicon structures in the epitaxial layer.

[0027] The beneficial effects of the present invention are as follows:

[0028] The present invention adds high stress silicon nitride growth and removal steps in the manufacturing method of power MOSFET devices, and the growth of silicon nitride is carried out by using PECVD. The silicon nitride film deposited by PECVD has high stress. The silicon nitride film generates stress on silicon, and after the silicon nitride film is removed, the stress remains in the silicon.

[0029] When tensile stress acts on NMOS <100> or <110> In the crystal direction channel, the speed of NMOS increases with the increase of stress, while for compressive stress, the opposite is true, the speed of NMOS decreases with the increase of compressive stress. According to the definition of electron mobility The conductivity (ρ=nqu) is obtained. It can be seen that when the electron velocity increases, the electron mobility will increase, and then the conductivity will increase or the resistivity will decrease.

[0030] Therefore, by using the manufacturing method of increasing the tensile stress of silicon proposed in the present invention, the lattice spacing of silicon is widened. When a voltage is applied between the gate and source of the MOSFET to form a channel, the migration rate of the carriers will increase, effectively improving the mobility of the channel region, thereby reducing the on-state internal resistance of the MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 FIG. 4 is a schematic diagram of a step of forming a groove in an embodiment of the present invention.

[0032] Figure 2 Schematic diagram of the step of backfilling the trench in an embodiment of the present invention.

[0033] Figure 3 Schematic diagram of the step of etching source polysilicon in an embodiment of the present invention.

[0034] Figure 4Schematic diagram of the step of depositing a dielectric layer in an embodiment of the present invention.

[0035] Figure 5 Schematic diagram of the steps of growing a gate oxide layer and silicon nitride in an embodiment of the present invention.

[0036] Figure 6 Schematic diagram of the step of removing silicon nitride in an embodiment of the present invention.

[0037] Figure 7 Schematic diagram of the step of depositing gate polysilicon in an embodiment of the present invention.

[0038] Figure 8 Schematic diagram of the step of forming a body region in an embodiment of the present invention.

[0039] Fig. 9 It is a schematic diagram of the steps of forming a source region, a contact hole and depositing metal in an embodiment of the present invention.

[0040] In the figure: 100, substrate; 101, epitaxial layer; 102, trench; 103, field oxide layer; 104, source polysilicon; 105, gate oxide layer; 106, silicon nitride film; 107, gate polysilicon; 108, body region; 109, source region; 110, contact hole metal; 111, source metal. DETAILED DESCRIPTION

[0041] The specific implementation of the present invention will be described below in conjunction with the accompanying drawings.

[0042] The embodiment of the present invention discloses a method for manufacturing a power MOSFET device. Fig. 9 It is a schematic diagram of the steps of forming a source region, a contact hole and depositing metal in an embodiment of the present invention. Fig. 9 The structure of the MOSFET device manufactured by the manufacturing method of the power MOSFET device disclosed in the embodiment of the present invention is shown as a whole. The MOSFET device in the embodiment of the present invention is an NMOS type. Fig. 9 As shown, the power MOSFET device includes a substrate 100 and an epitaxial layer 101 grown on the substrate 100. A groove 102 is opened in the epitaxial layer 101. A shielding gate structure is arranged in the groove 102. Specifically, the shielding gate structure includes a gate polysilicon 107 and a source polysilicon 104. A field oxide layer 103 is formed between the source polysilicon 104 and the inner wall of the groove 102, and a gate oxide layer 105 is formed between the gate polysilicon 107 and the inner wall of the groove 102. An IPO oxide layer is formed between the source polysilicon 104 and the gate polysilicon 107. In the epitaxial layer 101 corresponding to the position of the gate oxide layer 105, there is a strained silicon layer close to the outer wall of the groove 102. The lattice spacing of the strained silicon layer is wider than that of other parts in the epitaxial layer 101, that is, the lattice spacing of the silicon structure of the strained silicon layer.

[0043] P-type impurities are doped on both sides of the trench 102 to form a body region 108, and an active region 109 is grown on the body region 108 on both sides of the trench 102. The source region 109 serves as the source of the device and is short-circuited with the source metal 111 through the contact hole metal 110. The source region 109 is also short-circuited with the source polysilicon 104 inside the MOSFET device.

[0044] In the MOSFET device structure, the strained silicon layer is formed by adding high-stress silicon nitride growth and removal steps in the manufacturing method of the power MOSFET device, and the growth of silicon nitride is achieved by using PECVD. The silicon nitride film deposited by PECVD has a high stress. The silicon nitride film exerts stress on silicon, and after the silicon nitride film is removed, the stress remains in the silicon, increasing the tensile stress of silicon and widening the lattice spacing of silicon. When a voltage is applied between the gate and source of the MOSFET to form a channel, the migration rate of the carriers will increase, effectively improving the mobility of the channel region, thereby reducing the on-state internal resistance of the MOSFET device.

[0045] The manufacturing method of the power MOSFET device disclosed in the embodiment of the present invention is specifically as follows:

[0046] Step 1: Forming a groove. Figure 1 FIG. 1 is a schematic diagram of a step of forming a groove in an embodiment of the present invention. Figure 1 As shown, an epitaxial layer 101 is grown on a substrate 100. Specifically, an N-type epitaxial layer 101 with a target thickness and a target doping concentration is formed on the substrate 100. A trench 102 with a target depth is formed by a first photolithography, etching, and other processes, and a dielectric layer with a target thickness is formed at the bottom and sidewalls of the trench 102 as a field oxide layer 103 by, but not limited to, thermal oxidation, CVD deposition, and other methods.

[0047] The target thickness and target doping concentration in this step and subsequent steps are determined according to the device model and functional parameters, and can be specifically adjusted by those skilled in the art according to known techniques.

[0048] Step 2: Backfill the trench. Figure 2 FIG. 1 is a schematic diagram of the step of backfilling the trench in an embodiment of the present invention. Figure 2 As shown, source polysilicon 104 is deposited in the trench 102 , the trench 102 is backfilled, and the surface of the trench 102 is planarized by CMP.

[0049] Step 3: Etching the source polysilicon. Figure 3 FIG. 1 is a schematic diagram of the step of etching source polysilicon in an embodiment of the present invention. Figure 3 As shown, through the second photolithography and etching, the source polysilicon 104 of the target thickness is etched away in the trench 102 , and the thickness of the etched source polysilicon 104 is smaller than the depth of the trench 102 .

[0050] Step 4: Deposit a dielectric layer. Figure 4 Schematic diagram of the step of depositing a dielectric layer in an embodiment of the present invention. A dielectric layer of target thickness is deposited in the trench 102, the trench 102 is backfilled, and the silicon surface is planarized by CMP, and then a third photolithography and etching are performed to etch away the dielectric layer of target thickness as an IPO oxide layer, so that the final result is as follows Figure 4 shown.

[0051] Step 5: grow a gate oxide layer. Figure 5 Schematic diagram of the steps of growing a gate oxide layer and silicon nitride in an embodiment of the present invention. Figure 5 After cleaning the silicon sidewalls exposed in the upper part of the trench 102 , a gate oxide layer 105 of a target thickness is grown in the trench 102 .

[0052] Step 6: High stress silicon nitride growth and removal.

[0053] Specifically, high stress silicon nitride is first grown. Figure 5 , a silicon nitride film 106 is deposited on the gate oxide layer 105 and the IPO oxide layer in the trench 102 by PECVD, and then annealed in a nitrogen environment, and the annealing temperature range is 1100°C ± 5°C. In the process of depositing the silicon nitride film 106 by PECVD, the temperature range can be controlled at 360°C ± 10°C, the ratio of the reaction gas silane and ammonia is 1 to 1.1, the reaction pressure is 600mToor to 650Toor, the radio frequency frequency is 13MHz, and the power is 15W to 20W.

[0054] In this process, the silicon nitride film 106 deposited by PECVD has a high stress, and the silicon nitride film 106 generates stress on silicon, that is, in the epitaxial layer 101 corresponding to the position of the gate oxide layer 105, a strained silicon layer is generated close to the outer wall of the trench 102. The lattice spacing of the strained silicon layer is wider than that of the non-strained silicon structure in the epitaxial layer 101, that is, the lattice spacing of the silicon structure of the strained silicon layer is wider.

[0055] Next, the silicon nitride is removed. Figure 6 Schematic diagram of the step of removing silicon nitride in an embodiment of the present invention. Figure 6 As shown, the silicon nitride film 106 is removed using a phosphoric acid solution.

[0056] After the silicon nitride film 106 is removed, stress remains in the strained silicon structure of the epitaxial layer 101 .

[0057] Step 7: deposit gate polysilicon. Figure 7 FIG. 2 is a schematic diagram of the step of depositing gate polysilicon in an embodiment of the present invention. Figure 7As shown, after cleaning, gate polysilicon 107 of a target thickness is deposited in the trench 102 , the trench 102 is backfilled, and the surface is planarized by CMP, and a shield gate structure is formed in the trench 102 .

[0058] Figure 8 Schematic diagram of the step of forming a body region in an embodiment of the present invention. Fig. 9 Schematic diagram of the steps of forming source regions, contact holes and depositing metal in an embodiment of the present invention. Figure 8 and Fig. 9 , further, the manufacturing method further comprises the following steps:

[0059] Step 8, forming body and source regions. Inject impurities, anneal, and inject P-type impurities on both sides of the trench 102 to form the body region 108. Then, after the fourth photolithography process, inject N-type impurities to form the device source region 109. The source region 109 is electrically connected to the source polysilicon 104.

[0060] Step 9: forming contact holes. Depositing a contact hole dielectric layer of target thickness, followed by a fifth photolithography process, etching to form contact holes, and depositing contact hole metal 110.

[0061] Step 8: Deposit metal. Deposit source metal 111. Contact hole metal 110 electrically connects source region 109 to source metal 111. Then, the sixth photolithography process is performed, metal etching is performed, and a dielectric layer is deposited. Then, the seventh photolithography process is performed to etch the dielectric layer to form a device protection layer. The final device structure is as follows: Fig. 9 shown.

[0062] In this embodiment, the specific process parameters of steps 1 to 5, and steps 6 to 8 are adjusted and selected by technicians in this field based on general process knowledge and device parameter requirements of integrated circuits. The specific process parameters are not the content to be protected by this application and will not be repeated in this article.

[0063] Table 1 shows the stress test values ​​and on-resistance test values ​​of the MOSFET device manufactured according to the method shown in this embodiment. Table 1 also shows the stress test values ​​and on-resistance test values ​​of the MOSFET device in a set of control experiments.

[0064]

[0065] In each group of experiments in Table 1, except for the high stress silicon nitride growth and removal steps, the other manufacturing process parameters of the MOSFET device are the same. Specifically, in each experiment shown in Table 1, the manufactured MOSFET device is an N-type 30V device, and the other process steps corresponding to the device parameters are as follows. Of course, those skilled in the art can know that the specific parameters of the following process steps are closely related to the device parameters and actual needs. In the specific implementation process, the various parameters in the manufacturing process can be adjusted as needed, and these parameters do not limit the protection content of the present invention:

[0066] Step 1a, forming a trench. An epitaxial layer 101 is grown on the substrate 100. The thickness of the epitaxial layer 101 is 2.8um, the resistivity of the epitaxial layer 101 is 0.065Ω·cm, and the depth of the trench 102 is 1.3um. A thermal oxidation method is used to form a A dielectric layer with a thickness of Å serves as the field oxide layer 103 .

[0067] Step 2a, backfilling the trench: Depositing source polysilicon 104 in the trench 102, backfilling the trench 102, and planarizing the surface of the trench 102 by CMP.

[0068] Step 3a, etching the source polysilicon: Through the second photolithography and etching, the source polysilicon 104 with a thickness of 0.65 um is etched away in the trench 102 .

[0069] Step 4a, depositing a dielectric layer. Deposit a dielectric layer of target thickness in the trench 102, backfill the trench 102, and planarize the silicon surface by CMP, then perform a third photolithography and etching to etch away the dielectric layer with a thickness of 0.53 um below the silicon surface as an IPO oxide layer.

[0070] Step 5a: growing a gate oxide layer. The thickness of the gate oxide layer 105 is

[0071] Step 6a: High stress silicon nitride growth and removal.

[0072] Specifically, high stress silicon nitride is first grown. Silicon nitride film 106 is deposited on gate oxide layer 105 and IPO oxide layer in trench 102 by PECVD, and then annealed in nitrogen environment, with annealing temperature range of 1100°C. In the process of depositing silicon nitride film 106 by PECVD, the temperature range is controlled at 360°C, the ratio of reaction gas silane and ammonia is 1 to 1.1, the reaction pressure is 600mToor to 650mToor, the RF frequency is 13MHz, and the power is 15W to 20W.

[0073] Next, the silicon nitride film 106 is removed by using a phosphoric acid solution.

[0074] Step 7a, depositing gate polysilicon. After cleaning, gate polysilicon 107 is deposited in the trench 102, the trench 102 is backfilled, and the surface is planarized by CMP. At this time, a shield gate structure is formed in the trench 102.

[0075] Step 8a, forming body and source regions. Inject impurities, anneal, and inject P-type impurities on both sides of the trench 102 to form the body region 108. Then, after the fourth photolithography process, inject N-type impurities to form the device source region 109. The source region 109 is electrically connected to the source polysilicon 104.

[0076] Step 9: Form contact holes. Deposition USG and The contact hole dielectric layer is then subjected to a fifth photolithography process to etch and form a contact hole, and a contact hole metal 110 is deposited.

[0077] Step 8, metal deposition. Deposit source metal 111. Contact hole metal 110 electrically connects source region 109 to source metal 111. Then, perform the sixth photolithography process, metal etching, and deposit a dielectric layer, and then perform the seventh photolithography process to etch the dielectric layer to form a device protection layer.

[0078] In Table 1, the experiment numbered #8 is a control experiment, which uses a general device manufacturing method. There is no high stress silicon nitride growth and removal step in the manufacturing method. After obtaining the MOSFET device, the silicon structure in the MOSFET device is subjected to stress testing and the on-resistance is tested. According to the table, when there is no high stress silicon nitride growth and removal step, the stress in the silicon structure ranges from xx to xx, and its on-resistance Ron value is xx to xx. The specific value difference is due to the normal error of different experimental environments.

[0079] Experiments numbered #1 to #8 are devices obtained using the method in this embodiment. In the step of forming a shielding gate structure, after the step of growing a gate oxide layer, a high stress silicon nitride growth and removal step is added, and a silicon nitride film is grown using the process conditions in Table 1. The film is then annealed at a temperature of 1100°C in a nitrogen environment, and then the silicon nitride film is completely removed using a phosphoric acid solution.

[0080] It can be seen from the data in the table that when growing silicon nitride film, it is necessary to control the SiH4 flow rate and NH3 flow rate ratio at 1:1 to 1:1.1, and maintain the gas pressure at 600 to 650 Toor, the RF frequency at 13W, and the RF power at 15W to 20W. At this time, after removing the silicon nitride film, positive tensile stress can be measured in the strained silicon, and the on-resistance of the MOSFET device is tested, and it can be found that the on-resistance has decreased significantly, which can be reduced to below 1mΩ.

[0081] The above description is an explanation of the present invention, not a limitation of the present invention. The scope of the present invention is defined in the claims. The present invention may be modified in any form without violating the basic structure of the present invention.

Claims

1. A method for manufacturing a power MOSFET device, characterized in that: The MOSFET device is of N type; the manufacturing method includes the step of forming a shielded gate structure, in which a high stress silicon nitride growth and removal step is added after the gate oxide layer growth step in the step of forming the shielded gate structure, specifically: First, a silicon nitride film is deposited on the gate oxide layer and the IPO oxide layer by PECVD, and then annealed; Secondly, the silicon nitride film is completely removed; After the high stress silicon nitride growth and cleaning steps, a gate polysilicon growth step is performed.

2. The method for manufacturing a power MOSFET device according to claim 1, wherein: After silicon nitride is deposited by PECVD, a rapid annealing process is used in a nitrogen environment, with an annealing temperature ranging from 1000° C. to 1050° C. and a time ranging from 0.5 msec to 2 sec.

3. The method for manufacturing a power MOSFET device according to claim 1, wherein: The silicon nitride film is removed using a phosphoric acid solution.

4. The method for manufacturing a power MOSFET device according to claim 1, wherein: In the process of depositing silicon nitride film by PECVD, the temperature range is 360℃±10℃, the ratio of reaction gas ammonia NH3 and silane SiN4 is 1~1.1, the reaction pressure is 600mToor~650Toor, the RF frequency is 13MHz, and the power is 12W~20W.

5. The method for manufacturing a power MOSFET device according to claim 1, wherein: The manufacturing method further comprises growing an N-type epitaxial layer on a substrate; and forming a shielding gate structure in the N-type epitaxial layer.

6. The method for manufacturing a power MOSFET device according to claim 1, characterized in that: The step of forming the shielding grid structure also includes: forming grooves; depositing source polysilicon in the trench to backfill the trench; Etching the source polysilicon; etching the target thickness of the source polysilicon in the groove by photolithography and etching, wherein the thickness of the etched source polysilicon is less than the depth of the groove; Depositing a dielectric layer; depositing a dielectric layer in the trench, backfilling the trench, and then performing photolithography and etching to etch away excess dielectric layer to form an IPO oxide layer; growing a gate oxide layer; performing the high stress silicon nitride growth and removal steps; Gate polysilicon is grown to backfill the trench and form a shielding gate structure in the trench.

7. The method for manufacturing a power MOSFET device according to claim 6, characterized in that: After the step of forming the shielding gate structure, the manufacturing method further comprises: P-type impurities are injected into both sides of the trench, and annealed to form a body region; then, N-type impurities are injected into the body region through a photolithography process to form a source region; Then, the steps of forming contact holes and depositing metal are performed: depositing a contact hole dielectric layer, followed by photolithography and etching to form contact holes, and depositing contact hole metal; and then depositing source metal.

8. A power MOSFET device manufactured by the method for manufacturing a power MOSFET device according to any one of claims 1 to 7, characterized in that: The invention comprises a shielding gate structure formed in a trench, wherein the shielding gate structure comprises gate polysilicon and source polysilicon; a field oxide layer is formed between the source polysilicon and the inner wall of the trench, and a gate oxide layer is formed between the gate polysilicon and the inner wall of the trench; an IPO oxide layer is formed between the source polysilicon and the gate polysilicon; in an epitaxial layer corresponding to the position of the gate oxide layer, a strained silicon layer is provided in close contact with the outer wall of the trench; and the lattice spacing of the strained silicon layer is wider than the lattice spacing of other silicon structures in the epitaxial layer.

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