Power gallium nitride device and forming method thereof

Abstract

The invention discloses a power gallium nitride device and a forming method thereof, and relates to a power semiconductor device, crystal defects are formed in a buffer layer in a wafer manufacturing process, and electrons are injected from a substrate and captured in the crystal defects in the buffer layer under the states of transistor turn-off and high drain bias voltage, so that the power gallium nitride device is formed. In order to overcome the influence of captured electrons on the device, a P-type doped semiconductor region is also arranged below a drain metal layer, and the P-type doped semiconductor region injects holes into a buffer layer 101 to capture the electrons in a drain bias state on the premise of not influencing the conduction, so that the device is more stable in performance. The on-resistance of the device is reduced, and the stability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor devices, and in particular to a method for forming a power gallium nitride device. Background Art

[0002] Compared with silicon materials, gallium nitride materials have larger energy band gaps, higher electron mobility, saturated electron velocity and breakdown electric field. Gallium nitride high electron mobility transistors (HEMTs) are common power devices and are widely used in high-frequency applications such as radio frequency and microwave.

[0003] In the existing GaN high electron mobility transistor structure, the substrate and the layers above it are usually made of different materials, so there is a lattice mismatch and thermal expansion coefficient mismatch, and crystal defects will be formed in the buffer layer during the wafer manufacturing process. When the transistor is turned off and the drain bias is high, electrons will be injected from the substrate and captured in the crystal defects in the buffer layer. On the other hand, under the conditions of high drain bias and high drain current during the hard switching conversion of the transistor, hot electrons will be injected from the two-dimensional electron gas (formed on the surface of the channel layer) and captured in the crystal defects in the buffer layer. The above-mentioned electrons captured in the buffer layer will consume part of the electrons in the two-dimensional electron gas, reducing the electron density of the two-dimensional electron gas, increasing the on-resistance of the transistor, and reducing the performance, stability and reliability of the transistor. Summary of the invention

[0004] In order to improve the above problems, the present invention provides a P-type doped semiconductor region below the drain metal layer. To achieve this purpose, the present invention provides the following technical solutions: One of the technical solutions provided by the present invention is: a power gallium nitride device, the device includes a substrate layer located at the bottom, a buffer layer located above the substrate layer, a channel layer located above the buffer layer, a barrier layer located above the channel layer, a P-type cap layer located above the barrier layer, a gate metal layer located above the P-type cap layer, a dielectric layer located above the barrier layer and the gate metal layer, a source metal layer and a drain metal layer located on both sides of the gate metal layer, and a P-type doped semiconductor region for injecting holes into the buffer layer to release electrons trapped in crystal defects in the buffer layer is provided below the drain metal layer. Under the premise of not affecting conduction, the P-type doped semiconductor region injects holes into the buffer layer 101 under the drain bias state, releases the electrons trapped in the crystal defects in the buffer layer, reduces the on-resistance of the device and improves its stability.

[0005] Furthermore, the drain metal layer is located above the P-type doped semiconductor region and the barrier layer, and the area of ​​the contact surface between the top surface of the P-type doped semiconductor region and the bottom surface of the drain metal layer is smaller than the area of ​​the bottom surface of the drain metal layer.

[0006] Furthermore, the P-type doped semiconductor region is in the shape of a long strip, or one or more regularly arranged squares, rectangles, semicircles, ellipses, or a combination of the above shapes.

[0007] Furthermore, the P-type doped semiconductor region extends inward, and at least a portion of the P-type doped semiconductor region extends out of the drain metal layer.

[0008] Furthermore, the cross-sectional shape of the portion of the P-type doped semiconductor region outside the drain metal layer is semicircular or semi-elliptical.

[0009] The present invention also provides a method for forming the above-mentioned power gallium nitride device, the method comprising the following steps: In the first step, a buffer layer is formed on the substrate layer, a channel layer is formed on the buffer layer, and then a barrier layer is formed on the channel layer; The second step is to perform photolithography on the barrier layer and part of the channel layer below the drain metal layer to be formed, and then perform ion implantation to form a P-type doped semiconductor region; The third step is to form a patterned P-type cap layer and a gate metal layer located thereon on the barrier layer; The fourth step is to form a patterned dielectric layer on the surface of the barrier layer and the gate metal layer; In the fifth step, a source metal layer and a drain metal layer are formed on both sides of the dielectric layer.

[0010] Furthermore, the source metal layer and the drain metal layer extend downward into the channel layer and form an ohmic contact with the channel layer, and the P-type doped semiconductor region is located in the channel layer.

[0011] Furthermore, the top surface of the P-type doped semiconductor region coincides with the bottom surface of the drain metal layer.

[0012] Furthermore, the P-type doped semiconductor region is in the shape of a long strip, or one or more regularly arranged squares, rectangles, semicircles, ellipses, or a combination of the above shapes.

[0013] Furthermore, the P-type doped semiconductor region extends inward, and at least a portion of the P-type doped semiconductor region extends outside the drain metal layer.

[0014] The present invention also provides a method for forming the above-mentioned power gallium nitride device, and the method comprises the following steps: In the first step, a buffer layer is formed on the substrate layer, a channel layer is formed on the buffer layer, and then a barrier layer is formed on the channel layer; The second step is to form a patterned P-type cap layer and a gate metal layer located thereon on the barrier layer; The third step is to form a patterned dielectric layer on the surface of the barrier layer and the gate metal layer; Step 4: ion implantation is performed below the drain metal layer to be formed to form a P-type doped semiconductor region, and the dielectric layer is used as a hard mask for ion implantation of the P-type doped semiconductor region; In the fifth step, a source metal layer and a drain metal layer are formed on both sides of the dielectric layer.

[0015] The above-mentioned P-type doped semiconductor region does not completely cover the contact surface between the drain metal layer and the barrier layer or the channel layer, and a portion of the contact surface between the drain metal layer and the barrier layer or the channel layer can still form an ohmic contact, allowing the device to be normally turned on.

[0016] Under the drain bias state, the P-type doped semiconductor region injects holes into the buffer layer, thereby releasing electrons trapped in crystal defects in the buffer layer, reducing the on-resistance of the device and improving the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic cross-sectional view of a device structure embodiment of the present invention; Figure 2 for Figure 1 A top view of the cross section at A-A'; Figure 3 is a cross-sectional schematic diagram of another device structure embodiment of the present invention; Figure 4 is a cross-sectional schematic diagram of another device structure embodiment of the present invention; Figure 5 for Figure 1 A top view of a cross section taken at AA' in various embodiments; Figure 6 is a cross-sectional schematic diagram of another device structure embodiment of the present invention; Figure 7 for Figure 6 Transverse cross-sectional views along line AA' in two embodiments; Figure 8-12 for Figure 1 A schematic cross-sectional view of an embodiment of a method for manufacturing a device structure; Figure 13-17 for Figure 4 A cross-sectional schematic diagram of an embodiment of a method for manufacturing a device structure. DETAILED DESCRIPTION

[0018] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "back", "vertical", and "horizontal" described in this document correspond to the relative positions of the reference diagrams, and are not limited to fixed directions in specific implementations. The devices in the accompanying drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the accompanying drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0019] Example 1 Figure 1 Schematic diagram of the cross section and top view of the first device structure embodiment of the present invention, Figure 2 for Figure 1 The top view of the cross section at A-A' in the figure, the structure includes: a substrate layer 100 at the bottom; a buffer layer 101 located above the substrate layer 100; A channel layer 102 located above the buffer layer 101; a barrier layer 103 located above the channel layer 102; A P-type cap layer 106 located above the barrier layer 103; The gate metal layer 207 is located above the P-type cap layer 106; The dielectric layer 208 is located above the barrier layer 103 and the gate metal layer 207; The source metal layer 209 is located on the left of the gate metal layer 207 and the drain metal layer 210 is located on the right of the gate metal layer 207 .

[0020] P-type doped semiconductor region 205 located below the drain metal layer 210; In the above structure, the barrier layer 103 forms a heterojunction with the channel layer 102 thereunder, and a two-dimensional electron gas 104 is formed on the surface of the channel layer 102 to form a current channel between the source metal layer 209 and the drain metal layer 210 when the device is turned on.

[0021] In the above structure, when the device is turned off, the P-type cap layer 106 depletes the two-dimensional electron gas 104 thereunder, forming an enhancement-mode device.

[0022] In the above structure, under the drain bias state, the P-type doped semiconductor region 205 injects holes into the buffer layer 101, thereby releasing electrons trapped in crystal defects in the buffer layer 101, reducing the on-resistance of the device and improving its stability.

[0023] In the above structure, the width of the P-type doped semiconductor region 205 is smaller than the width of the drain metal layer 210, and the top of the P-type doped semiconductor region 205 does not completely cover the bottom of the drain metal layer 210. Part of the bottom of the drain metal layer 210 can still form an ohmic contact with the barrier layer 103 located therebelow, so that the device can be normally turned on.

[0024] Example 2 A cross-sectional schematic diagram of a device structure embodiment of the present invention is shown in FIG. Figure 3 As shown, and Figure 1 The difference between the embodiments is that the source metal layer 209 and the drain metal layer 210 extend into the channel layer 102 and form an ohmic contact with the channel layer 102 so that the device can be normally turned on. The P-type doped semiconductor region 205 is located at a vertical position closer to the buffer layer 101 .

[0025] In the above structure, the source metal layer 209 and the drain metal layer 210 can extend into the channel layer 102 , which has a large process window and low process difficulty.

[0026] Example 3 A cross-sectional schematic diagram of a device structure embodiment of the present invention is shown in FIG. Figure 4 As shown, and Figure 3 The difference of the embodiment is that the width of the P-type doped semiconductor region 205 is similar to or the same as the width of the drain metal layer 210, and the top of the P-type doped semiconductor region 205 completely covers (overlaps) the bottom of the drain metal layer 210. The left side of the drain metal layer 210 forms an ohmic contact with the contact surface of the barrier layer or the channel layer, so that the device can be normally turned on.

[0027] In the above structure, the dielectric layer 208 can be used as a hard mask when ions are implanted into the P-type doped semiconductor region 205 , thereby ensuring that the P-type doped semiconductor region 205 can be accurately aligned with the drain metal layer 210 located thereon.

[0028] Example 4 A top view schematic diagram of a device structure embodiment of the present invention is shown in FIG. Figure 5 As shown, and Figure 2 The difference between the integrated long strip P-type doped semiconductor region 205 is that: Figure 5 The P-type doped semiconductor region 205 is composed of a series of independent squares or rectangles, semicircles or combinations of rectangles / squares and other shapes, among which it is worth noting that Figure 5 In the embodiment shown in b, the P-type doped semiconductor region 205 is not located near the edge, but is located in the middle of the bottom of the drain metal layer 210. Similarly, other embodiments may also adopt this method according to actual needs. Figure 5The total area of ​​the P-type doped semiconductor region 205 is shown as Figure 2 The total area shown is small, and the number of hot electrons injected into the buffer layer 101 under the drain bias state is small, and the drain leakage current is also small.

[0029] In the above structure, the required length, spacing and total area of ​​the P-type doped semiconductor region 205 can be obtained by adjusting the layout design of the P-type doped semiconductor region 205 , which is more flexible than the first embodiment in optimizing device performance.

[0030] Example 5 A cross-sectional and top view schematic diagram of a device structure embodiment of the present invention is shown in FIG. Figure 6 As shown, and Figure 5 The difference between the embodiments is that the P-type doped semiconductor region 205 extends laterally beyond the range of the drain metal layer 210 , and the P-type doped semiconductor region 205 is composed of different independent square or rectangular lamps, which does not affect the conduction of the device.

[0031] In the above structure, since the P-type doped semiconductor region 205 extends to the side, the area of ​​each independent P-type doped semiconductor region 205 is increased, so the number of P-type doped semiconductor regions 205 can be reduced, or the area of ​​the contact surface between the P-type doped semiconductor region 205 and the drain metal layer 210 can be reduced. Therefore, the contact area between the drain metal layer 210 and the barrier layer 103 can be increased while the total area of ​​the P-type doped semiconductor region 205 remains unchanged, thereby reducing the ohmic contact resistance formed by the drain metal layer 210 and the barrier layer 103.

[0032] Example 6 A top view schematic diagram of a device structure embodiment of the present invention is shown in FIG. Figure 7 As shown in B, and Figure 6 Example ( Figure 7 The difference is that Figure 7 The cross section of the portion of the P-type doped semiconductor region 205 shown in B extending beyond the range of the drain metal layer 210 is semicircular or semi-elliptical.

[0033] In the above structure, the sharp corner is removed at one end of the P-type doped semiconductor region 205 close to the gate metal layer 207, which reduces the peak electric field formed at this position when the drain is biased, thereby reducing the number of hot electrons generated at this position. According to the features of the device structure embodiments of the present invention described above, combined with the existing manufacturing process of GaN high electron mobility transistors, various methods for forming the device structure embodiments of the present invention can be obtained. Figure 2 Device structure formation method such as Figure 8-12 Shown: In the first step, a buffer layer 101 is formed on the substrate layer 100, a channel layer 102 is formed on the buffer layer 101, and a barrier layer 103 is formed on the channel layer 102. Figure 8 shown.

[0034] The material of the substrate layer 100 is usually silicon (Si), and may also be other suitable materials such as gallium nitride (GaN), silicon carbide (SiC), and sapphire.

[0035] The buffer layer 101 may include one material or a combination of multiple materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), etc. The one material or the combination of multiple materials may include doping elements such as carbon (C) and iron (Fe), which helps to reduce leakage current.

[0036] The material of the channel layer 102 is usually gallium nitride (GaN), and may also include a combination of one or more materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInGaN), and its band gap is smaller than the band gap of the material of the barrier layer 103 located thereon.

[0037] The material of the barrier layer 103 is usually aluminum gallium nitride (AlGaN), and may also include a combination of one or more materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInGaN), and its band gap is greater than the band gap of the material of the channel layer 102 located thereunder.

[0038] The channel layer 102 and the barrier layer 103 form a heterojunction, and a preliminary two-dimensional electron gas 904 is formed on the surface of the channel layer 102 below the heterojunction.

[0039] The above structure can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, epitaxial growth and other processes.

[0040] In the second step, the barrier layer 103 and part of the channel layer 102 located below the drain metal layer 210 to be formed are subjected to photolithography, ion implantation and other process steps to form a P-type doped semiconductor region 205, such as Fig. 9 The doping material of the P-type doped semiconductor region 205 includes magnesium (Mg) or other suitable P-type doping elements.

[0041] In the third step, a preliminary P-type cap layer is formed on the barrier layer 103, and a preliminary gate metal layer is formed on the preliminary P-type cap layer. Then, photolithography, dry etching, wet etching and other process steps are performed on the surface of the preliminary gate metal layer to form a patterned gate metal layer 207 and a P-type cap layer 106 located thereunder. Fig.10 As shown. The P-type cap layer 106 depletes the two-dimensional electron gas 104 located therebelow, forming an enhancement-mode device. Generally, the gate metal layer 207 forms a Schottky contact with the P-type cap layer 106 located therebelow.

[0042] In the above structure, the material of the P-type cap layer 106 is usually doped gallium nitride (GaN), and may also include a combination of one or more materials such as doped gallium nitride (GaN), doped aluminum nitride (AlN), doped indium nitride (InN), doped aluminum gallium nitride (AlGaN), doped indium gallium nitride (InGaN), doped aluminum indium nitride (AlInN), and doped aluminum indium gallium nitride (AlInGaN), and the doping material includes magnesium (Mg) or other suitable P-type doping elements. The above structure can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, epitaxial growth, and the like.

[0043] In the above structure, the gate metal layer 207 can be formed by evaporation, sputtering and other processes, and its constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other suitable materials.

[0044] In the fourth step, a preliminary dielectric layer is formed on the surface of the barrier layer 103 and the gate metal layer 207, and then photolithography, dry etching, wet etching and other process steps are performed on the preliminary dielectric layer to form a patterned dielectric layer 208, such as Fig.11 shown.

[0045] The material of the dielectric layer 208 is usually composed of oxide or nitride, such as aluminum oxide (Al2O3), silicon oxide (SiO2), aluminum nitride (AlN), silicon nitride (Si3N4), etc., and can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition and other processes.

[0046] In the fifth step, a source metal layer 209 is formed on the dielectric layer 208 (on the left and right sides of the gate metal layer 207) and a drain metal layer 210 is formed on the right side. Fig.12 Typically, the source metal layer 210 and the drain metal layer 211 form an ohmic contact with the barrier layer 103 thereunder.

[0047] The source metal layer 209 and the drain metal layer 210 may be formed by processes such as evaporation and sputtering, and their constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other appropriate materials.

[0048] Example 8 An exemplary Figure 4 The method for forming the device structure embodiment is as follows Figure 13-17 Shown: In the first step, a buffer layer 101 is formed on the substrate layer 100, a channel layer 102 is formed on the buffer layer 101, and a barrier layer 103 is formed on the channel layer 102. Fig.13 shown.

[0049] The channel layer 102 and the barrier layer 103 form a heterojunction, and a preliminary two-dimensional electron gas 904 is formed on the surface of the channel layer 102 below the heterojunction.

[0050] In the second step, a preliminary P-type cap layer is formed on the barrier layer 103, and a preliminary gate metal layer is formed on the preliminary P-type cap layer. Then, photolithography, dry etching, wet etching and other process steps are performed on the surface of the preliminary gate metal layer to form a patterned gate metal layer 207 and a P-type cap layer 106 located thereunder. Fig.14 As shown, the P-type cap layer 106 depletes the two-dimensional electron gas 104 located therebelow, forming an enhancement-mode device.

[0051] In the third step, a preliminary dielectric layer is formed on the surface of the barrier layer 103 and the gate metal layer 207, and then photolithography, dry etching, wet etching and other process steps are performed on the preliminary dielectric layer to form a patterned dielectric layer 208, such as Fig.15 shown.

[0052] In the fourth step, photolithography, ion implantation and other process steps are performed on the dielectric layer 208 to form a P-type doped semiconductor region 205 below the drain metal layer 210 to be formed. Fig.16 The dielectric layer 208 is used as a hard mask when ions are implanted into the P-type doped semiconductor region 205 .

[0053] In the fifth step, a drain metal layer 210 is formed on both sides of the dielectric layer 208 (the left and right sides of the gate metal layer 207), such as Fig.17 shown.

[0054] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.

Claims

1. A power gallium nitride device, comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a P-type cap layer above the barrier layer, a gate metal layer above the P-type cap layer, a dielectric layer above the barrier layer and the gate metal layer, and a source metal layer and a drain metal layer on both sides of the gate metal layer, characterized in that: A P-type doped semiconductor region is also provided below the drain metal layer for injecting holes into the buffer layer to release electrons captured in crystal defects in the buffer layer.

2. A power gallium nitride device according to claim 1, characterized in that: The drain metal layer is located above the P-type doped semiconductor region and the barrier layer, and the area of ​​the contact surface between the top surface of the P-type doped semiconductor region and the bottom surface of the drain metal layer is smaller than the area of ​​the bottom surface of the drain metal layer.

3. A power gallium nitride device as claimed in claim 2, characterized in that: The P-type doped semiconductor region is in the shape of a long strip, or one or more regularly arranged squares, rectangles, semicircles, ellipses, or a combination of the above shapes.

4. A power gallium nitride device as claimed in claim 3, characterized in that: The P-type doped semiconductor region extends inwardly, and at least a portion of the P-type doped semiconductor region extends out of the drain metal layer.

5. A power gallium nitride device as claimed in claim 4, characterized in that: The cross-sectional shape of the portion of the P-type doped semiconductor region outside the drain metal layer is semicircular or semi-elliptical.

6. A method for forming a power gallium nitride device according to any one of claims 1 to 5, characterized in that: The forming method comprises the following steps: In the first step, a buffer layer is formed on the substrate layer, a channel layer is formed on the buffer layer, and then a barrier layer is formed on the channel layer; The second step is to perform photolithography on the barrier layer and part of the channel layer below the drain metal layer to be formed, and then perform ion implantation to form a P-type doped semiconductor region; The third step is to form a patterned P-type cap layer and a gate metal layer located thereon on the barrier layer; The fourth step is to form a patterned dielectric layer on the surface of the barrier layer and the gate metal layer; In the fifth step, a source metal layer and a drain metal layer are formed on both sides of the dielectric layer.

7. A power gallium nitride device according to claim 1, characterized in that: The source metal layer and the drain metal layer extend downward into the channel layer and form an ohmic contact with the channel layer. The P-type doped semiconductor region is located in the channel layer.

8. A power gallium nitride device as claimed in claim 7, characterized in that: The top surface of the P-type doped semiconductor region coincides with the bottom surface of the drain metal layer.

9. A power gallium nitride device as claimed in claim 7, characterized in that: The P-type doped semiconductor region is in the shape of a long strip, or one or more regularly arranged squares, rectangles, semicircles, ellipses, or a combination of the above shapes.

10. A power gallium nitride device according to claim 9, characterized in that: The P-type doped semiconductor region extends inwardly, and at least a portion of the P-type doped semiconductor region extends outside the drain metal layer.

11. A method for forming a power gallium nitride device according to any one of claims 7 to 10, characterized in that: The forming method comprises the following steps: In the first step, a buffer layer is formed on the substrate layer, a channel layer is formed on the buffer layer, and then a barrier layer is formed on the channel layer; The second step is to form a patterned P-type cap layer and a gate metal layer located thereon on the barrier layer; The third step is to form a patterned dielectric layer on the surface of the barrier layer and the gate metal layer; Step 4: ion implantation is performed below the drain metal layer to be formed to form a P-type doped semiconductor region, and the dielectric layer is used as a hard mask for ion implantation of the P-type doped semiconductor region; In the fifth step, a source metal layer and a drain metal layer are formed on both sides of the dielectric layer.

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