Super-junction MOSFET device and preparation method thereof

Abstract

The invention discloses a super-junction MOSFET device and a preparation method thereof, and belongs to the technical field of semiconductors, and the super-junction MOSFET device comprises a first conduction type substrate and a first conduction type epitaxial layer located on the first conduction type substrate; a cellular region and a terminal region of the device are arranged in the first conductive type epitaxial layer; a plurality of second conductive type columns are longitudinally distributed in a cellular region and a terminal region in the first conductive type epitaxial layer; wherein the plurality of second conductive type columns distributed in the terminal area comprise a plurality of size types, and the second conductive type columns of different size types are alternately arranged. The structural design relieves the strength of a terminal electric field of the device in a reverse withstand voltage state, so that the electric field strength of a terminal region is lower than that of a cellular region, breakdown occurs in the cellular region, the situation that holes are injected into a silicon and silicon dioxide interface, and consequently charges on an oxide layer interface are increased is avoided, the reliability of the device is improved, and the performance of the device is improved. And meanwhile, the avalanche breakdown capability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a super junction MOSFET device and a preparation method thereof. Background Art

[0002] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled power semiconductor device with significant advantages such as fast switching speed, good high-frequency characteristics, good thermal stability, low noise, simple driving circuit, low driving power, wide safe operating area, and no secondary breakdown problem. It plays a vital role in modern electronic devices.

[0003] Super junction MOSFET is a new product with excellent performance and wide application fields. Its main feature is the use of alternating PN columns to replace the drift region in ordinary MOSFET, thereby introducing a two-dimensional electric field in the drift region. When the various parameters of the PN column are reasonably designed, the modulation effect of the lateral electric field is utilized. Compared with traditional MOSFET, while maintaining the same withstand voltage level, the drift region doping concentration is increased by 1 to 2 orders of magnitude, so it has excellent on-resistance.

[0004] The terminal of super junction MOSFET is more complicated than that of traditional MOSFET. In the terminal area, alternate PN columns are needed to extend the depletion region and improve the voltage resistance of the device as much as possible. The terminal structure of existing super junction MOSFET is arranged alternately with PN columns at equal intervals to improve the voltage resistance.

[0005] However, this structural design often causes the breakdown position of the device to occur at the terminal. The process of avalanche breakdown current flowing from the terminal position through the cell region will cause holes to be injected into the interface of silicon and silicon dioxide, causing the interface charge of the oxide layer to increase, thus affecting the reliability of the device. In addition, the breakdown position occurring at the terminal will also reduce the device's ability to resist avalanche current. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a super junction MOSFET device and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0007] In the first aspect, the present invention proposes a super junction MOSFET device, comprising: a first conductive type substrate and a first conductive type epitaxial layer located on the first conductive type substrate; a cell region and a terminal region of the device are provided in the first conductive type epitaxial layer; a plurality of second conductive type columns are longitudinally distributed in the cell region and the terminal region in the first conductive type epitaxial layer; wherein the plurality of second conductive type columns distributed in the terminal region include a plurality of size types, and the second conductive type columns of different size types are alternately arranged.

[0008] In a second aspect, the present invention provides a method for preparing a super junction MOSFET device, comprising:

[0009] Step 1: Select a first conductive type substrate, and epitaxially grow a portion of a first conductive type epitaxial layer of a preset thickness on the first conductive type substrate; the first conductive type epitaxial layer is divided into a cell region and a terminal region of the device;

[0010] Step 2: Performing a general implantation of first conductive type donor ions at an oblique angle on the top of the first conductive type epitaxial layer; then performing a second conductive type ion implantation in the cell region and the terminal region of the first conductive type epitaxial layer using a mask to form a plurality of implantation regions; wherein the portion corresponding to the terminal region on the mask adopts a layout in which windows of various sizes are alternately arranged, so that the formed plurality of implantation regions are also arranged alternately;

[0011] Step 3: Repeat the operations of step 1 and step 2 to form a complete first conductive type epitaxial layer. At the same time, the injection regions at corresponding positions in different levels of the first conductive type epitaxial layers are interconnected in the vertical direction to form a plurality of second conductive type columns distributed longitudinally in the cell area and the terminal area; and the second conductive type columns in the terminal area are arranged alternately in different sizes and types.

[0012] Beneficial effects of the present invention:

[0013] The present invention proposes a super junction MOSFET device, comprising: a first conductive type substrate and a first conductive type epitaxial layer located on the first conductive type substrate; a cell region and a terminal region of the device are provided in the first conductive type epitaxial layer; a plurality of second conductive type columns are longitudinally distributed in the cell region and the terminal region in the first conductive type epitaxial layer; wherein the plurality of second conductive type columns distributed in the terminal region include a plurality of size types, and the second conductive type columns of different size types are arranged alternately. The structural design alleviates the strength of the terminal electric field of the device under the reverse withstand voltage state by forming second conductive type columns of different sizes arranged alternately in the terminal region of the device, so that the electric field strength in the terminal region is lower than that in the cell region, so that the breakdown occurs in the cell region, that is, whether in the charge balance state or the non-balanced state, the avalanche current flows away from the cell region, avoiding the injection of holes into the interface of silicon and silicon dioxide, causing the increase of the interface charge of the oxide layer, improving the reliability of the device, and at the same time improving the avalanche breakdown capability of the device.

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic structural diagram of a super junction MOSFET device provided by an embodiment of the present invention;

[0016] Figure 2 This is the electric field distribution diagram of the traditional equally spaced terminals under reverse withstand voltage state;

[0017] Figure 3 is an electric field distribution diagram of the terminal structure provided by an embodiment of the present invention in a reverse withstand voltage state;

[0018] Figure 4 This is the avalanche current distribution diagram of the traditional equally spaced terminals under reverse withstand voltage state;

[0019] Figure 5 is an avalanche current distribution diagram of the terminal structure provided by an embodiment of the present invention under a reverse withstand voltage state;

[0020] Figure 6 It is a schematic flow chart of a method for preparing a super junction MOSFET device provided by an embodiment of the present invention;

[0021] Figures 7a-7j It is a schematic diagram of the process for preparing a super junction MOSFET device provided in an embodiment of the present invention.

[0022] Description of reference numerals:

[0023] 01-first conductivity type substrate, 02-first conductivity type epitaxial layer, 03-second conductivity type column, 04-second conductivity type multi-ring region, 05-second conductivity type single ring region, 06-field oxide layer, 07-JFET region, 08-gate oxide layer, 09-polysilicon layer, 10-second conductivity type body region, 11-first conductivity type source region, 12-interlayer insulating medium, 13-source metal, 14-drain metal. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] A first aspect of the present invention provides a super junction MOSFET device. Figure 1 , Figure 1 It is a structural schematic diagram of a super junction MOSFET device provided by an embodiment of the present invention, including: a first conductive type substrate 01 and a first conductive type epitaxial layer 02 located on the first conductive type substrate 01; a cell region and a terminal region of the device are provided in the first conductive type epitaxial layer 02; a plurality of second conductive type columns 03 are longitudinally distributed in the cell region and the terminal region in the first conductive type epitaxial layer 02; wherein the plurality of second conductive type columns 03 distributed in the terminal region include a plurality of size types, and the second conductive type columns 03 of different size types are alternately arranged.

[0026] Specifically, in this embodiment, the first conductivity type can be selected as N type, and the second conductivity type is P type, so the second conductivity type column 03 can be called a P column. In this embodiment, the first conductivity type substrate 01 can be selected as an N+ type silicon substrate material, and the first conductivity type epitaxial layer 02 can be selected as an N-type silicon carbide epitaxial material.

[0027] Optionally, as an implementation method, the present embodiment designs two size types for a plurality of second conductive type columns 03 distributed in the terminal area, namely, small-sized second conductive type columns and large-sized second conductive type columns, and the small-sized second conductive type columns and the large-sized second conductive type columns are arranged alternately. The sum of the widths of the small-sized second conductive type columns and the large-sized second conductive type columns is equal to the width of the second conductive type columns distributed in the cell area.

[0028] Optionally, as an implementation, in this embodiment, the width of the large-sized second conductive type column can be 1.8-2.8 μm; the width of the small-sized second conductive type column can be three-fifths of the width of the large-sized second conductive type column. The spacing distance between the small-sized second conductive type column and the large-sized second conductive type column is 3-3.9 μm.

[0029] like Figure 1 As shown, it can be seen that the present embodiment adopts a small CD and a large CD parallel arrangement for the CD (Critical Dimension) of the terminal P column to form a terminal structure, and the sum of the two CDs of the terminal P column is equal to the CD of the P column in the cell area. When the device is in a certain humidity environment and a reverse withstand voltage is applied, the avalanche current occurs in the cell area, thereby solving the problem of hole injection into the silicon and silicon dioxide interface caused by the high electric field at the terminal, causing the interface charge of the oxide layer to increase, so that the charge balance of the terminal area can be stabilized and the reliability can be guaranteed. In addition, this design not only better optimizes the potential distribution of the device terminal structure, and can increase the withstand voltage by 5% compared with the traditional terminal design, but also can improve the device's ability to resist avalanche breakdown.

[0030] For further information, please see Figure 1 In the terminal region, a second conductive type multi-ring region 04 and a second conductive type single-ring region 05 are further provided in the top layer of the first conductive type epitaxial layer 02, the second conductive type multi-ring region 04 is located in the middle region of the terminal region, the second conductive type single-ring region 05 is located on the left side immediately adjacent to the second conductive type multi-ring region 04, and the upper surfaces of the two are in the same plane; a second conductive type body region 10 is further provided in the second conductive type single-ring region 05; a field oxide layer 06 is further provided on the upper surface of the first conductive type epitaxial layer 02, and the field oxide layer 06 covers the upper surface of the second conductive type multi-ring region 04 and the right area of ​​the terminal region;

[0031] In the cell region, a JFET region 07 is further provided in the top layer of the first conductive type epitaxial layer 02; the JFET region 07 is adjacent to the second conductive type single ring region 05, and the upper surfaces of the two are in the same plane; a gate oxide layer 08 is further provided on the upper surface of the first conductive type epitaxial layer 02, and the gate oxide layer 08 covers a portion of the JFET region 07; a polysilicon layer 09 is further provided above the gate oxide layer 08 to form a gate; a first conductive type source region 11 is provided in the JFET region 07;

[0032] An interlayer insulating medium 12 is also provided on the upper surface of the first conductive type epitaxial layer 02 ; a metal contact hole is opened in the area of ​​the interlayer insulating medium 12 corresponding to the first conductive type source region 11 , and a source metal 13 is provided therein; a drain metal 14 is provided under the first conductive type substrate 01 .

[0033] The present invention forms P columns of large and small sizes arranged alternately in the terminal region of the device, thereby alleviating the intensity of the terminal electric field of the device under the reverse withstand voltage state, making the electric field intensity of the terminal region lower than that of the cell region, so that the breakdown occurs in the cell region, that is, no matter in the charge balance state or the non-balanced state, the avalanche current flows away from the cell region, avoiding the situation where holes are injected into the interface of silicon and silicon dioxide, causing the increase of the interface charge of the oxide layer, thereby improving the reliability of the device and enhancing the avalanche breakdown capability of the device.

[0034] In order to further illustrate the advantages of the terminal structure of the present invention, the electric field distribution and avalanche current distribution of the terminal structure of the present invention and the traditional equidistant terminal structure under the reverse withstand voltage state are compared through simulation experiments.

[0035] See also Figure 2 and Figure 3 , Figure 2 This is the electric field distribution diagram of the traditional equally spaced terminals under reverse withstand voltage. Figure 3 : is an electric field distribution diagram of the terminal structure provided by the embodiment of the present invention in the reverse withstand voltage state. Figure 2 It can be seen that the PN columns of the traditional terminal are arranged alternately. When the device is in the reverse withstand voltage state, the electric field strength of the terminal is prone to uneven distribution, resulting in the terminal electric field strength being higher than the cell area. After the terminal breaks down prematurely, holes are injected into the interface of silicon and silicon dioxide, causing the interface charge of the oxide layer to increase, breaking the terminal charge balance and eventually causing device damage. Figure 3 It can be seen that the terminal structure of the present invention has an electric field distribution diagram under the reverse withstand voltage state. When the device is under the reverse withstand voltage state, the structure introduces small CD P columns to form a structure in which small CD and large CD P columns are arranged alternately, which alleviates the terminal electric field strength and makes the terminal electric field strength lower than the cell area, and the breakdown occurs in the cell. This avoids the injection of holes into the interface between silicon and silicon dioxide, causing the interface charge of the oxide layer to increase and breaking the terminal charge balance.

[0036] See also Figure 4 and Figure 5 , Figure 4 This is the avalanche current distribution diagram of traditional equally spaced terminals under reverse withstand voltage state. Figure 5 : is a diagram of avalanche current distribution of the terminal structure provided by an embodiment of the present invention under reverse withstand voltage state. Figure 4 and Figure 5 It can be seen that the breakdown position of the conventional terminal structure is likely to occur at the terminal at a concentration outside the charge balance point, and the avalanche current flows from the terminal to the cell region. However, the breakdown position of the terminal structure of the present invention occurs in the cell region at a concentration outside the charge balance point, indicating that the junction structure has a good ability to resist avalanche breakdown.

[0037] In summary, the structural design adopted by the present invention can better optimize the potential distribution of the device terminal structure, effectively reduce the peak electric field strength, and improve the withstand voltage performance of the device terminal; at the same time, this design can better solve the problem that the high electric field at the terminal causes holes to be injected into the silicon and silicon dioxide interface, causing the interface charge of the oxide layer to increase, breaking the charge balance in the terminal area, and the withstand voltage degradation of the device. The breakdown position of the terminal structure occurs in the cell area, which ensures the device's anti-avalanche breakdown capability.

[0038] It should be noted that, for the materials, thicknesses, implanted ions, etc. of each layer involved in this embodiment, reference may be made to the existing related technologies, and no specific limitation is made in this embodiment.

[0039] It is understandable that the terminal structure designed in the present invention can be applied to not only MOSFET devices but also other semiconductor devices such as IGBT (Insulate-Gate Bipolar Transistor).

[0040] Based on the same inventive concept, the second aspect of the present invention also provides a method for preparing a super junction MOSFET device. Figure 6 The process diagram shown and Figures 7a-7j The process schematic diagram shown is a detailed introduction to the preparation method of the present invention.

[0041] Step 1: Select a first conductive type substrate 01, and epitaxially grow a first conductive type epitaxial layer 02 of a preset thickness on the first conductive type substrate 01; the first conductive type epitaxial layer 02 is divided into a cell region and a terminal region of the device.

[0042] Specifically, N+ type silicon is selected as the substrate, and a thin N- type epitaxial layer is epitaxially grown thereon to obtain Figure 7a The device structure shown.

[0043] Step 2: Perform a general implantation of first conductivity type donor ions at an oblique angle on the top of the first conductivity type epitaxial layer 02; then perform a second conductivity type ion implantation in the cell region and terminal region of the first conductivity type epitaxial layer 02 using a mask to form a plurality of implantation regions.

[0044] The portion corresponding to the terminal area on the mask plate adopts a layout in which windows of various sizes are arranged alternately, so that the formed injection areas are also arranged alternately.

[0045] Specifically, firstly, the N-type epitaxial layer is implanted with impurities at an oblique angle of 7 degrees, the implantation dose is 2.4e12-2.8e12, and the implantation energy is 100kev-200kev.

[0046] Next, a mask with a terminal area of ​​small CD and large CD arranged in parallel is used to etch out an ion implantation window through photolithography and etching processes, and a 0-degree angle P-type ion implantation is performed, with an implantation dose of 6.0e12 to 7.4e12 and an implantation energy of 100kev to 200kev, to form a number of elliptical implantation areas. It can be understood that the several elliptical implantation areas are also distributed in alternating sizes, such as Figure 7b shown.

[0047] Step 3: Repeat the operations of step 1 and step 2 to form a complete first conductive type epitaxial layer 02. At the same time, the injection regions at corresponding positions in different levels of the first conductive type epitaxial layer 02 are interconnected in the vertical direction to form a plurality of second conductive type columns 03 distributed longitudinally in the cell area and the terminal area; and the second conductive type columns 03 in the terminal area are arranged alternately in different sizes and types.

[0048] Generally speaking, the operation of step 1 and step 2 can be repeated 7 times to form Figure 7c The device structure shown. It can be understood that Figure 7c The injection regions in adjacent layers shown in the figure have a certain distance from each other in the vertical direction, and after subsequent high-temperature annealing, they will be interconnected in the vertical direction to form P columns.

[0049] Furthermore, to prepare a super junction MOSFET device, the following steps are also included:

[0050] Step 4: In the top layer of the first conductive type epitaxial layer 02, the second conductive type acceptor ions are selectively implanted using a mask layer, and a high temperature annealing process is performed to form a second conductive type multi-ring region 04 in the middle area of ​​the terminal region.

[0051] Specifically, on the top of the N-type epitaxial layer, a window for acceptor ion implantation is etched out by photolithography and etching using a mask layer to form a P-type multi-ring region, i.e., the second conductive type multi-ring region 04, with an implantation dose of 1e12 to 3e12 and an implantation energy of 100kev to 200kev, followed by high temperature annealing to obtain the following: Figure 7d The device structure shown.

[0052] It can be seen that after high-temperature annealing, the larger injection regions in the cell region and the terminal region are interconnected in the vertical direction.

[0053] Step 5: In the top layer of the first conductive type epitaxial layer 02 , the second conductive type acceptor ions are selectively implanted using a mask layer to form a second conductive type single ring region 05 immediately to the left of the second conductive type multi-ring region 04 .

[0054] Specifically, on the top of the N-type epitaxial layer, a window for acceptor ion implantation is etched out by photolithography and etching using a mask layer to form a P+ type single ring region, that is, the second conductive type single ring region 05; wherein the implantation dose is 1e14 to 3e14, and the implantation energy is 500kev to 100kev, and the following is obtained: Figure 7e The device structure shown.

[0055] Step 6: forming a field oxide layer 06 on the upper surface of the first conductive type epitaxial layer 02 , and then implanting first conductive type impurities into the surface layer of the cell region of the first conductive type epitaxial layer 02 to form a JFET region 07 .

[0056] Specifically, first, a field oxide layer with a thickness of 50nm to 120nm is generated by thermal oxidation in a high-temperature furnace tube, and the required field oxide layer 06 is selectively etched using a mask layer. Then, N-type impurity general implantation is performed to form a JFET region 07; wherein the implantation dose is 1e12 to 3e12, and the implantation energy is 100kev to 250ke, and the following is obtained: Figure 7f The device structure shown.

[0057] Step 7: Generate a gate oxide layer 08 on the surface of the cell region of the first conductive type epitaxial layer 02 by thermal oxidation in a high temperature furnace tube, and deposit a first conductive type doped polysilicon layer 09, and selectively etch away part of the polysilicon layer 09 and the gate oxide layer 08 using a mask layer to form a gate.

[0058] Specifically, firstly, a gate oxide layer 08 is formed by thermal oxidation in a high temperature furnace tube; then, an N-type doped polysilicon layer 09 is deposited thereon, and the N-type polysilicon layer 09 and the gate oxide layer 08 are selectively etched away by a mask layer to form a gate, and the gate oxide layer 08 is obtained as shown in FIG. Figure 7g The device structure shown.

[0059] Step 8: Use a self-aligned process to implant second conductivity type acceptor ions into the second conductivity type single ring region 05 to form a second conductivity type body region 10 .

[0060] Specifically, acceptor ions are implanted by a self-aligned process, and then high-temperature annealing is performed to form a P-type body region, that is, a second conductive type body region 10, as shown in FIG. Figure 7h The device structure shown.

[0061] Step 9: In the top layer of the first conductive type epitaxial layer 02 , first conductive type donor ions are selectively implanted using a mask layer to form a first conductive type source region 11 in the cell region.

[0062] Specifically, a window for acceptor ion implantation is etched out by photolithography and etching using a mask layer to form an N+ type source region 11, and the following is obtained: Figure 7i The device structure shown.

[0063] Step 10: deposit an interlayer insulating dielectric 12 on the upper surface of the first conductive type epitaxial layer 02 , and deposit metal to form a source metal 13 after selective etching using a mask layer; and deposit metal to form a drain metal 14 on the back side of the first conductive type substrate 01 .

[0064] Specifically, an interlayer insulating dielectric 12 is deposited on the upper surface of the N-type epitaxial layer, a metal contact hole is etched by photolithography using a mask layer, and a source metal 13 is deposited; a metal is deposited on the back surface to form a drain metal 14, and the following is obtained: Figure 7j The device structure shown.

[0065] At this point, the preparation of the super junction MOSFET device has been completed.

[0066] It should be noted that the specific implementation processes of the epitaxial process, ion implantation process, photolithography and etching process, self-alignment process, etc. involved in this embodiment can also be implemented by referring to the existing related technologies, and this embodiment will not be described in detail here.

[0067] The preparation method provided in the second aspect of the present invention can be used to prepare the super junction MOSFET device provided in the first aspect, and therefore has similar beneficial effects as the embodiment of the first aspect. For technical details not disclosed in the preparation method embodiment of the present invention, reference can be made to the description of the device embodiment for understanding.

[0068] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0069] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0070] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0071] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0072] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A super junction MOSFET device, characterized in that: include: A first conductive type substrate (01) and a first conductive type epitaxial layer (02) located on the first conductive type substrate (01); a cell region and a terminal region of a device are provided in the first conductive type epitaxial layer (02); a plurality of second conductive type columns (03) are longitudinally distributed in the cell region and the terminal region in the first conductive type epitaxial layer (02); wherein the plurality of second conductive type columns (03) distributed in the terminal region include a plurality of size types, and the second conductive type columns (03) of different size types are alternately arranged.

2. A super junction MOSFET device according to claim 1, characterized in that: The plurality of second conductive type columns (03) distributed in the terminal area include two size types, namely small size second conductive type columns and large size second conductive type columns, and the small size second conductive type columns and the large size second conductive type columns are arranged alternately.

3. A super junction MOSFET device according to claim 2, characterized in that: The sum of the widths of the small-sized second conductive type pillars and the large-sized second conductive type pillars is equal to the width of the second conductive type pillars distributed in the cell region.

4. A super junction MOSFET device according to claim 2, characterized in that: The width of the large-sized second conductive type column is 1.8 μm to 2.8 μm; the width of the small-sized second conductive type column is three fifths of the width of the large-sized second conductive type column.

5. A super junction MOSFET device according to claim 2, characterized in that: The spacing distance between the small-sized second conductive type pillar and the large-sized second conductive type pillar is 3 μm to 3.9 μm.

6. A super junction MOSFET device according to any one of claims 1 to 5, characterized in that: In the terminal region, a second conductive type multi-ring region (04) and a second conductive type single-ring region (05) are also provided in the top layer of the first conductive type epitaxial layer (02), the second conductive type multi-ring region (04) is located in the middle region of the terminal region, the second conductive type single-ring region (05) is located on the left side of the second conductive type multi-ring region (04), and the upper surfaces of the two are in the same plane; a second conductive type body region (10) is also provided in the second conductive type single-ring region (05); a field oxide layer (06) is also provided on the upper surface of the first conductive type epitaxial layer (02), and the field oxide layer (06) covers the upper surface of the second conductive type multi-ring region (04) and the right side region of the terminal region; In the cell region, a JFET region (07) is also provided in the top layer of the first conductive type epitaxial layer (02); the JFET region (07) is adjacent to the second conductive type single ring region (05), and the upper surfaces of the two are in the same plane; a gate oxide layer (08) is also provided on the upper surface of the first conductive type epitaxial layer (02), and the gate oxide layer (08) covers a portion of the JFET region (07); a polysilicon layer (09) is also provided above the gate oxide layer (08) to form a gate; a first conductive type source region (11) is provided in the JFET region (07); An interlayer insulating medium (12) is also provided on the upper surface of the first conductive type epitaxial layer (02); a metal contact hole is opened in a region on the interlayer insulating medium (12) corresponding to the first conductive type source region (11), and a source metal (13) is provided therein; and a drain metal (14) is provided below the first conductive type substrate (01).

7. A method for preparing a super junction MOSFET device, characterized in that: include: Step 1: selecting a first conductive type substrate, and epitaxially growing a first conductive type epitaxial layer of a predetermined thickness on the first conductive type substrate; The first conductive type epitaxial layer is divided into a cell region and a terminal region of the device; Step 2: on the top of the first conductive type epitaxial layer, perform a general implantation of first conductive type donor ions at an oblique angle; then perform a second conductive type ion implantation in the cell region and the terminal region of the first conductive type epitaxial layer using a mask to form a plurality of implantation regions; wherein the portion corresponding to the terminal region on the mask adopts a layout in which windows of various sizes are alternately arranged, so that the formed plurality of implantation regions are also arranged alternately; Step 3: Repeat the operations of step 1 and step 2 to form a complete first conductive type epitaxial layer. At the same time, the injection regions at corresponding positions in different levels of the first conductive type epitaxial layers are interconnected in the vertical direction to form a plurality of second conductive type columns distributed longitudinally in the cell area and the terminal area; and the second conductive type columns in the terminal area are arranged alternately in different sizes and types.

8. The method for preparing a super junction MOSFET device according to claim 7, characterized in that: In step 2, the first conductivity type donor ion general injection using an oblique angle has an injection dose of 2.4e12-2.8e12 and an injection energy of 100kev-200kev; The second conductive type ion implantation is performed in the cell region and the terminal region of the first conductive type epitaxial layer using a mask, the implantation dosage is 6.0e12-7.4e12, and the implantation energy is 100kev-200kev.

9. A method for preparing a super junction MOSFET device according to any one of claims 7 to 8, characterized in that: After step 3, it also includes: Step 4: selectively implanting the second conductivity type acceptor ions into the top layer of the first conductivity type epitaxial layer using a mask layer, and performing high temperature annealing to form a second conductivity type multi-ring region in the middle region of the terminal region; Step 5: selectively implanting the second conductivity type acceptor ions into the top layer of the first conductivity type epitaxial layer using a mask layer to form a second conductivity type single ring region immediately to the left of the second conductivity type multi-ring region; Step 6: forming a field oxide layer on the upper surface of the first conductive type epitaxial layer, and then implanting the first conductive type impurities into the surface layer of the cell region of the first conductive type epitaxial layer to form a JFET region; Step 7: generating a gate oxide layer on the surface layer of the cell region of the first conductive type epitaxial layer by thermal oxidation in a high temperature furnace tube, depositing a first conductive type doped polysilicon layer, and selectively etching away a portion of the polysilicon layer and the gate oxide layer by using a mask layer to form a gate; Step 8: implanting second conductivity type acceptor ions into the second conductivity type single ring region using a self-aligned process to form a second conductivity type body region; Step 9: selectively implanting first conductivity type donor ions into the top layer of the first conductivity type epitaxial layer using a mask layer to form a first conductivity type source region in the cell region; Step 10: depositing an interlayer insulating dielectric on the upper surface of the first conductive type epitaxial layer, depositing metal to form source metal after selective etching using the mask layer; and depositing metal on the back side of the first conductive type substrate to form drain metal.

10. The method for preparing a super junction MOSFET device according to claim 9, characterized in that: The ion implantation in step 4 has an implantation dose of 1e12 to 3e12 and an implantation energy of 100kev to 200kev; The ion implantation in step 5 has an implantation dose of 1e14 to 3e14 and an implantation energy of 500kev to 100kev; The ion implantation in step 6 has an implantation dose of 1e12 to 3e12 and an implantation energy of 100kev to 250ke; the thickness of the formed field oxide layer is 50nm to 120nm.

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