Metal oxide semiconductor field effect transistor and preparation method thereof

Abstract

The invention discloses a metal oxide semiconductor field effect transistor and a preparation method thereof. The metal oxide semiconductor field effect transistor comprises a drain metal layer, a substrate, a first epitaxial layer, a second epitaxial layer, a dielectric layer and a source metal layer which are stacked in sequence, the upper surface of the first epitaxial layer comprises first buried regions which are arranged at intervals; the second epitaxial layer comprises an ion implantation layer, a groove region and a second buried region which are arranged at intervals; the trench region comprises a first gate oxide layer, a first gate region, a second gate oxide layer and a second gate region; the first gate region, the second gate oxide layer and the second gate region form a split gate structure; the dielectric layer comprises a target opening, and the target opening is filled with contact metal. According to the embodiment of the invention, the dynamic loss of the metal oxide semiconductor field effect transistor can be reduced, and the reliability of the metal oxide semiconductor field effect transistor is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a metal oxide semiconductor field effect transistor and a preparation method thereof. Background Art

[0002] Silicon Carbide (SiC) power trench gate metal oxide semiconductor field effect transistor (U-Groove MOSFET, UMOSFET) has a smaller on-resistance and a larger channel density due to its high-density cell size and high mobility on the non-polar surface, and has broad application prospects.

[0003] At present, in the field of power electronics, such as photovoltaic inverter, motor drive and direct current (DC)-to-DC conversion, it is necessary to parasitic PN body diode inside SiC UMOSFET so that the PN body diode can act as a reverse recovery diode to form a complete current path.

[0004] However, the parasitic PN body diode inside the SiC UMOSFET currently produces high dynamic losses, and when the SiC UMOSFET is in the reverse blocking state, there will be two-dimensional electric field concentration at the corners of the trench in the SiC UMOSFET, resulting in a high electric field intensity at the bottom of the trench, which in turn reduces the reliability of the device. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a metal oxide semiconductor field effect transistor and a method for preparing the same, which can solve the problems of high dynamic loss and low reliability of silicon carbide power trench gate metal oxide semiconductor field effect transistor with internal parasitic body diode in the related art.

[0006] In a first aspect, an embodiment of the present application provides a metal oxide semiconductor field effect transistor, the metal oxide semiconductor field effect transistor comprising a drain metal layer, a substrate, a first epitaxial layer, a second epitaxial layer, a dielectric layer and a source metal layer stacked in sequence;

[0007] Wherein, the upper surface of the first epitaxial layer includes first buried regions arranged at intervals;

[0008] The second epitaxial layer comprises an ion implantation layer, a groove region and a second buried region which are arranged at intervals; the ion implantation layer extends from the upper surface of the second epitaxial layer to the inside of the second epitaxial layer along the thickness direction of the metal oxide semiconductor field effect transistor; the groove region penetrates the ion implantation layer along the longitudinal center line of the ion implantation layer and extends to the second buried region;

[0009] The trench region includes a first gate oxide layer, a first gate region, a second gate oxide layer and a second gate region; the first gate oxide layer is stacked on the inner wall of the trench region, and the first gate region, the second gate oxide layer and the second gate region are stacked in sequence on the upper surface of the first gate oxide layer along the direction from the first epitaxial layer to the second epitaxial layer to form a split gate structure;

[0010] The dielectric layer includes a target opening, and the target opening is filled with a contact metal; the contact metal is used to connect the second epitaxial layer and the source metal layer.

[0011] Optionally, the width of the first gate region is less than or equal to the width of the second gate region, and the width of the first gate region and / or the second gate region is 0.5 μm to 1 μm.

[0012] Optionally, a thickness of the first gate region and / or the second gate region is 0.5 μm to 1.5 μm.

[0013] Optionally, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0014] Optionally, the second gate oxide layer has a thickness of 0.05 μm to 0.12 μm.

[0015] Optionally, a minimum value of an angle between a sidewall of the trench region and a lower surface of the second epitaxial layer is 85° to 89°.

[0016] Optionally, the depth of the groove region is 2 μm to 3 μm, and the width of the groove region is 0.5 μm to 1.2 μm.

[0017] Optionally, the target opening includes a first opening corresponding to the ion implantation layer and a second opening corresponding to a spacing region between the ion implantation layers;

[0018] The contact metal includes an ohmic contact metal and a Schottky contact metal, the first opening is filled with the ohmic contact metal, and the second opening is filled with the Schottky contact metal.

[0019] Optionally, the thickness of the ohmic contact metal and / or the Schottky contact metal is less than or equal to the thickness of the dielectric layer.

[0020] Optionally, the thickness of the ohmic contact metal is 60 nm to 200 nm, and the width of the ohmic contact metal is 0.2 μm to 0.5 μm.

[0021] Optionally, the thickness of the Schottky contact metal is 0.2 μm to 0.6 μm, and the width of the Schottky contact metal is 0.3 μm to 0.8 μm.

[0022] In a second aspect, an embodiment of the present application provides a method for preparing a metal oxide semiconductor field effect transistor, the method comprising:

[0023] Forming a first epitaxial layer and a second epitaxial layer stacked in sequence on the upper surface of the substrate; the upper surface of the first epitaxial layer includes first buried regions arranged at intervals;

[0024] Performing a first ion implantation operation in a first target region on the upper surface of the second epitaxial layer to obtain ion implantation layers arranged at intervals;

[0025] Etching the second epitaxial layer along the longitudinal center line of the ion implantation layer to obtain a target groove penetrating the ion implantation layer;

[0026] performing a second ion implantation operation at the bottom of the target trench to form a second buried region in the second epitaxial layer in contact with the bottom of the target trench;

[0027] A first gate oxide layer, a first gate region, a second gate oxide layer, and a second gate region are sequentially prepared in the target trench to obtain a trench region; the first gate oxide layer is stacked on an inner wall of the trench region, and the first gate region, the second gate oxide layer, and the second gate region are sequentially stacked on an upper surface of the first gate oxide layer along a direction from the first epitaxial layer to the second epitaxial layer to form a split gate structure;

[0028] Prepare an original dielectric layer on the upper surface of the second epitaxial layer having the groove region;

[0029] preparing a target opening in a second target region of the original dielectric layer, and filling the target opening with a contact metal to obtain a dielectric layer;

[0030] A source metal layer is prepared on the upper surface of the dielectric layer, and a drain metal layer is prepared on the lower surface of the substrate to obtain the metal oxide semiconductor field effect transistor as described in any one of the above items.

[0031] In the metal oxide semiconductor field effect transistor provided in the embodiment of the present application, a trench region is introduced into the second epitaxial layer, and the first gate region, the second gate oxide layer and the second gate region in the trench region are sequentially stacked along the direction from the first epitaxial layer to the second epitaxial layer to form a split gate structure; the gate in the metal oxide semiconductor field effect transistor is divided into two by using the split gate structure, so that the gate-drain capacitance of the gate is reduced, and the gate-drain capacitance is positively correlated with the switching loss of the metal oxide semiconductor field effect transistor, which can reduce the dynamic loss of the metal oxide semiconductor field effect transistor; further, when the metal oxide semiconductor field effect transistor is in a reverse blocking state, the first gate region located at the bottom of the split gate structure is connected to the source metal layer at a low potential, and the PN junction of the body diode formed by the ion implantation layer and the second epitaxial layer generates a lateral depletion region, and the first gate region can promote the lateral depletion region to be connected to the depletion region formed by the first buried region arranged in the first epitaxial layer, so that the electric field distribution in the metal oxide semiconductor field effect transistor is more uniform, the electric field concentration at the bottom corner of the trench region is suppressed, and the electric field strength at the bottom position of the trench region is reduced, thereby improving the reliability of the metal oxide semiconductor field effect transistor.

[0032] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 1 ;

[0034] Figure 2 It is a flow chart of the steps of a method for preparing a metal oxide semiconductor field effect transistor provided in an embodiment of the present application;

[0035] Figure 3 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 2 ;

[0036] Figure 4 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 3 ;

[0037] Figure 5 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 4 ;

[0038] Figure 6 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 5 ;

[0039] Figure 7 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 6 ;

[0040] Figure 8 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 7 ;

[0041] Fig. 9 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 8 ;

[0042] Fig.10 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 9 ;

[0043] Fig.11 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 10 .

[0044] Description of reference numerals:

[0045] 10-cell; 11-drain metal layer; 12-substrate; 13-first epitaxial layer; 131-first buried region; 14-second epitaxial layer; 141-ion implantation layer; 1411-second ion implantation layer; 1412-first ion implantation layer; 142-groove region; 1421-first gate oxide layer; 1422-first gate region; 1423-second gate oxide layer; 1424-second gate region; 143-second buried region; 15-dielectric layer; 151-target opening; 1511-first opening; 1512-second opening; 15-1-original dielectric layer; 16-source metal layer; 01-target groove. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0047] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0048] Product Examples

[0049] The silicon carbide diode provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0050] Reference Figure 1 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 1 It should be noted that the schematic diagram of the cross-sectional structure of the metal oxide semiconductor field effect transistor is a schematic diagram of the cross-sectional structure along the thickness direction of the metal oxide semiconductor field effect transistor; the metal oxide semiconductor field effect transistor provided in the embodiment of the present application includes at least two cells 10, and after a voltage is applied to the metal oxide semiconductor field effect transistor, the cells 10 are in a parallel relationship.

[0051] like Figure 1 As shown, the metal oxide semiconductor field effect transistor includes a drain metal layer 11, a substrate 12, a first epitaxial layer 13, a second epitaxial layer 14, a dielectric layer 15 and a source metal layer 16 which are stacked in sequence.

[0052] The upper surface of the first epitaxial layer 13 includes first buried regions 131 that are spaced apart.

[0053] The second epitaxial layer 14 includes an ion implantation layer 141, a groove region 142 and a second buried region 143 which are arranged at intervals; the ion implantation layer 141 extends from the upper surface of the second epitaxial layer 14 to the inside of the second epitaxial layer 14 along the thickness direction of the metal oxide semiconductor field effect transistor; the groove region 142 penetrates the ion implantation layer 141 along the longitudinal center line of the ion implantation layer 141 and extends to the second buried region 143.

[0054] The trench region 142 includes a first gate oxide layer 1421, a first gate region 1422, a second gate oxide layer 1423 and a second gate region 1424; the first gate oxide layer 1421 is stacked on the inner wall of the trench region 142, and the first gate region 1422, the second gate oxide layer 1423 and the second gate region 1424 are stacked in sequence on the upper surface of the first gate oxide layer 1421 along the direction from the first epitaxial layer 13 to the second epitaxial layer 14, forming a split gate structure.

[0055] The dielectric layer 15 includes a target opening 151 , and the target opening 151 is filled with a contact metal; the contact metal is used to connect the second epitaxial layer 14 and the source metal layer 16 .

[0056] Specifically, the drain metal layer 11 may include any one of nickel (Ni), titanium (Ti) and titanium-nickel alloy and copper (Cu) aluminum (Al) alloy. In some embodiments, the thickness of the drain metal layer 11 is 0.5 μm to 1.5 μm. For example, the thickness of the drain metal layer 11 may be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm and 1.5 μm, or any two of the range values. In an embodiment of the present application, the drain metal layer 11 serves as a back metal electrode layer connected to the substrate 12, providing good electrical contact for the metal oxide semiconductor field effect transistor, ensuring that the current can smoothly pass through the metal oxide semiconductor field effect transistor.

[0057] The substrate 12 is an N-type heavily doped (N+) silicon carbide substrate, and the substrate 12 can be any one of a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate, and a 3C-SiC single crystal substrate; as the bottom material of the entire metal oxide semiconductor field effect transistor, the substrate 12 provides physical support for the metal oxide semiconductor field effect transistor and ensures the structural integrity of the metal oxide semiconductor field effect transistor. In addition, the silicon carbide substrate has excellent thermal and electrical conductivity, so that the substrate 12 can effectively remove the heat generated inside the metal oxide semiconductor field effect transistor and improve the uniformity of the current distribution in the metal oxide semiconductor field effect transistor. The thickness of the substrate 12 is 100 μm to 150 μm, for example, the thickness of the substrate 12 is one or any two of 100 μm, 110 μm, 120 μm, 130 μm, 140 μm and 150 μm.

[0058] The first epitaxial layer 13 is stacked on the upper surface of the substrate 12, and the upper surface of the first epitaxial layer 13 away from the substrate 12 includes at least two first buried regions 131 spaced apart from each other, and the spacing between the first buried regions 131 is equal. It can be understood that the spacing between the first buried regions 131 refers to the minimum distance between two adjacent first buried regions 131 in the upper surface of the first epitaxial layer 13. The spacing between the first buried regions 131 can be 1 μm to 3 μm.

[0059] Among them, the first epitaxial layer 13 is an N-type lightly doped (N-) silicon carbide epitaxial layer, and the thickness of the first epitaxial layer 13 is 4μm to 10μm. In some embodiments, the thickness of the first epitaxial layer 13 can be a range of one or any two of 4μm, 5μm, 6μm, 7μm, 8μm, 9μm and 10μm.

[0060] The first buried region 131 is a P-type heavily doped (P+) region, and the depth of the first buried region 131 is less than the thickness of the first epitaxial layer 13 .

[0061] In the embodiment of the present application, the first buried regions 131 with equal spacing arranged on the upper surface of the first epitaxial layer 13 can increase the voltage resistance of the metal oxide semiconductor field effect transistor, adjust the uniform distribution of the electric field in the metal oxide semiconductor field effect transistor, so that when a reverse bias voltage is applied to the metal oxide semiconductor field effect transistor, the depletion regions of the first doped regions are connected, shielding the Schottky region above the metal oxide semiconductor field effect transistor, reducing the electric field strength at the lower corner of the trench region 142 and the electric field strength at the Schottky contact position, thereby improving the reliability of the metal oxide semiconductor field effect transistor in high temperature, high field and other application scenarios.

[0062] Reference Figure 1 The second epitaxial layer 14 is stacked on the upper surface of the first epitaxial layer 13, and the second epitaxial layer 14 is away from the upper surface of the first epitaxial layer 13 and includes at least two ion implantation layers 141 arranged at intervals and extending from the upper surface of the second epitaxial layer 14 to the inside of the second epitaxial layer 14 along the direction of the thickness of the metal oxide semiconductor field effect transistor; each ion implantation layer 141 corresponds to a trench area 142 and a second buried area 143, and there is a one-to-one correspondence between the trench area 142 and the second buried area 143.

[0063] Specifically, the trench region 142 penetrates the ion implantation layer 141 along the longitudinal center line of the ion implantation layer 141 and extends to the second buried region 143 inside the second epitaxial layer 14 .

[0064] The longitudinal center line of the trench region 142 coincides with the longitudinal center line of the ion implantation layer 141 , and the longitudinal center line refers to the center line along the thickness direction of the MOSFET.

[0065] In the second epitaxial layer 14 , the spacings between the ion implantation layers 141 are equal; it can be understood that the spacing between the ion implantation layers 141 refers to the minimum distance between two adjacent ion implantation layers 141 on the upper surface of the second epitaxial layer 14 .

[0066] The second epitaxial layer 14 is an N-type lightly doped silicon carbide epitaxial layer, and the thickness of the second epitaxial layer 14 is 4μm to 10μm. In some embodiments, the thickness of the second epitaxial layer 14 can be one or any two of 4μm, 5μm, 6μm, 7μm, 8μm, 9μm and 10μm.

[0067] In the second epitaxial layer 14 , the sum of the depths of the trench region 142 and the second buried region 143 is smaller than the thickness of the second epitaxial layer 14 .

[0068] In the embodiment of the present application, the trench region 142 includes a first gate oxide layer 1421 , a first gate region 1422 , a second gate oxide layer 1423 and a second gate region 1424 .

[0069] Among them, the first gate oxide layer 1421 is stacked on the upper surface of the inner wall of the groove area 142. The first gate area 1422, the second gate oxide layer 1423 and the second gate area 1424 are stacked in sequence on the upper surface of the first gate oxide layer along the direction from the first epitaxial layer 13 to the second epitaxial layer 14 to form a split gate structure. It can be understood that in the gate area, the first gate area 1422 is stacked on the bottom of the groove area 142 provided with the first gate oxide layer 1421, the upper surface of the first gate area 1422 is stacked with the second gate oxide layer 1423, and the upper surface of the second gate oxide layer 1423 is stacked with the second gate area 1424.

[0070] It should be noted that the first gate oxide layer 1421 and the second gate oxide layer 1423 are made of the same material. Specifically, the first gate oxide layer 1421 and the second gate oxide layer 1423 can be silicon dioxide (SiO2) layers. The first gate oxide layer 1421 is used to separate the first gate region 1422 and the second gate region 1424 from the second epitaxial layer 14, and the second gate oxide layer 1423 is used to separate the first gate region 1422 and the second gate region 1424 to form a split gate structure.

[0071] The first gate region 1422 and the second gate region 1424 are made of the same material. In the embodiment of the present application, the first gate region 1422 and the second gate region 1424 are polysilicon (PolySi).

[0072] In addition, refer to Figure 1The ion implantation region 141 includes a first ion implantation layer 1412 and a second ion implantation layer 1411 which are sequentially stacked along the thickness direction of the MOSFET; the upper surface of the second ion implantation layer 1411 overlaps with the upper surface of the second epitaxial layer 14 .

[0073] Among them, the first ion injection layer 1412 serves as the lower layer in the ion injection area 141, and the first ion injection layer 1412 is a P-type lightly doped (P-) layer. The second ion injection layer 1411 serves as the upper layer in the ion injection area 141, and the second ion injection layer 1411 includes a P-type heavily doped area and an N-type heavily doped area; one end of the N-type heavily doped area is connected to the first gate oxide layer 1421 of the trench area 142; one end of the N-type heavily doped area away from the trench area 142 is connected to the P-type heavily doped area.

[0074] In the embodiment of the present application, the gate of the metal oxide semiconductor field effect transistor is divided into two, so that the gate-drain capacitance of the gate is reduced, and the gate-drain capacitance is positively correlated with the switching loss of the metal oxide semiconductor field effect transistor, thereby reducing the dynamic loss of the metal oxide semiconductor field effect transistor; when the metal oxide semiconductor field effect transistor is in a reverse blocking state, that is, when a reverse bias voltage is applied to the metal oxide semiconductor field effect transistor, the first gate region 1422 located at the lower part of the split gate structure is connected to the source metal layer 16 at a low potential, and the PN junction of the body diode formed by the first ion implantation layer 1412 in the ion implantation layer 141 and the second epitaxial layer 14 generates a lateral depletion region, and the first gate region 1422 can promote the connection between the lateral depletion region and the depletion region formed by the first buried region 131 arranged in the first epitaxial layer 13, so that the electric field distribution in the metal oxide semiconductor field effect transistor is more uniform, further suppressing the electric field concentration at the bottom corner of the trench region 142, reducing the electric field strength at the bottom position of the trench region 142, improving the withstand voltage characteristics of the metal oxide semiconductor field effect transistor, and thus improving the reliability of the metal oxide semiconductor field effect transistor.

[0075] Reference Figure 1 The dielectric layer 15 is stacked on the upper surface of the second epitaxial layer 14. The dielectric layer 15 is specifically an isolation layer definition (ILD) oxide layer. In the embodiment of the present application, the dielectric layer 15 includes silicon dioxide.

[0076] In the embodiment of the present application, the dielectric layer 15 mainly plays the role of isolation and insulation. In addition, the dielectric layer 15 is also used to provide a metal contact position so that the source metal layer 16 and the second epitaxial layer 14 in the metal oxide semiconductor field effect transistor can be electrically connected; specifically, the dielectric layer 15 includes a plurality of target openings 151, and the second epitaxial layer 14 and the source metal layer 16 are connected through the contact metal filled in the target openings 151.

[0077] The target opening 151 includes openings corresponding to the P-type heavily doped (P+) region and the N-type heavily doped region in the second ion implantation layer 1411 and openings corresponding to the spacing regions between the ion implantation layers 141. The contact metal includes an ohmic contact metal and a Schottky contact metal; the openings corresponding to the P-type heavily doped region and the N-type heavily doped region in the second ion implantation layer 1411 are filled with the ohmic contact metal, and the openings corresponding to the spacing regions between the ion implantation layers 141 are filled with the Schottky contact metal.

[0078] The source metal layer 16 may include copper and / or aluminum; the thickness of the source metal layer 16 is 2 μm to 4 μm, specifically, the thickness of the source metal layer 16 may be in the range of one or any two of 2 μm, 2.5 μm, 3 μm, 3.5 μm and 4 μm.

[0079] 4H-SiC has excellent physical and electrical properties, such as high electron saturation drift velocity, high critical breakdown electric field, wide bandgap and high thermal conductivity, and is suitable for high temperature and high voltage power electronics. Vertical metal oxide semiconductor field effect transistors include double diffused metal oxide semiconductor field effect transistors (DMOSFET) and power trench gate metal oxide semiconductor field effect transistors, while 4H-SiC UMOSFET has smaller on-resistance and larger channel density due to its higher density cell size and high mobility of non-polar surface, so it has a broader application prospect. In the related technology, in the field of power electronics, such as photovoltaic inverter, motor drive and DC-DC conversion, it is necessary to parasitize a PN body diode inside the 4H-SiC UMOSFET so that the PN body diode acts as a reverse recovery diode to form a complete current path. However, in the related technology, the parasitic PN body diode inside the SiC UMOSFET will produce higher dynamic losses, and when the SiCUMOSFET is in a reverse blocking state, there will be a two-dimensional electric field concentration at the corner of the groove in the SiC UMOSFET, resulting in a higher electric field strength at the bottom of the groove, which in turn leads to a decrease in the reliability of the device. The metal oxide semiconductor field effect transistor provided in the embodiment of the present application, firstly, the first buried regions 131 with equal spacings arranged on the upper surface of the first epitaxial layer 13 can increase the withstand voltage of the metal oxide semiconductor field effect transistor, adjust the uniform distribution of the electric field in the metal oxide semiconductor field effect transistor, so that when a reverse bias voltage is applied to the metal oxide semiconductor field effect transistor, the depletion region of the first doped region is connected, shielding the Schottky region above the metal oxide semiconductor field effect transistor, reducing the electric field strength at the corner of the lower part of the groove region 142 and the electric field strength at the Schottky contact position, and improving the reliability of the metal oxide semiconductor field effect transistor in high temperature, high field and other application scenarios.Furthermore, a trench region 142 is introduced into the second epitaxial layer 14, and the first gate region 1422, the second gate oxide layer 1423 and the second gate region 1424 in the trench region 142 are stacked in sequence along the direction from the first epitaxial layer 13 to the second epitaxial layer 14 to form a split gate structure; the gate in the metal oxide semiconductor field effect transistor is divided into two by the split gate structure, so that the gate-drain capacitance of the gate is reduced, and the gate-drain capacitance is positively correlated with the switching loss of the metal oxide semiconductor field effect transistor, which can reduce the dynamic loss of the metal oxide semiconductor field effect transistor; in addition, when the metal oxide semiconductor field effect transistor is in a reverse blocking state, the gate located at the lower part of the split gate structure The first gate region 1422 is connected to the source metal layer 16 at a low potential. The PN junction of the body diode formed by the first ion implantation layer 1412 and the second epitaxial layer 14 in the ion implantation layer 141 generates a lateral depletion region. The first gate region 1422 can promote the connection between the lateral depletion region and the depletion region formed by the first buried region 131 arranged in the first epitaxial layer 13, so that the electric field distribution in the metal oxide semiconductor field effect transistor is more uniform, further suppressing the electric field concentration at the bottom corner of the trench region 142, reducing the electric field strength at the bottom position of the trench region 142, improving the withstand voltage characteristics of the metal oxide semiconductor field effect transistor, and thereby improving the reliability of the metal oxide semiconductor field effect transistor.

[0080] Optionally, the width of the first gate region 1422 is less than or equal to the width of the second gate region 1424 , and the width of the first gate region 1422 and / or the second gate region 1424 is 0.5 μm to 1 μm.

[0081] Specifically, the sidewalls of the trench region 142 may be as follows: Figure 1 The inclined sidewalls shown are at a certain angle to the lower surface of the second epitaxial layer 14, so that the width of the opening area of ​​the trench area 142 is greater than the width of the bottom area of ​​the trench area 142; the sidewalls of the trench area 142 may also be sidewalls perpendicular to the lower surface of the second epitaxial layer 14, so that the width of the opening area of ​​the trench area 142 is equal to the width of the bottom area of ​​the trench area 142. The specific form of the sidewalls of the trench area 142 is not limited in the embodiment of the present application.

[0082] It can be understood that, when the sidewalls of the trench region 142 are inclined sidewalls forming a certain angle with the lower surface of the second epitaxial layer 14, the width of the first gate region 1422 is smaller than the width of the second gate region 1424; when the sidewalls of the trench region 142 are sidewalls perpendicular to the lower surface of the second epitaxial layer 14, the width of the first gate region 1422 is equal to the width of the second gate region 1424.

[0083] In some embodiments, when the width of the first gate region 1422 is less than or equal to the width of the second gate region 1424, the width of the first gate region 1422 can be a range of one or any two of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm and 1 μm, and the width of the second gate region 1424 can be a range of one or any two of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm and 1 μm.

[0084] Optionally, the thickness of the first gate region 1422 and / or the second gate region 1424 is 0.5 μm to 1.5 μm. In the embodiment of the present application, the thickness of the first gate region 1422 and the second gate region 1424 may be the same or different. Specifically, the thickness of the first gate region 1422 may be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm and 1.5 μm, or any two of the range values; the thickness of the second gate region 1424 may be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm and 1.5 μm, or any two of the range values.

[0085] Optionally, the thickness of the first gate oxide layer 1421 is greater than the thickness of the second gate oxide layer 1423 .

[0086] In the embodiment of the present application, while utilizing a split gate structure to divide the gate in the metal oxide semiconductor field effect transistor into two, thereby reducing the gate-drain capacitance of the gate, the thickness of the first gate oxide layer 1421 is controlled to be greater than the thickness of the second gate oxide layer 1423, so that the thickness of the first gate oxide layer 1421 in contact with the lower surface of the first gate region 1422 can be thicker than the thickness of the second gate oxide layer 1423 stacked on the upper surface of the first gate region 1422, thereby enabling the first gate region 1422 to convert a considerable portion of the gate-drain capacitance into a gate-source capacitance, thereby further reducing the gate-drain capacitance, and thereby reducing the dynamic loss of the metal oxide semiconductor field effect transistor.

[0087] Optionally, the thickness of the second gate oxide layer 1423 is 0.05 μm to 0.12 μm. In some embodiments, the thickness of the second gate oxide layer 1423 can be in the range of one or any two of 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.10 μm, 0.11 μm and 0.12 μm.

[0088] Optionally, the thickness of the first gate oxide layer 1421 is 0.08 μm to 0.15 μm. In some embodiments, the thickness of the first gate oxide layer 1421 may be in the range of one or any two of 0.08 μm, 0.09 μm, 0.10 μm, 0.11 μm, 0.12 μm, 0.13 μm, 0.14 μm and 0.15 μm.

[0089] It should be noted that in the embodiment of the present application, the sum of the thicknesses of the first gate region 1422 , the second gate region 1424 , the first gate oxide layer 1421 and the second gate oxide layer 1423 is equal to the depth of the trench region 142 . In other words, the upper surface of the second gate region 1424 is flush with the upper surface of the second epitaxial layer 14 .

[0090] Optionally, the minimum value of the angle between the sidewall of the trench region 142 and the lower surface of the second epitaxial layer 14 is 85° to 89°. Specifically, in some embodiments, the minimum value of the angle between the sidewall of the trench region 142 and the lower surface of the second epitaxial layer 14 can be a range of one or any two of 85°, 86°, 87°, 88° and 89°.

[0091] It can be understood that when the minimum angle between the side wall of the trench region 142 and the lower surface of the second epitaxial layer 14 is 85° to 89°, it is beneficial to control the angle of ion implantation during the preparation of the second buried region 143, and when the minimum angle between the side wall of the trench region 142 and the lower surface of the second epitaxial layer 14 is 85° to 89°, the opening of the trench region 142 can also be enlarged, which is beneficial to the preparation of the first gate oxide layer 1421, the first gate region 1422, the second gate oxide layer 1423 and the second gate region 1424.

[0092] Optionally, the depth of the trench region 142 is 2 μm to 3 μm, and the width of the trench region 142 is 0.5 μm to 1.2 μm.

[0093] The depth and width of the trench region 142 refer to the depth and width of the original trench before the first gate oxide layer 1421, the first gate region 1422, the second gate oxide layer 1423, and the second gate region 1424 are prepared. It should be noted that, when the sidewall of the trench region 142 is an inclined sidewall that forms a certain angle with the lower surface of the second epitaxial layer 14, the maximum width and the minimum width of the trench region 142 are both within the range of 0.5 μm to 1.2 μm.

[0094] In some embodiments, the depth of the trench region 142 may be in a range of one or any two of 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, and 3 μm.

[0095] In some embodiments, the width of the trench region 142 may be in a range of one or any two of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, and 1.2 μm.

[0096] Optionally, refer to Figure 1 The target opening 151 includes a first opening 1511 corresponding to the ion implantation layer 141 and a second opening 1512 corresponding to the spacing region between the ion implantation layers 141 .

[0097] Among them, the contact metal includes ohmic contact metal and Schottky contact metal. The first opening 1511 is filled with ohmic contact metal to form a front ohmic metal contact area between the source metal layer 16 and the semiconductor formed by the second ion implantation layer 1411; the second opening 1512 is filled with Schottky contact metal to form a Schottky metal contact area between the source metal layer 16 and the second epitaxial layer 14.

[0098] It should be noted that the first opening 1511 simultaneously exposes the upper surfaces of the P-type heavily doped region and the N-type heavily doped region in the second ion implantation layer 1411 to ensure that the ohmic contact metal filled in the first opening 1511 can form an ohmic contact between the source metal layer 16 and the second ion implantation layer 1411 .

[0099] In the embodiment of the present application, the Schottky metal contact region formed by the Schottky contact metal filled in the second opening 1512 between the source metal layer 16 and the second epitaxial layer 14 serves as the anode region in the junction barrier Schottky diode (JBS) in the metal oxide semiconductor field effect transistor. The metal system of the Schottky metal contact region is compatible with the metal system of the front ohmic metal contact region. The embodiment of the present application selects a low-barrier Schottky contact metal to form the Schottky metal contact region, which reduces the source-drain turn-on voltage of the metal oxide semiconductor field effect transistor when working in the third quadrant, eliminates the bipolar conduction degradation caused by the parasitic PN-type body diode in the metal oxide semiconductor field effect transistor, improves the unipolar carrier working ability of the metal oxide semiconductor field effect transistor, improves the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic PN-type body diode in the metal oxide semiconductor field effect transistor, reduces the source-drain turn-on voltage and reverse recovery time of the parasitic PN-type body diode in the metal oxide semiconductor field effect transistor, and thus reduces the reverse recovery loss of the metal oxide semiconductor field effect transistor.

[0100] It can be understood that in the embodiment of the present application, each junction between the P-type heavily doped region and the N-type heavily doped region in the second ion implantation layer 1411 corresponds to a first opening 1511 ; and each spacing area between the ion implantation layers 141 corresponds to a second opening 1512 .

[0101] Optionally, the ohmic contact metal and / or the Schottky contact metal includes any one of nickel, titanium, a titanium-nickel alloy, and a copper-aluminum alloy.

[0102] Optionally, the thickness of the ohmic contact metal and / or the Schottky contact metal is less than or equal to the thickness of the dielectric layer 15 .

[0103] Specifically, the dielectric layer 15 has good electrical stability and can withstand a certain voltage and current without breakdown or failure. When the thickness of the ohmic contact metal and / or the Schottky contact metal is greater than the thickness of the dielectric layer 15, the electric field strength on the dielectric layer 15 will increase, making the dielectric layer 15 more prone to breakdown, thereby affecting the electrical performance and reliability of the metal oxide semiconductor field effect transistor. In the embodiment of the present application, the thickness of the ohmic contact metal and / or the Schottky contact metal is less than or equal to the thickness of the dielectric layer 15, which can reduce the probability of breakdown or failure of the dielectric layer 15 and improve the electrical performance and reliability of the metal oxide semiconductor field effect transistor.

[0104] Optionally, the thickness of the ohmic contact metal is 60 nm to 200 nm, and the width of the ohmic contact metal is 0.2 μm to 0.5 μm.

[0105] The width of the ohmic contact metal is equal to the width of the first opening 1511 .

[0106] Specifically, in some embodiments, the thickness of the ohmic contact metal may be in the range of one or any two of 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm and 200 nm.

[0107] In some embodiments, the width of the ohmic contact metal may be in a range of one or any two of 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, and 0.5 μm.

[0108] Optionally, the thickness of the Schottky contact metal is 0.2 μm to 0.6 μm, and the width of the Schottky contact metal is 0.3 μm to 0.8 μm.

[0109] The width of the Schottky contact metal is equal to the width of the second opening 1512 .

[0110] Specifically, in some embodiments, the thickness of the Schottky contact metal may be in the range of one or any two of 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm and 0.6 μm.

[0111] In some embodiments, the width of the Schottky contact metal may be in a range of one or any two of 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm and 0.8 μm.

[0112] In summary, in the metal oxide semiconductor field effect transistor provided in the embodiment of the present application, the trench region 142 is introduced into the second epitaxial layer 14, and the first gate region 1422, the second gate oxide layer 1423 and the second gate region 1424 in the trench region 142 are stacked in sequence along the direction from the first epitaxial layer 13 to the second epitaxial layer 14 to form a split gate structure; the gate in the metal oxide semiconductor field effect transistor is divided into two by using the split gate structure, so that the gate-drain capacitance of the gate is reduced, and the gate-drain capacitance is positively correlated with the switching loss of the metal oxide semiconductor field effect transistor, which can reduce the dynamic loss of the metal oxide semiconductor field effect transistor; further, in the metal oxide When the semiconductor field effect transistor is in a reverse blocking state, the first gate region 1422 located at the bottom of the split gate structure is connected to a low potential with the source metal layer 16, and the PN junction of the body diode formed by the ion implantation layer 141 and the second epitaxial layer 14 generates a lateral depletion region. The first gate region 1422 can promote the lateral depletion region to be connected with the depletion region formed by the first buried region 131 arranged in the first epitaxial layer 13, so that the electric field distribution in the metal oxide semiconductor field effect transistor is more uniform, the electric field concentration at the bottom corner of the trench region 142 is suppressed, and the electric field strength at the bottom position of the trench region 142 is reduced, thereby improving the reliability of the metal oxide semiconductor field effect transistor.

[0113] Method Embodiment

[0114] Reference Figure 2 , shows a flowchart of a method for preparing a metal oxide semiconductor field effect transistor provided in an embodiment of the present application, the method comprising steps S101 to S108:

[0115] Step S101 , forming a first epitaxial layer and a second epitaxial layer stacked in sequence on an upper surface of a substrate; an upper surface of the first epitaxial layer includes first buried regions arranged at intervals.

[0116] Specifically, first, refer to Figure 3 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 2, epitaxial growth is performed on the upper surface of the substrate 12 to obtain a first epitaxial layer 13 stacked on the upper surface of the substrate 12.

[0117] Then, refer to Figure 4 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 3 , the upper surface of the first epitaxial layer 13 is cleaned, and a layer of plasma enhanced tetraethyl orthosilicate (PETEOS) is deposited on the upper surface of the first epitaxial layer 13; then, photoresist is spin-coated on the upper surface of the PETEOS layer, and an ion implantation window corresponding to the first buried area 131 is formed by photolithography and etching processes; then, the photoresist is removed, and the PETEOS layer is used as a mask to perform a third ion implantation operation to remove the PETEOS layer, thereby obtaining a first epitaxial layer 13 having an upper surface including first buried areas 131 arranged at intervals. The third ion implantation operation is an aluminum ion implantation operation; the spacing between the first buried areas 131 is equal, and the spacing between the first buried areas 131 can be 1 μm to 3 μm; the depth of the first buried area 131 is less than the thickness of the first epitaxial layer 13.

[0118] Finally, refer to Figure 5 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 4 A sacrificial oxide layer is prepared on the upper surface of the first epitaxial layer 13 to remove surface defects introduced by the third ion implantation operation on the upper surface of the first epitaxial layer 13 by the sacrificial oxide layer, and epitaxial growth is performed on the upper surface of the first epitaxial layer 13 to obtain a second epitaxial layer 14 stacked on the upper surface of the first epitaxial layer 13.

[0119] The substrate 12 is an N-type heavily doped silicon carbide substrate, and the substrate 12 can be any one of a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate, and a 3C-SiC single crystal substrate. In steps S101 to S107, the thickness of the substrate 12 is 200 μm to 300 μm.

[0120] The first epitaxial layer 13 is an N-type lightly doped N-silicon carbide epitaxial layer. The doping concentration of the first epitaxial layer 13 is 6×10 15 cm -3 Up to 6×10 16 cm -3 ; The thickness of the first epitaxial layer 13 is 4μm to 10μm.

[0121] The second epitaxial layer 14 is an N-type lightly doped silicon carbide epitaxial layer, and the doping concentration of the second epitaxial layer 14 is 6×10 15 cm -3Up to 6×10 16 cm -3 ; The thickness of the second epitaxial layer 14 is 4μm to 10μm.

[0122] The first buried region 131 is a P-type heavily doped region, and the doping concentration of the first buried region 131 is 1×10 18 cm -3 Up to 1×10 20 cm -3 .

[0123] Step S102 : performing a first ion implantation operation in a first target region on the upper surface of the second epitaxial layer to obtain ion implantation layers arranged at intervals.

[0124] The first target area is the area on the upper surface of the second epitaxial layer 14 where the ion implantation layer 141 is located.

[0125] The first ion implantation operation includes a first sub-operation, a second sub-operation and a third sub-operation. Figure 6 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 5 First, the upper surface of the second epitaxial layer 14 is cleaned, and a PETEOS layer is deposited on the upper surface of the second epitaxial layer 14 .

[0126] Then, photoresist is spin-coated on the upper surface of the PETEOS layer, and an ion implantation window corresponding to the first target area is formed through photolithography and etching processes.

[0127] Then, the photoresist is removed, and the PETEOS layer is used as a mask to perform a first sub-operation, and the PETEOS layer is removed to form a first original ion implantation layer extending from the upper surface of the second epitaxial layer 14 to the inside of the second epitaxial layer 14; the first sub-operation is an aluminum ion implantation operation.

[0128] Then, a PETEOS layer is deposited on the upper surface of the second epitaxial layer 14, and photoresist is spin-coated on the upper surface of the PETEOS layer, and ion implantation windows corresponding to the P-type heavily doped regions in the second ion implantation layer 1411 are formed by photolithography and etching processes.

[0129] Then, the photoresist is removed, and the PETEOS layer is used as a mask to perform a second sub-operation, and the PETEOS layer is removed to form a P-type heavily doped region in the second ion implantation layer 1411; the second sub-operation is an aluminum ion implantation operation.

[0130] Then, a PETEOS layer is deposited on the upper surface of the second epitaxial layer 14, and photoresist is spin-coated on the upper surface of the PETEOS layer, and ion implantation windows corresponding to the N-type heavily doped regions in the second ion implantation layer 1411 are formed by photolithography and etching processes.

[0131] Then, the photoresist is removed, and the PETEOS layer is used as a mask to perform a third sub-operation, and the PETEOS layer is removed to form an N-type heavily doped region in the second ion implantation layer 1411, thereby obtaining a second ion implantation layer 1411 consisting of a P-type heavily doped region and an N-type heavily doped region; wherein the third sub-operation is a nitrogen ion implantation operation.

[0132] It should be noted that the upper part of the first original ion injection layer is formed into a second ion injection layer 1411 including two P-type heavily doped regions and one N-type heavily doped region through the second sub-operation and the third sub-operation, and the part of the first original ion injection layer outside the second ion injection layer 1411 is the first ion injection layer 1412, and the second ion injection layer 1411 is stacked on the upper surface of the first ion injection layer 1412; the thickness of the first original ion injection layer is equal to the sum of the thicknesses of the second ion injection layer 1411 and the first ion injection layer 1412.

[0133] In the ion implantation layer 141 , the left and right ends of the N-type heavily doped region in the second ion implantation layer 1411 are connected to the P-type heavily doped region respectively.

[0134] The intervals between the ion implantation layers 141 in the upper surface of the second epitaxial layer 14 are equal.

[0135] In addition, the doping concentrations of the second ion implantation layer 1411 and the first ion implantation layer 1412 in the implantation layer 141 may be determined according to actual requirements, and are not limited in this embodiment of the present application.

[0136] Step S103 , etching the second epitaxial layer along the longitudinal center line of the ion implantation layer to obtain a target groove penetrating the ion implantation layer.

[0137] Specifically, in the case where the ion implantation layers 141 spaced apart on the upper surface of the second epitaxial layer 14 are obtained by step S102, the second epitaxial layer 14 can be etched along the longitudinal center line of each ion implantation layer 141 by etching processes such as growth mask medium, photolithography, dry etching, surface oxidation, and selective etching to obtain the target groove 01 penetrating the ion implantation layer 141, referring to Figure 7 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 6 .

[0138] In the embodiment of the present application, for each ion implantation layer 141 , the longitudinal center line of the target trench 01 coincides with the longitudinal center line of the ion implantation layer 141 .

[0139] The sidewall of the target trench 01 may be as follows Figure 7 The inclined sidewall shown is at a certain angle to the lower surface of the second epitaxial layer 14, so that the width of the target groove 01 opening area is greater than the width of the target groove 01 bottom area; the sidewall of the target groove 01 can also be a sidewall perpendicular to the lower surface of the second epitaxial layer 14, so that the width of the target groove 01 opening area is equal to the width of the bottom area of ​​the groove area 142. The specific form of the sidewall of the target groove 01 is not limited in the embodiment of the present application.

[0140] When the sidewall of the target trench 01 is an inclined sidewall forming a certain angle with the lower surface of the second epitaxial layer 14 , the minimum angle between the sidewall of the target trench 01 and the lower surface of the second epitaxial layer 14 is 85° to 89°.

[0141] When the sidewalls of the target groove 01 are inclined sidewalls that form a certain angle with the lower surface of the second epitaxial layer 14, after the second epitaxial layer 14 is etched through etching treatments such as growth mask dielectric, photolithography, dry etching, surface oxidation, and selective corrosion, it is necessary to etch the sidewalls of the target groove 01 through a reactive ion etching (RIF) process to obtain a target groove 01 whose sidewalls form a certain angle with the lower surface of the second epitaxial layer 14.

[0142] In the embodiment of the present application, the depth of the target groove 01 is 2 μm to 3 μm, and the width of the target groove 01 is 0.5 μm to 1.2 μm.

[0143] Step S104 , performing a second ion implantation operation at the bottom of the target trench to form a second buried region in the second epitaxial layer that contacts the bottom of the target trench.

[0144] Specifically, during the second ion implantation operation at the bottom of the target trench 01, refer to Figure 8 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 7 A second ion implantation operation may be performed by tilted angle implantation to form a second buried region 143 in the second epitaxial layer 14 that contacts the bottom of the target trench 01 , wherein the tilted angle of the tilted angle implantation is 0° to 30°.

[0145] The second ion implantation operation is an aluminum ion implantation operation.

[0146] It can be understood that after step S104 , in the second epitaxial layer 14 , the target trench 01 penetrates the ion implantation layer 141 and extends to contact the second buried region 143 .

[0147] In the second epitaxial layer 14 , the sum of the depths of the target trench 01 and the second buried region 143 is less than the thickness of the second epitaxial layer 14 .

[0148] Step S105, sequentially preparing a first gate oxide layer, a first gate region, a second gate oxide layer, and a second gate region in the target trench to obtain a trench region; the first gate oxide layer is stacked on the inner wall of the trench region, and the first gate region, the second gate oxide layer, and the second gate region are sequentially stacked on the upper surface of the first gate oxide layer along the direction from the first epitaxial layer to the second epitaxial layer to form a split gate structure.

[0149] Specifically, first, a sacrificial oxide layer of good quality is formed on the upper surface of the second epitaxial layer 14 after step S104 by using a dry oxygen thermal oxidation method, and the interface damage caused by ion implantation and ion etching is removed by wet etching the sacrificial oxide layer; then, after the sacrificial oxide layer is removed, Fig. 9 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 8 A first gate oxide layer 1421 with low interface state density and high mobility is grown on the upper surface of the inner wall of the target trench 01 by a combination of dry oxygen thermal oxidation, deposition and annealing, wherein the temperature of the dry oxygen thermal oxidation is 1000° C. to 1500° C.; then, a ... A first polysilicon deposition and etching process is performed to obtain a first gate region 1422 stacked on the bottom of the target trench 01 provided with a first gate oxide layer 1421; then, a second gate oxide layer 1423 is grown on the upper surface of the first gate region 1422; then, a second polysilicon deposition is performed on the upper surface of the second gate oxide layer 1423 to obtain a second gate region 1424; finally, through annealing activation, planarization, photolithography, etching and other processes, a trench region 142 including the first gate oxide layer 1421, the first gate region 1422, the second gate oxide layer 1423 and the second gate region 1424 is obtained.

[0150] Among them, processes such as annealing activation, planarization, photolithography, and etching are beneficial to optimizing the surface morphology of the first gate region 1422 and the second gate region 1424 and improving the reliability of the trench region 142 .

[0151] In the trench region 142, the first gate oxide layer 1421 is stacked on the upper surface of the inner wall of the trench region 142. The first gate region 1422, the second gate oxide layer 1423, and the second gate region 1424 are stacked in sequence on the upper surface of the first gate oxide layer 1421 along the direction from the first epitaxial layer 13 to the second epitaxial layer 14, forming a split gate structure. It can be understood that in the gate region, the first gate region 1422 is stacked on the bottom of the trench region 142 where the first gate oxide layer 1421 is provided, the second gate oxide layer 1423 is stacked on the upper surface of the first gate region 1422, and the second gate region 1424 is stacked on the upper surface of the second gate oxide layer 1423.

[0152] It should be noted that the first gate oxide layer 1421 and the second gate oxide layer 1423 are made of the same material. Specifically, the first gate oxide layer 1421 and the second gate oxide layer 1423 may be silicon dioxide layers.

[0153] The first gate region 1422 and the second gate region 1424 are made of the same material. In the embodiment of the present application, the first gate region 1422 and the second gate region 1424 are made of polysilicon, and the doping concentration of the polysilicon can be 10 21 cm -3 Up to 2×10 19 cm -3 .

[0154] In the embodiment of the present application, the width of the first gate region 1422 is less than or equal to the width of the second gate region 1424, and the width of the first gate region 1422 and / or the second gate region 1424 is 0.5 μm to 1 μm. In the case where the sidewall of the trench region 142 is an inclined sidewall at a certain angle to the lower surface of the second epitaxial layer 14, the width of the first gate region 1422 is less than the width of the second gate region 1424; in the case where the sidewall of the trench region 142 is a sidewall perpendicular to the lower surface of the second epitaxial layer 14, the width of the first gate region 1422 is equal to the width of the second gate region 1424.

[0155] The thickness of the first gate region 1422 and / or the second gate region 1424 is 0.5 μm to 1.5 μm.

[0156] The thickness of the second gate oxide layer 1423 is 0.05 μm to 0.12 μm; the thickness of the first gate oxide layer 1421 is 0.08 μm to 0.15 μm, and the thickness of the first gate oxide layer 1421 is greater than that of the second gate oxide layer 1423 .

[0157] Step S106: preparing an original dielectric layer on the upper surface of the second epitaxial layer having the trench region.

[0158] Specifically, an ILD oxide layer is deposited on the upper surface of the second epitaxial layer 14 by a deposition process to obtain an original dielectric layer 15-1. Fig.10 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 9 .

[0159] Step S107 , preparing a target opening in the second target region of the original dielectric layer, and filling the target opening with a contact metal to obtain a dielectric layer.

[0160] Specifically, first, a first opening 1511 corresponding to the ion implantation layer 141 and a second opening 1512 corresponding to the spacing region between the ion implantation layers 141 are obtained in the second target region of the original dielectric layer 15-1 by photolithography, etching, and stripping processes; then, an ohmic contact metal is formed in the first opening 1511 and a Schottky contact metal is formed in the second opening 1512 by deposition, metallization, and high-temperature annealing treatment, thereby obtaining the dielectric layer 15, as shown in FIG. Fig.11 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 10 .

[0161] The first opening 1511 and the second opening 1512 constitute a target opening 151 in the dielectric layer 15 , and the ohmic contact metal filled in the first opening 1511 and the Schottky contact metal filled in the second opening 1512 constitute a contact metal filled in the target opening 151 .

[0162] The ohmic contact metal filled in the first opening 1511 forms a front ohmic metal contact region between the source metal layer 16 and the semiconductor formed by the second ion implantation layer 1411 ; the Schottky contact metal filled in the second opening 1512 forms a Schottky metal contact region between the source metal layer 16 and the second epitaxial layer 14 .

[0163] It should be noted that the first opening 1511 simultaneously exposes the upper surfaces of the P-type heavily doped region and the N-type heavily doped region in the second ion implantation layer 1411 to ensure that the ohmic contact metal filled in the first opening 1511 can form an ohmic contact between the source metal layer 16 and the second ion implantation layer 1411 .

[0164] Each junction between the P-type heavily doped region and the N-type heavily doped region in the second ion implantation layer 1411 corresponds to a first opening 1511 ; and each spacing region between the ion implantation layers 141 corresponds to a second opening 1512 .

[0165] The ohmic contact metal and / or the Schottky contact metal includes any one of nickel, titanium, a titanium-nickel alloy, and a copper-aluminum alloy.

[0166] The thickness of the ohmic contact metal and / or the Schottky contact metal is less than or equal to the thickness of the dielectric layer 15 .

[0167] In the embodiment of the present application, the thickness of the ohmic contact metal is 60nm to 200nm, and the width of the ohmic contact metal is 0.2μm to 0.5μm; the thickness of the Schottky contact metal is 0.2μm to 0.6μm, and the width of the Schottky contact metal is 0.3μm to 0.8μm. It can be understood that the width of the ohmic contact metal is equal to the width of the first opening 1511; the width of the Schottky contact metal is equal to the width of the second opening 1512.

[0168] Step S108: preparing a source metal layer on the upper surface of the dielectric layer, and preparing a drain metal layer on the lower surface of the substrate, to obtain a metal oxide semiconductor field effect transistor.

[0169] Specifically, first, a source metal layer 16 is formed on the upper surface of the dielectric layer 15 by sputtering; then, the lower surface of the substrate 12 is thinned by at least one of mechanical grinding, chemical etching, and inductively coupled plasma etching (ICP) technology to reduce the thickness of the substrate 12 to 100 μm to 150 μm, and a drain metal layer 11 is formed on the lower surface of the substrate 12 by sputtering, referring to Figure 1 .

[0170] The source metal layer 16 may include copper and / or aluminum; the thickness of the source metal layer 16 is 2 μm to 4 μm.

[0171] The drain metal layer 11 may include any one of nickel, titanium, a titanium-nickel alloy, and a copper-aluminum alloy; the thickness of the drain metal layer 11 is 0.5 μm to 1.5 μm.

[0172] It is understandable that the method for preparing the metal oxide semiconductor field effect transistor provided in the embodiment of the present application can be used to prepare the metal oxide semiconductor field effect transistor as described in any of the above items, and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0173] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0174] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A metal oxide semiconductor field effect transistor, characterized in that: The metal oxide semiconductor field effect transistor comprises a drain metal layer, a substrate, a first epitaxial layer, a second epitaxial layer, a dielectric layer and a source metal layer which are stacked in sequence; Wherein, the upper surface of the first epitaxial layer includes first buried regions arranged at intervals; The second epitaxial layer comprises an ion implantation layer, a groove region and a second buried region which are arranged at intervals; the ion implantation layer extends from the upper surface of the second epitaxial layer to the inside of the second epitaxial layer along the thickness direction of the metal oxide semiconductor field effect transistor; the groove region penetrates the ion implantation layer along the longitudinal center line of the ion implantation layer and extends to the second buried region; The trench region includes a first gate oxide layer, a first gate region, a second gate oxide layer and a second gate region; the first gate oxide layer is stacked on the inner wall of the trench region, and the first gate region, the second gate oxide layer and the second gate region are stacked in sequence on the upper surface of the first gate oxide layer along the direction from the first epitaxial layer to the second epitaxial layer to form a split gate structure; The dielectric layer includes a target opening, and the target opening is filled with a contact metal; the contact metal is used to connect the second epitaxial layer and the source metal layer.

2. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The width of the first gate region is smaller than or equal to the width of the second gate region, and the width of the first gate region and / or the second gate region is 0.5 μm to 1 μm.

3. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The thickness of the first gate region and / or the second gate region is 0.5 μm to 1.5 μm.

4. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

5. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The second gate oxide layer has a thickness of 0.05 μm to 0.12 μm.

6. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The minimum value of the angle between the sidewall of the trench region and the lower surface of the second epitaxial layer is 85° to 89°.

7. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The depth of the groove region is 2 μm to 3 μm, and the width of the groove region is 0..5 μm to 1.2 μm.

8. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The target opening includes a first opening corresponding to the ion implantation layer and a second opening corresponding to a spacing region between the ion implantation layers; The contact metal includes an ohmic contact metal and a Schottky contact metal, the first opening is filled with the ohmic contact metal, and the second opening is filled with the Schottky contact metal.

9. The metal oxide semiconductor field effect transistor according to claim 8, characterized in that: The thickness of the ohmic contact metal and / or the Schottky contact metal is less than or equal to the thickness of the dielectric layer.

10. The metal oxide semiconductor field effect transistor according to claim 8, characterized in that: The thickness of the ohmic contact metal is 60 nm to 200 nm, and the width of the ohmic contact metal is 0.2 μm to 0.5 μm.

11. The metal oxide semiconductor field effect transistor according to claim 8, characterized in that: The thickness of the Schottky contact metal is 0.2 μm to 0.6 μm, and the width of the Schottky contact metal is 0.3 μm to 0.8 μm.

12. A method for preparing a metal oxide semiconductor field effect transistor, characterized in that: The method comprises: Forming a first epitaxial layer and a second epitaxial layer stacked in sequence on the upper surface of the substrate; the upper surface of the first epitaxial layer includes first buried regions arranged at intervals; Performing a first ion implantation operation in a first target region on the upper surface of the second epitaxial layer to obtain ion implantation layers arranged at intervals; Etching the second epitaxial layer along the longitudinal center line of the ion implantation layer to obtain a target groove penetrating the ion implantation layer; performing a second ion implantation operation at the bottom of the target trench to form a second buried region in the second epitaxial layer in contact with the bottom of the target trench; A first gate oxide layer, a first gate region, a second gate oxide layer, and a second gate region are sequentially prepared in the target trench to obtain a trench region; the first gate oxide layer is stacked on an inner wall of the trench region, and the first gate region, the second gate oxide layer, and the second gate region are sequentially stacked on an upper surface of the first gate oxide layer along a direction from the first epitaxial layer to the second epitaxial layer to form a split gate structure; Prepare an original dielectric layer on the upper surface of the second epitaxial layer having the groove region; Prepare a target opening in a second target area of ​​the original dielectric layer, and fill the target opening with a contact metal to obtain a dielectric layer; A source metal layer is prepared on the upper surface of the dielectric layer, and a drain metal layer is prepared on the lower surface of the substrate to obtain the metal oxide semiconductor field effect transistor as claimed in any one of claims 1 to 11.

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