Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and aims to improve the performance of the semiconductor device and prolong the service life of the semiconductor device, the semiconductor device comprises a substrate, a barrier layer, a grid electrode, a source electrode, a drain electrode and at least two first polarization enhancement parts, the barrier layer is arranged on one side of the substrate, the grid electrode is arranged on the side, away from the substrate, of the barrier layer, the source electrode and the drain electrode are arranged on the two opposite sides of the grid electrode in the first direction, the first direction is parallel to the substrate, and the at least two first polarization enhancement parts are arranged between the grid electrode and the drain electrode and arranged on the side, away from the substrate, of the barrier layer. The at least two first polarization enhancement parts are arranged at intervals along the first direction. The semiconductor device is applied to a chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0002] Gallium nitride (GaN) semiconductor materials are called third-generation semiconductor materials. Compared with first-generation semiconductor materials represented by silicon, they have higher bandgap width, critical breakdown field strength, and electron saturation drift velocity. They have significant advantages in high frequency, high voltage resistance, high power, and low on-resistance, and can be used as core devices in various power conversion systems.

[0003] High-electron-mobility transistors (HEMTs) based on gallium nitride (GaN) are widely used as power amplifiers in electronic devices. For example, the power of the RF signal generated in the RF modulation circuit of an electronic device is very small, and it needs to go through a series of amplifications to obtain sufficient RF power before it can be fed to the antenna for radiation. In order to obtain sufficiently large RF power, an RF power amplifier must be used to amplify the power of the RF signal. RF power amplifiers are widely used in equipment in radar, wireless communication, navigation, satellite communication, electronic countermeasures and other systems, and are key components in modern wireless communications. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a chip, and an electronic device, aiming to improve the performance of the semiconductor device and increase the service life of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor device is provided. The semiconductor device includes a substrate, a barrier layer, a gate, a source, a drain, and at least two first polarization enhancement portions. The barrier layer is disposed on one side of the substrate. The gate is disposed on a side of the barrier layer away from the substrate. The source and the drain are disposed on opposite sides of the gate along a first direction, and the first direction is parallel to the substrate. At least two first polarization enhancement portions are disposed between the gate and the drain, and are disposed on a side of the barrier layer away from the substrate. At least two first polarization enhancement portions are disposed at intervals along the first direction.

[0007] The semiconductor device provided by the above-mentioned embodiment of the present disclosure includes at least two first polarization enhancement parts, and the first polarization enhancement part is arranged between the gate and the drain, and is arranged on the side of the barrier layer away from the substrate. The strong polarization effect of the first polarization enhancement part can be used to accumulate more positive polarization charges on the surface of the side of the first polarization enhancement part close to the barrier layer. On the one hand, in the case of surface defects in the barrier layer, the positive polarization charges accumulated on the surface of the side of the first polarization enhancement part close to the barrier layer can compensate for the electrons captured in the two-dimensional electron gas due to the surface defects of the barrier layer, which can avoid the two-dimensional electron gas in the semiconductor device from being depleted, which is conducive to ensuring the conductivity of the semiconductor device.

[0008] On the other hand, in the thermal equilibrium state, the positive polarization charge accumulated on the surface of the first polarization enhanced portion close to the barrier layer is beneficial to increasing the electron concentration of the two-dimensional electron gas in the semiconductor device, which in turn is beneficial to reducing the on-resistance of the semiconductor device, thereby improving the performance of the semiconductor device.

[0009] By arranging the first polarization enhancement parts in the semiconductor device at intervals along the first direction, it is beneficial to uniformize the electric field distribution in the semiconductor device, and then to achieve flattening of the electric field distribution in the semiconductor device. The peak electric field strength in the semiconductor device can be reduced, and the probability of the semiconductor device being broken down due to excessively high peak electric field strength in the semiconductor device is reduced, which is beneficial to improving the service life of the semiconductor device.

[0010] Especially when the electron concentration of the two-dimensional electron gas in the semiconductor device is high, the peak electric field strength in the semiconductor device is also high. By arranging the first polarization enhancement portion in the semiconductor device at intervals along the first direction, it is beneficial to uniformize the electric field distribution in the semiconductor device, and the peak electric field strength in the semiconductor device can be reduced, thereby reducing the probability of the semiconductor device being broken down, which is beneficial to increasing the service life of the semiconductor device.

[0011] In some embodiments, the first polarization enhanced portion is extended along a second direction, the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

[0012] In some embodiments, a size of the first polarization enhanced portion along the second direction is the same as a size of the barrier layer along the second direction.

[0013] In some embodiments, the first polarization enhancement portion includes a plurality of sub-enhancement portions, and the plurality of sub-enhancement portions are arranged at intervals along a second direction, the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

[0014] In some embodiments, the sizes of the plurality of sub-reinforcement portions along the second direction are equal, and / or, along the second direction, the intervals between any two adjacent sub-reinforcement portions are equal.

[0015] In some embodiments, at least two first polarization enhancement portions have the same size along the first direction, and / or, along the first direction, the intervals between any two adjacent first polarization enhancement portions are the same.

[0016] In some embodiments, the material of the first polarization enhanced portion includes a Group III-V compound semiconductor.

[0017] In some embodiments, a dimension of the first polarization enhanced portion along a third direction is greater than or equal to 1 nm and less than or equal to 100 nm, and the third direction is a thickness direction of the substrate.

[0018] In some embodiments, the semiconductor device further comprises a cap layer and a second polarization enhancement portion. The cap layer is disposed between the gate and the barrier layer. The second polarization enhancement portion is at least partially disposed on a side of the cap layer close to the drain electrode and covers a surface of a side of the cap layer close to the drain electrode.

[0019] In some embodiments, a material of the second polarization enhancement portion is the same as a material of the first polarization enhancement portion.

[0020] In some embodiments, the semiconductor device further comprises a cap layer and a passivation layer. The cap layer is disposed between the gate and the barrier layer. The passivation layer covers two opposite sides of the cap layer in the first direction, an area between the cap layer and the source electrode, an area between the cap layer and the drain electrode, and at least two first polarization enhancement portions.

[0021] In another aspect, a method for preparing a semiconductor device is provided. The method for preparing a semiconductor device comprises the following steps:

[0022] A barrier layer is formed on one side of the substrate.

[0023] At least two first polarization enhancement portions are formed on a side of the barrier layer away from the substrate. The at least two first polarization enhancement portions are spaced apart along a first direction, and the first direction is parallel to the substrate.

[0024] A source electrode and a drain electrode are formed. The source electrode and the drain electrode are arranged on two opposite sides of the at least two first polarization enhanced portions in the first direction.

[0025] A gate is formed between the source and the drain. At least two first polarization enhancement portions are arranged between the gate and the drain.

[0026] In some embodiments, forming at least two first polarization enhancement portions on a side of the barrier layer away from the substrate comprises the following steps:

[0027] An initial polarization enhancement layer is formed on a side of the barrier layer away from the substrate.

[0028] The initial polarization enhanced layer in a partial region is removed to form at least two first polarization enhanced portions.

[0029] In some embodiments, forming at least two first polarization enhancement portions on a side of the barrier layer away from the substrate comprises the following steps:

[0030] At least two first polarization enhancement portions are formed on a side of the barrier layer away from the substrate through an epitaxial growth process.

[0031] In another aspect, a chip is provided, wherein the chip includes the semiconductor device described in any one of the above embodiments.

[0032] In another aspect, an electronic device is provided, wherein the electronic device comprises a circuit board and the chip as described above, wherein the chip is electrically connected to the circuit board.

[0033] It can be understood that the beneficial effects that can be achieved by the semiconductor device manufacturing method, chip and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0035] Figure 1 is a schematic structural diagram of an electronic device according to some embodiments;

[0036] Figure 2 is a cross-sectional schematic diagram of a chip according to some embodiments;

[0037] Figure 3 is a schematic diagram of electric field intensity distribution in a local area of ​​a semiconductor device according to some embodiments;

[0038] Figure 4 A three-dimensional schematic diagram of a semiconductor device according to some embodiments Figure 1 ;

[0039] Figure 5 A three-dimensional schematic diagram of a semiconductor device according to some embodiments Figure 2 ;

[0040] Figure 6 A three-dimensional schematic diagram of a semiconductor device according to some embodiments Figure 3 ;

[0041] Figure 7 is a schematic cross-sectional view of a semiconductor device according to some embodiments;

[0042] Figure 8 A process for preparing a semiconductor device according to some embodiments Figure 1 ;

[0043] Fig. 9 A process for preparing a semiconductor device according to some embodiments Figure 2 ;

[0044] Fig.10 for Figure 8 and Fig. 9 A schematic structural diagram of a semiconductor device corresponding to step S1 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0045] Fig.11 for Figure 8 A schematic structural diagram of a semiconductor device corresponding to step S2 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0046] Fig.12 for Fig. 9 A schematic structural diagram of a semiconductor device corresponding to step S2 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0047] Fig.13 for Figure 8 A schematic structural diagram of a semiconductor device corresponding to step S3 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0048] Fig.14 for Fig. 9 A schematic structural diagram of a semiconductor device corresponding to step S3 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0049] Fig.15 for Figure 8 A schematic structural diagram of a semiconductor device corresponding to step S4 in the flowchart of the method for preparing a semiconductor device in FIG.

[0050] Fig.16 for Fig. 9 A schematic structural diagram of a semiconductor device corresponding to step S4 in the flowchart of the method for preparing a semiconductor device in FIG.

[0051] Fig.17 for Figure 8 and Fig. 9 A schematic structural diagram of a semiconductor device corresponding to step S5 in the flowchart of the method for preparing a semiconductor device in FIG. DETAILED DESCRIPTION

[0052] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0053] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0054] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0055] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0056] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0057] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0058] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0059] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0060] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0061] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0062] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0063] The words "exemplarily" or "for example" are used herein to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplarily" or "for example" should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a specific way.

[0064] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0065] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0066] For the convenience of the following description, an XYZ coordinate system is established. The third direction Z is the thickness direction of the substrate, the XY plane is perpendicular to the third direction Z, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0067] like Figure 1 As shown, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include communication equipment (e.g., satellite communication equipment, wireless television receiver, etc.), radar equipment (e.g., millimeter wave radar, weather radar, etc.), radio navigation equipment (e.g., GPS receiver, etc.), etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device 1000.

[0068] In some embodiments, please refer to Figure 1 , the electronic device 1000 includes a chip 100 and a circuit board 200. The chip 100 and the circuit board 200 are electrically connected.

[0069] Exemplarily, the circuit board 200 in the electronic device 1000 may include a printed circuit board (PCB) or the like.

[0070] For example, the circuit board 200 in the electronic device 1000 may include a plurality of conductive layers. The plurality of conductive layers in the circuit board 200 may be separated from each other by a dielectric layer.

[0071] The chip 100 is described in detail below.

[0072] In some embodiments, Figure 2 As shown, Figure 2 FIG. 1 is a schematic cross-sectional view of a chip 100 according to some embodiments. The chip 100 includes a semiconductor device 10 .

[0073] Exemplarily, the chip 100 may include a processor chip. For example, the processor chip may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0074] The semiconductor device 10 described above will be described in detail below.

[0075] In some embodiments, please refer to Figure 2 , a semiconductor device 10 may include a substrate 1 .

[0076] Exemplarily, the material of the substrate 1 in the semiconductor device 10 may include one of silicon (Si), silicon carbide (SiC), sapphire, and the like.

[0077] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a buffer layer 2. The buffer layer 2 may be disposed on one side of the substrate 1.

[0078] By setting a buffer layer 2 in the semiconductor device 10, and the buffer layer 2 is set on one side of the substrate 1, other film layer structures set on the side of the buffer layer 2 in the semiconductor device 10 away from the substrate 1 can be bonded, and the substrate 1 can be protected to prevent the substrate 1 from being invaded by some metal ions.

[0079] For example, the material of the buffer layer 2 in the semiconductor device 10 may include a plurality of nitride Al x In y Ga (1-x-y) At least one of N, (0≤x, y≤1).

[0080] For example, the material of the buffer layer 2 in the semiconductor device 10 may include a plurality of nitride Al x In y Ga (1-x-y) N, one of (0≤x,y≤1).

[0081] For another example, the material of the buffer layer 2 in the semiconductor device 10 may include a plurality of nitride Al x Iny Ga (1-x-y) N, where x and y satisfy 0 ≤ x, y ≤ 1, and there are multiple (greater than or equal to two) of them.

[0082] Exemplarily, the buffer layer 2 in the semiconductor device 10 can be formed by processes such as Metal-organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or Physical Vapor Deposition (PVD).

[0083] Exemplarily, the buffer layer 2 in the semiconductor device 10 can be a single-layer structure. That is, along the third direction Z (i.e., the thickness direction of the substrate 1), the buffer layer 2 includes a single layer of film structure.

[0084] Alternatively, the buffer layer 2 in the semiconductor device 10 can be a multi-layer (greater than or equal to two) structure. That is, along the third direction Z, the buffer layer 2 includes multiple layers of film structure.

[0085] In some embodiments, please continue to refer to Figure 2 , the semiconductor device 10 may further include a channel layer 3. The channel layer 3 can be disposed on one side of the substrate 1.

[0086] Exemplarily, please continue to refer to Figure 2 , in the case where the semiconductor device 10 includes the buffer layer 2, the channel layer 3 in the semiconductor device 10 can be disposed on the side of the buffer layer 2 away from the substrate 1.

[0087] Exemplarily, the material of the channel layer 3 in the semiconductor device 10 may include gallium nitride (GaN).

[0088] Exemplarily, the channel layer 3 in the semiconductor device 10 can be formed by processes such as metal-organic chemical vapor deposition process, molecular beam epitaxy process, or physical vapor deposition process.

[0089] In some embodiments, please continue to refer to Figure 2 , the semiconductor device 10 may further include a barrier layer 4. The barrier layer 4 is disposed on one side of the substrate 1 in the semiconductor device 10.

[0090] Exemplarily, the material of the barrier layer 4 in the semiconductor device 10 may include nitrides Al x In y Ga (1-x-y) N, where at least one of 0 < x ≤ 1, 0 ≤ y ≤ 1 is satisfied.

[0091] For example, the material of the barrier layer 4 in the semiconductor device 10 may include nitrides of various different components, such as Al x In y Ga (1-x-y) N, where x satisfies 0 < x ≤ 1 and y satisfies 0 ≤ y ≤ 1, or one of them.

[0092] For another example, the material of the barrier layer 4 in the semiconductor device 10 may include multiple (greater than or equal to two) nitrides of various different components, such as Al x In y Ga (1-x-y) N, where x satisfies 0 < x ≤ 1 and y satisfies 0 ≤ y ≤ 1.

[0093] Exemplarily, the barrier layer 4 in the semiconductor device 10 may be formed by processes such as metal-organic chemical vapor deposition process, molecular beam epitaxy process, or physical vapor deposition process.

[0094] Exemplarily, the barrier layer 4 in the semiconductor device 10 may have a single-layer structure. That is, along the third direction Z, the barrier layer 4 includes a single-layer film structure.

[0095] Exemplarily, please continue to refer to Figure 2 , the barrier layer 4 in the semiconductor device 10 may be disposed on a side of the channel layer 3 away from the substrate 1. That is, the channel layer 3 may be disposed between the barrier layer 4 and the substrate 1.

[0096] When the barrier layer 4 in the semiconductor device 10 is disposed on a side of the channel layer 3 away from the substrate 1, and the band gap of the material of the barrier layer 4 (for example, aluminum gallium nitride (AlGaN)) is greater than the band gap of the material of the channel layer 3 (for example, gallium nitride (GaN)), due to the difference in electron affinity and work function between the material of the barrier layer 4 and the material of the channel layer 3, a heterojunction structure will be formed at the interface between the barrier layer 4 and the channel layer 3. This heterojunction structure will cause the energy band structure of the channel layer 3 to bend, and then a potential well will be formed in the channel layer 3. To balance the charge distribution at the interface between the barrier layer 4 and the channel layer 3, electrons in the barrier layer 4 will transfer to the potential well in the channel layer 3. The potential well in the channel layer 3 can restrict the electrons, enabling the electrons to move freely only in a direction parallel to the interface between the barrier layer 4 and the channel layer 3, thereby inducing the formation of a two-dimensional electron gas (2DEG) near the interface between the barrier layer 4 and the channel layer 3, which is beneficial to improving the electron mobility and enhancing the performance of the semiconductor device 10.

[0097] The band gap refers to the fact that the energy of electrons in solids cannot take continuous values, but forms some discontinuous energy bands, where the energy difference between the conduction band and the valence band is the band gap. Specifically, for bound electrons to become free electrons or holes, they must obtain enough energy to jump from the valence band to the conduction band, and the minimum value of this energy is the band gap.

[0098] For example, please refer to Figure 2 When a two-dimensional electron gas is formed in the semiconductor device 10 , the semiconductor device 10 can be used to form a high electron mobility transistor (HEMT).

[0099] For example, when a two-dimensional electron gas is formed in the semiconductor device 10 , the semiconductor device 10 can be used to form a Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT).

[0100] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a cap layer 5. The cap layer 5 may be disposed on a side of the barrier layer 4 in the semiconductor device 10 away from the substrate 1. The cap layer 5 includes a P-type doped semiconductor material.

[0101] By making the semiconductor device 10 include a cap layer 5, the cap layer 5 is arranged on the side of the barrier layer 4 in the semiconductor device 10 away from the substrate 1, and the cap layer 5 includes a P-type doped semiconductor material. On the one hand, an energy band difference (for example, a conduction band difference) can be made between the cap layer 5 and the barrier layer 4, and the energy band difference between the cap layer 5 and the barrier layer 4 can be used to regulate the two-dimensional electron gas near the connection interface between the barrier layer 4 and the channel layer 3, which is beneficial to depleting the two-dimensional electron gas below the cap layer 5, so that the semiconductor device 10 can achieve an enhanced operating mode.

[0102] On the other hand, due to the depletion effect of the cap layer 5 in the semiconductor device 10 on the two-dimensional electron gas located below the cap layer 5 , the semiconductor device 10 needs to overcome a higher potential barrier when turned on, which is beneficial to improving the threshold voltage of the semiconductor device 10 .

[0103] For example, the material of the cap layer 5 in the semiconductor device 10 may include p-type gallium nitride (p-GaN). P-type gallium nitride (p-GaN) may be formed by doping gallium nitride (GaN) material with elements such as iron (Fe) and magnesium (Mg).

[0104] For example, when doping elements such as iron (Fe) and magnesium (Mg) into gallium nitride (GaN) material to form p-type gallium nitride (p-GaN), a gas-phase doping process or an ion implantation process may be used.

[0105] In the process of forming the cap layer 5 within the semiconductor device 10, by doping a P-type material (e.g., magnesium (Mg)) as an impurity into a semiconductor material (e.g., gallium nitride (GaN)), the cap layer 5 can provide hole carriers, thereby adjusting the conductivity of the cap layer 5.

[0106] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a gate G. The gate G may be disposed on a side of the barrier layer 4 in the semiconductor device 10 away from the substrate 1 .

[0107] The gate G in the semiconductor device 10 is a key electrode for controlling the conductivity of the semiconductor device 10 . The gate G does not directly participate in the conduction of current, but controls the carrier concentration in the channel layer 3 in the semiconductor device 10 through the electric field effect, thereby controlling the current in the semiconductor device 10 .

[0108] For example, please refer to Figure 2 In the case where the semiconductor device 10 includes the cap layer 5 , the gate G may be disposed on a side of the cap layer 5 away from the substrate 1 . That is, the cap layer 5 may be disposed between the gate G and the barrier layer 4 .

[0109] By way of example, the material of the gate G in the semiconductor device 10 may include at least one of conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

[0110] For example, the material of the gate G in the semiconductor device 10 may include one of conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

[0111] For another example, the material of the gate G in the semiconductor device 10 may include multiple (greater than or equal to two) conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

[0112] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a source S and a drain D. The source S and the drain D are disposed on opposite sides of the gate G in the semiconductor device 10 along a first direction X, and the first direction X is parallel to the substrate 1 in the semiconductor device 10 .

[0113] For example, please refer to Figure 2 When a two-dimensional electron gas is formed in the semiconductor device 10, the source S and the drain D in the semiconductor device 10 can form an ohmic contact with the two-dimensional electron gas, which can reduce the contact resistance between the source S in the semiconductor device 10 and the two-dimensional electron gas, and the contact resistance between the drain D in the semiconductor device 10 and the two-dimensional electron gas. A low-impedance current channel can be formed between the source S, the drain D and the two-dimensional electron gas in the semiconductor device 10, so that the current can flow smoothly, which is beneficial to improving the performance of the semiconductor device 10.

[0114] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include at least two first polarization enhancement portions 61. The first polarization enhancement portion 61 is disposed between the gate G and the drain D, and is disposed on a side of the barrier layer 4 away from the substrate 1. The at least two first polarization enhancement portions 61 are spaced apart along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10).

[0115] By making the semiconductor device 10 include at least two first polarization enhancement portions 61, the first polarization enhancement portion 61 is arranged between the gate G and the drain D, and is arranged on the side of the barrier layer 4 away from the substrate 1, the strong polarization effect of the first polarization enhancement portion 61 can be used to make the side surface 61a of the first polarization enhancement portion 61 close to the barrier layer 4 accumulate more positive polarization charges. On the one hand, in the case of surface defects in the barrier layer 4, the positive polarization charges accumulated on the side surface 61a of the first polarization enhancement portion 61 close to the barrier layer 4 can compensate for the electrons captured in the two-dimensional electron gas due to the surface defects of the barrier layer 4, which can avoid the two-dimensional electron gas in the semiconductor device 10 from being depleted, which is conducive to ensuring the conductivity of the semiconductor device 10.

[0116] On the other hand, in the thermal equilibrium state, the positive polarization charge accumulated on the side surface 61a of the first polarization enhanced portion 61 close to the barrier layer 4 is beneficial to increasing the electron concentration of the two-dimensional electron gas in the semiconductor device 10, and then is beneficial to reducing the on-resistance of the semiconductor device 10, thereby helping to improve the performance of the semiconductor device 10.

[0117] like Figure 3 As shown, Figure 3Schematic diagram of the electric field intensity distribution in a local area of ​​the semiconductor device 10 according to some embodiments. By arranging the first polarization enhancement portions 61 in the semiconductor device 10 at intervals along the first direction X, it is possible to avoid the electric field being concentrated on the side of the gate G close to the drain D, which is conducive to the uniformity of the electric field distribution in the semiconductor device 10, and further conducive to the flattening of the electric field distribution in the semiconductor device 10, which can reduce the peak electric field intensity in the semiconductor device 10, reduce the probability of the semiconductor device 10 being broken down due to the excessively high peak electric field intensity in the semiconductor device 10, and help to increase the service life of the semiconductor device 10.

[0118] In particular, when the electron concentration of the two-dimensional electron gas in the semiconductor device 10 is high, the peak electric field strength in the semiconductor device 10 is also high. By arranging the first polarization enhancement portions 61 in the semiconductor device 10 at intervals along the first direction X, it is beneficial to uniformize the electric field distribution in the semiconductor device 10, and the peak electric field strength in the semiconductor device 10 can be reduced, thereby reducing the probability of the semiconductor device 10 being broken down, which is beneficial to improving the service life of the semiconductor device 10.

[0119] Exemplarily, the material of the first polarization enhanced portion 61 may include a group III-V compound semiconductor.

[0120] For example, the material of the first polarization enhancing portion 61 may include one or more of aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), and the like.

[0121] The band gap of III-V compound semiconductors (e.g., aluminum nitride (AlN)) is wide, and can absorb higher energy radiation without generating charge carriers. By making the material of the first polarization enhancement portion 61 include a III-V compound semiconductor, the first polarization enhancement portion 61 can effectively block or absorb most of the radiation in a space radiation environment, thereby reducing the influence of radiation on other film layers located below the first polarization enhancement portion 61 in the semiconductor device 10, thereby reducing the probability of performance degradation of the semiconductor device 10 due to radiation, which is beneficial to improving the reliability of the semiconductor device 10.

[0122] Exemplarily, the first polarization enhanced portion 61 may be formed by an atomic layer deposition (ALD) process, a molecular beam epitaxy process, or a metal organic chemical vapor deposition process.

[0123] For example, the first polarization enhanced portion 61 may be formed by depositing aluminum nitride (AlN) through an atomic layer deposition process.

[0124] For another example, the first polarization enhanced portion 61 may be formed by depositing aluminum gallium nitride (AlGaN) and / or aluminum indium nitride (AlInN) by a molecular beam epitaxy process or a metal organic chemical vapor deposition process.

[0125] For example, please refer to Figure 2 , a dimension h61 of the first polarization enhanced portion 61 along the third direction Z may be greater than or equal to 1 nm and less than or equal to 100 nm.

[0126] For example, see Figure 2 , a dimension h61 of the first polarization enhanced portion 61 along the third direction Z may be 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, etc.

[0127] For example, please refer to Figure 2 , the sizes L61 of at least two first polarization enhancement portions 61 along the first direction X are equal.

[0128] By making the dimensions L61 of at least two first polarization enhancement portions 61 in the semiconductor device 10 equal along the first direction X, it is beneficial to make the electric field distribution in the semiconductor device 10 more uniform, which is beneficial to further realize the flattening of the electric field distribution in the semiconductor device 10, and can reduce the peak electric field strength in the semiconductor device 10, reduce the probability of the semiconductor device 10 being broken down due to the excessively high peak electric field strength in the semiconductor device 10, and help to improve the service life of the semiconductor device 10.

[0129] The above “at least two first polarization enhancement portions 61 have the same size L61 along the first direction X” means that the difference between the sizes L61 of at least two first polarization enhancement portions 61 along the first direction X is within a preset threshold range. The threshold range is a relatively small numerical range, for example, the threshold range may be a process accuracy range when forming at least two first polarization enhancement portions 61 having the same size along the first direction X.

[0130] In the case where the sizes L61 of at least two first polarization enhanced portions 61 in the semiconductor device 10 along the first direction X are equal, the threshold range of the difference between the sizes L61 of at least two first polarization enhanced portions 61 along the first direction X may be 0-2 μm.

[0131] For example, the difference between the dimensions L61 of at least two first polarization enhanced portions 61 in the semiconductor device 10 along the first direction X may be 0, 0.1 μm, 0.3 μm, 0.6 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.6 μm, 1.8 μm or 2 μm, etc.

[0132] For example, please refer to Figure 2 Along the first direction X, the distance d61 between any two adjacent first polarization enhancement portions 61 may be equal.

[0133] Along the first direction X, by making the distance d61 between any two adjacent first polarization enhancement portions 61 in the semiconductor device 10 equal, it is beneficial to make the electric field distribution in the semiconductor device 10 more uniform, and thus it is beneficial to further realize the flattening of the electric field distribution in the semiconductor device 10, which can reduce the peak electric field strength in the semiconductor device 10, and reduce the probability of the semiconductor device 10 being broken down due to the excessively high peak electric field strength in the semiconductor device 10, which is beneficial to improve the service life of the semiconductor device 10.

[0134] The equal spacing d61 between any two adjacent first polarization enhanced portions 61 along the first direction X means that the difference between the spacing d61 between any two adjacent first polarization enhanced portions 61 along the first direction X is within a preset threshold range. The threshold range is a relatively small numerical range, for example, the threshold range may be a process accuracy range when forming a plurality of first polarization enhanced portions 61 with the same spacing d61 between any two adjacent first polarization enhanced portions 61 along the first direction X.

[0135] When the intervals d61 between any two adjacent first polarization enhancement portions 61 along the first direction X are equal, the threshold range of the difference between the intervals d61 between any two adjacent first polarization enhancement portions 61 along the first direction X may be 0-2 μm.

[0136] For example, along the first direction X, the difference between the interval d61 between any two adjacent first polarization enhancement portions 61 may be 0, 0.1 μm, 0.3 μm, 0.6 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.6 μm, 1.8 μm or 2 μm, etc.

[0137] For example, please refer to Figure 2 Along the first direction X, the interval J1 between the first polarization enhanced portion 61 closest to the gate G in the first polarization enhanced portion 61 in the semiconductor device 10 and the gate G may be 0-2 μm.

[0138] For example, see Figure 2 Along the first direction X, the spacing J1 between the first polarization enhanced portion 61 closest to the gate G in the first polarization enhanced portion 61 in the semiconductor device 10 and the gate G can be 0, 0.3μm, 0.6μm, 0.8μm, 1μm, 1.2μm, 1.5μm, 1.8μm or 2μm, etc.

[0139] In some embodiments, Figure 4 As shown, Figure 4 1 is a schematic three-dimensional diagram of a semiconductor device 10 according to some embodiments. The first polarization enhanced portion 61 is extended along a second direction Y, the second direction Y is perpendicular to the first direction X, and the second direction Y is parallel to the substrate 1 .

[0140] The second direction Y being perpendicular to the first direction X means that the difference between the angle between the second direction Y and the first direction X and 90° is within a preset threshold range. The threshold range is a relatively small numerical range, for example, the threshold range may be 0-6°.

[0141] For example, please refer to Figure 4 The dimension K61 of the first polarization enhancement portion 61 along the second direction Y may be the same as the dimension K4 of the barrier layer 4 along the second direction Y.

[0142] By making the dimension K61 of the first polarization enhancement portion 61 in the semiconductor device 10 along the second direction Y the same as the dimension K4 of the barrier layer 4 along the second direction Y, so that the dimension K61 of the first polarization enhancement portion 61 along the second direction Y is larger, the strong polarization effect of the first polarization enhancement portion 61 can be further utilized to accumulate more positive polarization charges on the side surface 61a of the first polarization enhancement portion 61 close to the barrier layer 4. On the one hand, in the case where the barrier layer 4 has surface defects, the positive polarization charges accumulated on the side surface 61a of the first polarization enhancement portion 61 close to the barrier layer 4 can further compensate for the electrons captured in the two-dimensional electron gas due to the surface defects of the barrier layer 4, so that the two-dimensional electron gas in the semiconductor device 10 can be prevented from being depleted, which is conducive to ensuring the conductivity of the semiconductor device 10.

[0143] On the other hand, in the thermal equilibrium state, the positive polarization charge accumulated on the side surface 61a of the first polarization enhancement portion 61 close to the barrier layer 4 is conducive to further increasing the electron concentration of the two-dimensional electron gas in the semiconductor device 10, which in turn is conducive to further reducing the on-resistance of the semiconductor device 10, thereby helping to further improve the performance of the semiconductor device 10.

[0144] The dimension K61 of the first polarization enhanced portion 61 along the second direction Y can be the same as the dimension K4 of the barrier layer 4 along the second direction Y, which means that the difference between the dimension K61 of the first polarization enhanced portion 61 along the second direction Y and the dimension K4 of the barrier layer 4 along the second direction Y is within a preset threshold range. The threshold range is a relatively small numerical range, for example, the threshold range can be a process accuracy range when forming the first polarization enhanced portion 61 and the barrier layer 4 with the same dimension along the second direction Y.

[0145] When the dimension K61 of the first polarization enhancement portion 61 along the second direction Y is the same as the dimension K4 of the barrier layer 4 along the second direction Y, the threshold range of the difference between the dimension K61 of the first polarization enhancement portion 61 along the second direction Y and the dimension K4 of the barrier layer 4 along the second direction Y can be 0-2 μm.

[0146] In other embodiments, Figure 5 As shown, Figure 5 1 is a perspective schematic diagram of a semiconductor device 10 according to some embodiments. The first polarization enhancement portion 61 includes a plurality of sub-enhancement portions 611. The plurality of sub-enhancement portions 611 are arranged at intervals along a second direction Y, the second direction Y is perpendicular to the first direction X, and the second direction Y is parallel to the substrate 1.

[0147] By making the first polarization enhancement portion 61 in the semiconductor device 10 include multiple sub-enhancement portions 611, and the multiple sub-enhancement portions 611 are arranged at intervals along the second direction Y, it is beneficial to further make the electric field distribution in the semiconductor device 10 uniform, and thus it is beneficial to further achieve the flattening of the electric field distribution in the semiconductor device 10, which can further reduce the peak electric field strength in the semiconductor device 10, and further reduce the probability of the semiconductor device 10 being broken down due to the excessively high peak electric field strength in the semiconductor device 10, which is beneficial to further improve the service life of the semiconductor device 10.

[0148] For example, please refer to Figure 5 , the sizes K611 of the multiple sub-enhancement parts 611 in the first polarization enhancement part 61 along the second direction Y can be equal.

[0149] By making the dimensions K611 of the multiple sub-enhancement parts 611 in the first polarization enhancement part 61 equal along the second direction Y, it is beneficial to further uniformize the electric field distribution in the semiconductor device 10, and thus to further achieve the flattening of the electric field distribution in the semiconductor device 10, which can further reduce the peak electric field strength in the semiconductor device 10, and further reduce the probability of the semiconductor device 10 being broken down due to the excessively high peak electric field strength in the semiconductor device 10, which is beneficial to further improve the service life of the semiconductor device 10.

[0150] For example, please refer to Figure 5 , along the second direction Y, the distance d611 between any two adjacent sub-reinforcement parts 611 can be equal.

[0151] Along the second direction Y, by making the distance d611 between any two adjacent sub-enhancement parts 611 equal, it is beneficial to further uniformize the electric field distribution in the semiconductor device 10, and thus to further achieve the flattening of the electric field distribution in the semiconductor device 10, which can further reduce the peak electric field strength in the semiconductor device 10, and further reduce the probability of the semiconductor device 10 being broken down due to the excessively high peak electric field strength in the semiconductor device 10, which is beneficial to further improve the service life of the semiconductor device 10.

[0152] For example, please refer to Figure 5 , the dimensions L611 of at least two sub-reinforcement portions 611 along the first direction X may be equal.

[0153] For example, please refer to Figure 5 , along the first direction X, the distance d612 between any two adjacent sub-reinforcement parts 611 may be equal.

[0154] In some other embodiments, Figure 6 As shown, Figure 6 FIG. 1 is a perspective schematic diagram of a semiconductor device 10 according to some embodiments. In the first polarization enhancement portion 61 in the semiconductor device 10, part of the first polarization enhancement portion 61 may be extended along the second direction Y, and part of the first polarization enhancement portion 61 may include a plurality of sub-enhancement portions 611, and the plurality of sub-enhancement portions 611 are spaced apart along the second direction Y.

[0155] In some embodiments, please refer to Figure 2 , Figure 4 , Figure 5 and Figure 6 The semiconductor device 10 may further include a second polarization enhancement portion 62. The second polarization enhancement portion 62 is at least partially disposed on a side of the cap layer 5 close to the drain electrode D, and covers a surface of the cap layer 5 close to the drain electrode D.

[0156] For example, please refer to Figure 2 , Figure 4 , Figure 5 and Figure 6 The second polarization enhanced portion 62 may also cover a portion of the surface of the cap layer 5 that is away from the substrate 1 .

[0157] For example, please refer to Figure 2 , Figure 4 , Figure 5 and Figure 6 , the material of the second polarization enhancing portion 62 can be the same as the material of the first polarization enhancing portion 61.

[0158] In some embodiments, please refer to Figure 2 , Figure 4 , Figure 5 and Figure 6 The semiconductor device 10 may further include a third polarization enhancement portion 63. The third polarization enhancement portion 62 may cover a region between the cap layer 5 and the source S.

[0159] For example, please refer to Figure 2 , Figure 4 , Figure 5 and Figure 6 The third polarization enhanced portion 63 may also cover a surface of one side of the cap layer 5 close to the source S, and a portion of a surface of the side of the cap layer 5 away from the substrate 1 .

[0160] For example, please refer to Figure 2 , Figure 4 , Figure 5 and Figure 6 , the material of the third polarization enhancing portion 63 can be the same as the material of the first polarization enhancing portion 61.

[0161] In some embodiments, Figure 7 As shown, Figure 7 is a cross-sectional schematic diagram of a semiconductor device 10 according to some embodiments. The semiconductor device 10 may further include a passivation layer 7. The passivation layer 7 may cover two opposite side surfaces of the cap layer 5 in the first direction X, a region between the cap layer 5 and the source S, a region between the cap layer 5 and the drain D, and at least two first polarization enhancement portions 61.

[0162] By setting a passivation layer 7 in the semiconductor device 10, and the passivation layer 7 covers two opposite sides of the cap layer 5 in the first direction X, the area between the cap layer 5 and the source S, the area between the cap layer 5 and the drain D, and at least two first polarization enhancement portions 61, on the one hand, the passivation layer 7 can block harmful substances in the external environment (for example, oxygen, water, etc.), which is beneficial to improving the stability of the semiconductor device 10 and extending the service life of the semiconductor device 10.

[0163] On the other hand, the passivation layer 7 has a certain mechanical strength, and can protect the semiconductor device 10 to a certain extent, which is beneficial to further improve the stability of the semiconductor device 10 and further extend the service life of the semiconductor device 10 .

[0164] For example, the material of the passivation layer 7 in the semiconductor device 10 may include silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ) and aluminum oxide (Al 2 O 3 ) etc.

[0165] The method for manufacturing the semiconductor device 10 is described in detail below.

[0166] In some embodiments, Figure 8 and Fig. 9 As shown, Figure 8 and Fig. 9 1 and 2 are flowcharts of methods for manufacturing a semiconductor device 10 according to some embodiments. It should be noted that: Figure 8 and Fig. 9 The method for preparing the semiconductor device 10 shown in FIG. 1 is not exclusive and may also be Figure 8 and Fig. 9 Other steps are performed before, after or between any steps in the method for manufacturing the semiconductor device 10. The method for manufacturing the semiconductor device 10 includes steps S1 to S4.

[0167] S1: Fig.10 As shown, Fig.10 for Figure 8 and Fig. 9 A schematic structural diagram of the semiconductor device 10 corresponding to step S1 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0168] S2: Fig.11 and Fig.12 As shown, Fig.11 for Figure 8 A schematic structural diagram of the semiconductor device 10 corresponding to step S2 in the flowchart of the method for preparing the semiconductor device 10 in FIG. Fig.12 for Fig. 9 A schematic structural diagram of the semiconductor device 10 corresponding to step S2 in the flowchart of the method for preparing the semiconductor device 10 in FIG. At least two first polarization enhancement portions 61 are formed on a side of the barrier layer 4 away from the substrate 1. The at least two first polarization enhancement portions 61 are arranged at intervals along a first direction X, and the first direction X is parallel to the substrate 1.

[0169] For example, please refer to Figure 8 , step S2 (ie, forming at least two first polarization enhanced portions 61 on a side of the barrier layer 4 away from the substrate 1 ) in the method for preparing the semiconductor device 10 may include step S21 and step S22 .

[0170] S21: Please continue reading Fig.11 , an initial polarization enhanced layer 6 is formed on the side of the barrier layer 4 away from the substrate 1 .

[0171] S22: Please continue reading Fig.11 , removing the initial polarization enhancement layer 6 in a partial area to form at least two first polarization enhancement portions 61.

[0172] For example, the initial polarization enhanced layer 6 in a partial region may be removed by an inductively coupled plasma reactive ion etching (ICP-RIE) process to form at least two first polarization enhanced portions 61 .

[0173] For example, please refer to Fig. 9 , step S2 (ie, forming at least two first polarization enhanced portions 61 on a side of the barrier layer 4 away from the substrate 1 ) in the method for preparing the semiconductor device 10 may also include step S23 .

[0174] S23: Please continue reading Fig.12 At least two first polarization enhancement portions 61 are formed on a side of the barrier layer 4 away from the substrate 1 through an epitaxial growth process.

[0175] For example, at least two first polarization enhanced portions 61 may be formed on a side of the barrier layer 4 away from the substrate 1 by a secondary epitaxial growth process.

[0176] When at least two first polarization enhanced portions 61 are formed on the side of the barrier layer 4 away from the substrate 1 by an epitaxial growth process, the growth mode is relatively gentle, which can avoid damaging other film structures (eg, the barrier layer 4) in the semiconductor device 10 .

[0177] S3: Fig.13 and Fig.14 As shown, Fig.13 for Figure 8 A schematic structural diagram of the semiconductor device 10 corresponding to step S3 in the flowchart of the method for preparing the semiconductor device 10 in FIG. Fig.14 for Fig. 9 The structure diagram of the semiconductor device 10 corresponding to step S3 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A source S and a drain D are formed. The source S and the drain D are arranged on opposite sides of at least two first polarization enhanced portions 61 in the first direction X.

[0178] S4: Fig.15 and Fig.16 As shown, Fig.15 for Figure 8 A schematic structural diagram of the semiconductor device 10 corresponding to step S4 in the flowchart of the method for preparing the semiconductor device 10 in FIG. Fig.16 for Fig. 9 A schematic structural diagram of the semiconductor device 10 corresponding to step S4 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A gate G is formed between the source S and the drain D. At least two first polarization enhancement portions 61 are disposed between the gate G and the drain D.

[0179] By forming at least two first polarization enhancement portions 61 in the semiconductor device 10, the first polarization enhancement portion 61 is disposed between the gate G and the drain D, and disposed on the side of the barrier layer 4 away from the substrate 1, the strong polarization effect of the first polarization enhancement portion 61 can be utilized to make the side surface 61a of the first polarization enhancement portion 61 close to the barrier layer 4 accumulate more positive polarization charges. On the one hand, in the case where the barrier layer 4 has surface defects, the positive polarization charges accumulated on the side surface 61a of the first polarization enhancement portion 61 close to the barrier layer 4 can compensate for the electrons captured in the two-dimensional electron gas due to the surface defects of the barrier layer 4, which can prevent the two-dimensional electron gas in the semiconductor device 10 from being depleted, which is conducive to ensuring the conductivity of the semiconductor device 10.

[0180] On the other hand, in the thermal equilibrium state, the positive polarization charge accumulated on the side surface 61a of the first polarization enhanced portion 61 close to the barrier layer 4 is beneficial to increasing the electron concentration of the two-dimensional electron gas in the semiconductor device 10, and then is beneficial to reducing the on-resistance of the semiconductor device 10, thereby helping to improve the performance of the semiconductor device 10.

[0181] By arranging the first polarization enhancement portions 61 in the semiconductor device 10 at intervals along the first direction X, it is possible to avoid the electric field being concentrated on the side of the gate G close to the drain D, which is beneficial to uniformizing the electric field distribution in the semiconductor device 10, and further beneficial to achieving flattening of the electric field distribution in the semiconductor device 10. It is possible to reduce the peak electric field strength in the semiconductor device 10, reduce the probability of the semiconductor device 10 being broken down due to excessively high peak electric field strength in the semiconductor device 10, and help to increase the service life of the semiconductor device 10.

[0182] In particular, when the electron concentration of the two-dimensional electron gas in the semiconductor device 10 is high, the peak electric field strength in the semiconductor device 10 is also high. By arranging the first polarization enhancement portions 61 in the semiconductor device 10 at intervals along the first direction X, it is beneficial to uniformize the electric field distribution in the semiconductor device 10, and the peak electric field strength in the semiconductor device 10 can be reduced, thereby reducing the probability of the semiconductor device 10 being broken down, which is beneficial to improving the service life of the semiconductor device 10.

[0183] In some embodiments, please refer to Figure 8 and Fig. 9 In the method for preparing the semiconductor device 10, between step S1 (i.e., forming a barrier layer 4 on one side of the substrate 1) and step S2 (i.e., forming at least two first polarization enhanced portions 61 on the side of the barrier layer 4 away from the substrate 1), the method for preparing the semiconductor device 10 may further include step S5.

[0184] S5: Fig.17 As shown, Fig.17 for Figure 8 and Fig. 9 A schematic structural diagram of the semiconductor device 10 corresponding to step S5 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0185] For example, please refer to Figure 8 and Fig. 9 , step S5 (ie, forming a cap layer 5 on a side of the barrier layer 4 away from the substrate 1 ) in the method for preparing the semiconductor device 10 may include step S51 and step S52 .

[0186] S51: Please continue reading Fig.17 , an initial capping layer 5 a is formed on the side of the barrier layer 4 away from the substrate 1 .

[0187] S52: Please continue reading Fig.17 , remove the initial capping layer 5a in a partial area to form a capping layer 5.

[0188] For example, the initial cap layer 5 a may be formed on the side of the barrier layer 4 away from the substrate 1 by a Metal-organic Chemical Vapor Deposition (MOCVD) process.

[0189] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A barrier layer, disposed on one side of the substrate; A gate, disposed on a side of the barrier layer away from the substrate; A source electrode and a drain electrode are arranged on opposite sides of the gate electrode along a first direction; the first direction is parallel to the substrate; At least two first polarization enhancement portions are arranged between the gate and the drain and on a side of the barrier layer away from the substrate; the at least two first polarization enhancement portions are arranged at intervals along the first direction.

2. The semiconductor device according to claim 1, wherein: The first polarization enhancement portion is extended along a second direction; the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

3. The semiconductor device according to claim 2, characterized in that A size of the first polarization enhanced portion along the second direction is the same as a size of the barrier layer along the second direction.

4. The semiconductor device according to claim 1, wherein: The first polarization enhancement portion includes a plurality of sub-enhancement portions, and the plurality of sub-enhancement portions are arranged at intervals along a second direction; the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

5. The semiconductor device according to claim 4, characterized in that The sizes of the plurality of sub-reinforcement parts along the second direction are equal; and / or, Along the second direction, the distances between any two adjacent sub-reinforcement parts are equal.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The at least two first polarization enhancement portions have the same size along the first direction; and / or, Along the first direction, the intervals between any two adjacent first polarization enhancement portions are equal.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that: The material of the first polarization enhancement portion includes a Group III-V compound semiconductor.

8. The semiconductor device according to any one of claims 1 to 5, characterized in that: A dimension of the first polarization enhanced portion along a third direction is greater than or equal to 1 nm and less than or equal to 100 nm; the third direction is a thickness direction of the substrate.

9. The semiconductor device according to any one of claims 1 to 5, characterized in that: The semiconductor device further comprises: A cap layer, disposed between the gate and the barrier layer; The second polarization enhancement portion is at least partially disposed on a side of the cap layer close to the drain electrode, and covers a surface of the cap layer close to the drain electrode.

10. The semiconductor device according to claim 9, characterized in that A material of the second polarization enhancing portion is the same as a material of the first polarization enhancing portion.

11. The semiconductor device according to any one of claims 1 to 5, characterized in that: The semiconductor device further comprises: A cap layer, disposed between the gate and the barrier layer; A passivation layer covers two opposite side surfaces of the cap layer in the first direction, a region between the cap layer and the source electrode, a region between the cap layer and the drain electrode, and the at least two first polarization enhancement portions.

12. A method for preparing a semiconductor device, characterized in that: include: forming a barrier layer on one side of the substrate; At least two first polarization enhancement portions are formed on a side of the barrier layer away from the substrate; the at least two first polarization enhancement portions are arranged at intervals along a first direction, and the first direction is parallel to the substrate; forming a source and a drain; The source electrode and the drain electrode are arranged on two opposite sides of the at least two first polarization enhanced portions in the first direction; A gate is formed between the source and the drain; and the at least two first polarization enhanced portions are disposed between the gate and the drain.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: The step of forming at least two first polarization enhancement portions on a side of the barrier layer away from the substrate comprises: forming an initial polarization enhancement layer on a side of the barrier layer away from the substrate; The initial polarization enhanced layer is removed from a partial region to form the at least two first polarization enhanced portions.

14. The method for preparing a semiconductor device according to claim 12, characterized in that: The step of forming at least two first polarization enhancement portions on a side of the barrier layer away from the substrate comprises: The at least two first polarization enhanced portions are formed on a side of the barrier layer away from the substrate by an epitaxial growth process.

15. A chip, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 11.

16. An electronic device, characterized in that: include: Circuit boards; The chip as claimed in claim 15, wherein the chip is electrically connected to the circuit board.

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