Medium voltage device and forming method thereof

Abstract

The invention provides a medium-voltage device and a forming method thereof, and the method comprises the steps: forming a first gate oxide layer through employing an ISSG technology, and enabling the first gate oxide layer to cover a substrate; and then a second gate oxide layer is formed by adopting an ALD process, the second gate oxide layer covers the first gate oxide layer and the shallow trench isolation structure, and the first gate oxide layer and the second gate oxide layer jointly form a gate oxide layer. According to the invention, the surface defects of the substrate can be repaired while the first gate oxide layer is formed by adopting the ISSG process; the sum of the thickness of the first gate oxide layer formed by the ISSG process and the thickness of the second gate oxide layer formed by the ALD process can reach the target thickness of the gate oxide layer, and the defect that the target thickness of the gate oxide layer cannot be achieved through one-step growth in the ISSG process is overcome. And the second gate oxide layer formed by adopting the ALD process is relatively good in uniformity and compactness and low in thermal budget, the thickness of the second gate oxide layer is relatively accurately controlled, and the reliability of the medium-voltage device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a medium voltage device and a forming method thereof. Background Art

[0002] With the continuous development of Moore's Law, semiconductor process technology is moving towards smaller process nodes, integrated circuits are becoming more and more complex, smaller in size, and more highly integrated, which places higher requirements on device performance.

[0003] Among the existing process technology nodes, medium voltage devices have a higher withstand voltage, and the gate oxide thickness requirement of the medium voltage device area is also relatively thick. Taking the 40-nanometer node HV (High Voltage) process platform or the 55-nanometer HV process platform as an example, the gate oxide thickness in the medium voltage device is usually between 170 angstroms and 250 angstroms. The traditional ISSG (In-situ Steam Generation) process cannot grow a gate oxide layer greater than 150 angstroms in one step. The existing technology mainly adopts the ISSG process to first grow a gate oxide layer of a certain thickness, and then adopts the HTO (High Temperature Oxidation) process to grow the gate oxide layer to the target thickness. However, since the thickness uniformity of the gate oxide layer grown by the HTO process is difficult to control, and the HTO process is a high-temperature process, the growth time is long, and the thermal budget is high, all of which lead to the poor reliability of the medium voltage device. Summary of the invention

[0004] The object of the present invention is to provide a medium voltage device and a method for forming the same, so as to solve at least one problem that the gate oxide layer in the medium voltage device cannot reach the target thickness in one step by using the ISSG process or that the reliability of the medium voltage device is poor by combining the ISSG process with the HTO process.

[0005] In order to solve the above technical problems, the present invention provides a method for forming a medium voltage device, comprising:

[0006] Providing a substrate, wherein a shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure is used to define a medium voltage device area;

[0007] Forming a first gate oxide layer by adopting an ISSG process, wherein the first gate oxide layer covers the substrate;

[0008] A second gate oxide layer is formed by adopting the ALD process, the second gate oxide layer covers the first gate oxide layer and the shallow trench isolation structure, and the first gate oxide layer and the second gate oxide layer together constitute the gate oxide layer of the medium voltage device area.

[0009] Optionally, the first gate oxide layer has a thickness of 50 angstroms to 150 angstroms.

[0010] Optionally, the second gate oxide layer has a thickness of 30 angstroms to 200 angstroms.

[0011] Optionally, the thickness of the gate oxide layer in the medium voltage device region is greater than 170 angstroms.

[0012] Optionally, the process temperature of the ISSG process is 700°C to 1100°C.

[0013] Optionally, the process temperature of the ALD process is 300°C to 700°C.

[0014] Optionally, the substrate further includes a low voltage device region and a high voltage device region, and the shallow trench isolation structure is used to isolate the low voltage device region, the medium voltage device region and the high voltage device region.

[0015] Optionally, before forming the gate oxide layer of the medium voltage device area, a gate oxide layer has been formed on the high voltage device area, and after forming the gate oxide layer of the medium voltage device area, the method includes:

[0016] forming a gate oxide layer in a low voltage device region, wherein the gate oxide layer covers a substrate in the low voltage device region;

[0017] Forming a gate material layer, wherein the gate material layer covers the gate oxide layers of the high voltage device region, the medium voltage device region and the low voltage device region;

[0018] A photolithography and etching process is performed to etch a portion of the gate material layer, and the remaining portion of the gate material layer forms a gate structure.

[0019] Based on the same inventive concept, the present invention further provides a medium voltage device, which is manufactured by using any of the above-mentioned methods for forming a medium voltage device, comprising:

[0020] A substrate having a shallow trench isolation structure formed therein, wherein the shallow trench isolation structure is used to define a medium voltage device area;

[0021] a first gate oxide layer, wherein the first gate oxide layer covers the substrate;

[0022] A second gate oxide layer, wherein the second gate oxide layer covers the first gate oxide layer and the shallow trench isolation structure, and the first gate oxide layer and the second gate oxide layer together constitute a gate oxide layer of the medium voltage device region.

[0023] Optionally, the thickness of the gate oxide layer in the medium voltage device region is greater than 170 angstroms.

[0024] In a method for forming a medium voltage device provided by the present invention, a first gate oxide layer is first formed by using an ISSG process, and the first gate oxide layer covers the substrate; then a second gate oxide layer is formed by using an ALD process, and the second gate oxide layer covers the first gate oxide layer and the shallow trench isolation structure, and the first gate oxide layer and the second gate oxide layer together constitute the gate oxide layer of the medium voltage device region. The present invention can repair the surface defects of the substrate while using the ISSG process to form the first gate oxide layer; and the sum of the thickness of the first gate oxide layer formed by the ISSG process and the second gate oxide layer formed by the ALD process can reach the target thickness of the gate oxide layer, which overcomes the disadvantage that the ISSG process cannot grow to the target thickness of the gate oxide layer in one step. In addition, the second gate oxide layer formed by the ALD process has better uniformity and density, and the control of the thickness of the second gate oxide layer is more accurate. The thermal budget of the ALD process is low, which improves the reliability of the medium voltage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0026] Figure 1 It is a flow chart of a method for forming a medium voltage device according to an embodiment of the present invention.

[0027] Figure 2 It is a schematic structural diagram of a medium voltage device after a shallow trench isolation structure is formed according to an embodiment of the present invention.

[0028] Figure 3 It is a schematic structural diagram of a medium voltage device after forming a first gate oxide layer according to an embodiment of the present invention.

[0029] Figure 4 It is a schematic structural diagram of a medium voltage device after forming a second gate oxide layer according to an embodiment of the present invention.

[0030] In the attached figure:

[0031] 10 - substrate; 11 - shallow trench isolation structure; 12 - first gate oxide layer; 13 - second gate oxide layer. DETAILED DESCRIPTION

[0032] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0033] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] Figure 1 FIG. 1 is a flow chart of a method for forming a medium voltage device according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a medium voltage device, including:

[0035] Step S10, providing a substrate, wherein a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure is used to define a medium voltage device area;

[0036] Step S20, forming a first gate oxide layer by using an ISSG process, wherein the first gate oxide layer covers the substrate;

[0037] Step S30, forming a second gate oxide layer by using an ALD process, wherein the second gate oxide layer covers the first gate oxide layer and the shallow trench isolation structure, and the first gate oxide layer and the second gate oxide layer together constitute the gate oxide layer of the medium voltage device region.

[0038] Figure 2 It is a schematic structural diagram of a medium voltage device after a shallow trench isolation structure is formed according to an embodiment of the present invention. Figure 3 It is a schematic structural diagram of a medium voltage device after forming a first gate oxide layer according to an embodiment of the present invention. Figure 4 1 is a schematic diagram of the structure of a medium voltage device after forming a second gate oxide layer according to an embodiment of the present invention. Figures 2 to 4The specific embodiments of the present invention are described in detail.

[0039] like Figure 2 As shown, a substrate 10 is provided, and the substrate 10 can provide an operating platform for subsequent processes. It can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, and can be a bare chip or a wafer processed by an epitaxial growth process. In detail, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 10 is a silicon substrate. A shallow trench isolation structure 11 is formed on the substrate 10, and the shallow trench isolation structure 11 is used to define an active area. The active area includes a low-voltage device area, a medium-voltage device area, and a high-voltage device area. Specifically, the shallow trench isolation structure 11 is used to isolate the low-voltage device area, the medium-voltage device area, and the high-voltage device area. The top surface of the shallow trench isolation structure 11 is higher than the surface of the substrate 10. This is because when the top surface of the shallow trench isolation structure 11 is lower than the surface of the substrate 10, gate oxide pitting problems are easily generated in subsequent processes. The withstand voltages of low-voltage devices, medium-voltage devices and high-voltage devices are different, and the thicknesses of the gate oxide layers in the corresponding low-voltage device area, the gate oxide layers in the medium-voltage device area and the gate oxide layers in the high-voltage device area are also different. The thickness of the gate oxide layer in the low-voltage device area is, for example, 20 angstroms to 50 angstroms, the thickness of the gate oxide layer in the medium-voltage device area is, for example, 170 angstroms to 250 angstroms, and the thickness of the gate oxide layer in the high-voltage device area is, for example, greater than 1000 angstroms. Usually, the gate oxide layer in the high-voltage device area is formed first. The gate oxide layer in the high-voltage device area is formed by a furnace tube process, and a thicker gate oxide layer can be formed by long-term oxidation. However, low-voltage devices and medium-voltage devices have relatively high requirements for the quality of the gate oxide layer. The gate oxide layer of the low-voltage device and the gate oxide layer of the medium-voltage device are generally formed by the ISSG process. The gate oxide layer thickness of the low voltage device is 20 angstroms to 50 angstroms, which can be formed by a one-step ISSG process. The one-step ISSG process can grow a gate oxide layer of up to 150 angstroms, but the thickness of the gate oxide layer in the medium voltage device area is at least greater than 170 angstroms, and the one-step ISSG process cannot form a gate oxide layer of the target thickness in the medium voltage device area. Therefore, in this embodiment, the ISSG process is first used to form a first gate oxide layer, and then the ALD process is used to form a second gate oxide layer. The first gate oxide layer and the second gate oxide layer together constitute the gate oxide layer of the medium voltage device area.

[0040] like Figure 3As shown, the first gate oxide layer 12 is formed by the ISSG process, and the first gate oxide layer 12 covers the substrate 10; the thickness of the first gate oxide layer is, for example, 50 angstroms to 150 angstroms. The process gas of the ISSG process includes oxygen and hydrogen, and the process temperature of the ISSG process is, for example, 700° C. to 1100° C. In this embodiment, the first gate oxide layer 12 is formed by the ISSG process, and the surface defects of the substrate 10 can be repaired at the same time.

[0041] like Figure 4 As shown, the second gate oxide layer 13 is formed by the ALD process, and the second gate oxide layer 13 covers the first gate oxide layer 12 and the shallow trench isolation structure 11, and the first gate oxide layer 12 and the second gate oxide layer 13 together constitute the gate oxide layer of the medium voltage device area. The thickness of the second gate oxide layer 13 is, for example, 30 angstroms to 200 angstroms. The thickness of the gate oxide layer in the medium voltage device area is greater than 170 angstroms to meet the withstand voltage requirements of the medium voltage device. That is, the sum of the thicknesses of the first gate oxide layer 12 and the second gate oxide layer 13 is greater than 170 angstroms. The medium voltage device is applied to the driving circuit, and its main function is to control and manage the power supply, provide a stable power supply, and receive and decode the image data of the controller. The withstand voltage requirements of the medium voltage device are relatively high. In this embodiment, the second gate oxide layer 13 is formed by the ALD process to meet the withstand voltage requirements of the medium voltage device by the sum of the thicknesses of the first gate oxide layer 12 and the second gate oxide layer 13. In this embodiment, the ISSG process is used to form the first gate oxide layer 12 and the ALD process is used to form the second gate oxide layer 13 to achieve the target thickness of the gate oxide layer, which overcomes the disadvantage that the ISSG process in the prior art cannot grow to the target thickness of the gate oxide layer in one step. In addition, the second gate oxide layer 13 formed by the ALD process has better uniformity and compactness, and the thickness of the second gate oxide layer 13 can be controlled more accurately. The process temperature of the ALD process is, for example, 300°C to 700°C. The thermal budget of the ALD process is low, which can improve the reliability of medium voltage devices.

[0042] Before forming the gate oxide layer of the medium voltage device area, a gate oxide layer has been formed on the high voltage device area. After forming the gate oxide layer of the medium voltage device area, it also includes: forming a gate oxide layer of the low voltage device area, and the gate oxide layer covers the substrate 10 of the low voltage device area. Next, a gate material layer is formed, and the gate material layer covers the gate oxide layers of the high voltage device area, the medium voltage device area and the low voltage device area; the material of the gate material layer is, for example, polysilicon, and can be formed by a furnace tube process. A hard mask layer and a photoresist layer are sequentially formed on the gate material layer, and a photolithography process is performed to form a patterned photoresist layer, and the patterned photoresist layer covers the gate material layer of the gate definition area. An etching process is performed, and a portion of the hard mask layer and a portion of the gate material layer are sequentially etched using the patterned photoresist layer as a mask, and the remaining portion of the gate material layer constitutes a gate structure.

[0043] Please continue to refer to Figure 4 This embodiment further provides a medium voltage device, which is manufactured by using any of the above-mentioned methods for forming a medium voltage device, and includes:

[0044] A substrate 10 is provided with a shallow trench isolation structure 11 formed thereon, and the shallow trench isolation structure 11 is used to define an active area; the active area includes a low voltage device area, a medium voltage device area and a high voltage device area. Specifically, the shallow trench isolation structure 11 is used to isolate the low voltage device area, the medium voltage device area and the high voltage device area. The top surface of the shallow trench isolation structure 11 is higher than the surface of the substrate 10, because when the top surface of the shallow trench isolation structure 11 is lower than the surface of the substrate 10, it is easy to generate a gate oxide defect (Gate oxide pitting) problem in the subsequent process. The withstand voltages of low voltage devices, medium voltage devices and high voltage devices are different, and the thicknesses of the gate oxide layer of the corresponding low voltage device area, the gate oxide layer of the medium voltage device area and the gate oxide layer of the high voltage device area are also different. The thickness of the gate oxide layer of the low voltage device area is, for example, 20 angstroms to 50 angstroms, the thickness of the gate oxide layer of the medium voltage device area is, for example, 170 angstroms to 250 angstroms, and the thickness of the gate oxide layer of the high voltage device area is, for example, greater than 1000 angstroms.

[0045] A first gate oxide layer 12 covers the substrate 10 . The thickness of the first gate oxide layer is, for example, 50 angstroms to 150 angstroms.

[0046] A second gate oxide layer 13, wherein the second gate oxide layer 13 covers the first gate oxide layer 12 and the shallow trench isolation structure 11, and the first gate oxide layer 12 and the second gate oxide layer 13 together constitute a gate oxide layer of a medium voltage device region. The thickness of the second gate oxide layer is, for example, 30 angstroms to 200 angstroms. The thickness of the gate oxide layer of the medium voltage device region is greater than 170 angstroms to meet the withstand voltage requirements of the medium voltage device. That is, the sum of the thickness of the first gate oxide layer 12 and the second gate oxide layer 13 is greater than 170 angstroms.

[0047] In summary, in a method for forming a medium-voltage device provided in an embodiment of the present invention, a first gate oxide layer is first formed by using an ISSG process, and the first gate oxide layer covers the substrate; then a second gate oxide layer is formed by using an ALD process, and the second gate oxide layer covers the first gate oxide layer and the shallow trench isolation structure, and the first gate oxide layer and the second gate oxide layer together constitute the gate oxide layer of the medium-voltage device region. The present invention can repair the surface defects of the substrate while using the ISSG process to form the first gate oxide layer; and the sum of the thickness of the first gate oxide layer formed by the ISSG process and the second gate oxide layer formed by the ALD process can reach the target thickness of the gate oxide layer, which overcomes the disadvantage that the ISSG process cannot grow to the target thickness of the gate oxide layer in one step. In addition, the second gate oxide layer formed by the ALD process has better uniformity and density, and the control of the thickness of the second gate oxide layer is more accurate. The thermal budget of the ALD process is low, which can improve the reliability of the medium-voltage device.

[0048] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0049] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a medium voltage device, characterized in that: include: Providing a substrate, wherein a shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure is used to define a medium voltage device area; Forming a first gate oxide layer by adopting an ISSG process, wherein the first gate oxide layer covers the substrate; A second gate oxide layer is formed by adopting the ALD process, the second gate oxide layer covers the first gate oxide layer and the shallow trench isolation structure, and the first gate oxide layer and the second gate oxide layer together constitute the gate oxide layer of the medium voltage device area.

2. The method for forming a medium voltage device according to claim 1, characterized in that: The thickness of the first gate oxide layer is 50 angstroms to 150 angstroms.

3. The method for forming a medium voltage device according to claim 1, characterized in that: The thickness of the second gate oxide layer is 30 angstroms to 200 angstroms.

4. The method for forming a medium voltage device according to claim 1, characterized in that: The thickness of the gate oxide layer in the medium voltage device region is greater than 170 angstroms.

5. The method for forming a medium voltage device according to claim 1, characterized in that: The process temperature of the ISSG process is 700° C. to 1100° C.

6. The method for forming a medium voltage device according to claim 1, characterized in that: The ALD process has a process temperature of 300° C. to 700° C.

7. The method for forming a medium voltage device according to claim 1, characterized in that: The substrate also includes a low-voltage device area and a high-voltage device area, and the shallow trench isolation structure is used to isolate the low-voltage device area, the medium-voltage device area and the high-voltage device area.

8. The method for forming a medium voltage device according to claim 7, characterized in that: Before forming the gate oxide layer of the medium voltage device area, a gate oxide layer has been formed on the high voltage device area, and after forming the gate oxide layer of the medium voltage device area, the method comprises: forming a gate oxide layer in a low voltage device region, wherein the gate oxide layer covers a substrate in the low voltage device region; Forming a gate material layer, wherein the gate material layer covers the gate oxide layers of the high voltage device region, the medium voltage device region and the low voltage device region; A photolithography and etching process is performed to etch a portion of the gate material layer, and the remaining portion of the gate material layer forms a gate structure.

9. A medium voltage device, characterized in that: The medium voltage device is manufactured by the method for forming the medium voltage device according to any one of claims 1 to 8, comprising: A substrate having a shallow trench isolation structure formed therein, wherein the shallow trench isolation structure is used to define a medium voltage device area; a first gate oxide layer, wherein the first gate oxide layer covers the substrate; A second gate oxide layer, wherein the second gate oxide layer covers the first gate oxide layer and the shallow trench isolation structure, and the first gate oxide layer and the second gate oxide layer together constitute a gate oxide layer of the medium voltage device region.

10. The medium voltage device according to claim 9, characterized in that: The thickness of the gate oxide layer in the medium voltage device region is greater than 170 angstroms.

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