Heterojunction solar cell and manufacturing method and device thereof

Abstract

The invention discloses a heterojunction solar cell and a manufacturing method and equipment thereof. Respectively forming at least one front surface passivation layer made of an intrinsic amorphous silicon-based material and at least one back surface passivation layer made of an intrinsic amorphous silicon-based material on the front surface and the back surface of the silicon substrate; respectively forming at least one front doping layer and at least one back doping layer which are made of microcrystalline silicon-based materials or nanocrystalline silicon-based materials on the at least one front passivation layer and the at least one back passivation layer; in the process of depositing at least one of the front doping layer and the back doping layer, the silicon substrate is placed on a carrier plate, the upper surface of the carrier plate is provided with one or more silicon substrate containing areas, and at least one part of the periphery of each containing area is provided with a flange. The manufacturing process of the heterojunction solar cell is simplified, and the performance of the heterojunction solar cell is improved.

Description

Technical Field

[0001] The invention relates to a heterojunction solar cell and a manufacturing method and equipment thereof. Background Art

[0002] Heterojunction solar cells combine the advantages of single-crystal silicon solar cells and amorphous silicon solar cells. They have the advantages of simple process flow, high efficiency, low temperature coefficient, and high conversion efficiency, and have become a hot spot for research and development in the photovoltaic industry. The process flow of heterojunction solar cells includes four main steps: cleaning and texturing, PECVD film deposition, PVD film deposition, and electrode metallization. Among them, the PECVD film deposition step is particularly critical and is the core process for forming heterojunction ninip or nipin structures. In the process of preparing amorphous silicon or microcrystalline silicon thin films using PECVD technology, due to the thinning of silicon wafer substrates and the precision limitations of thin film deposition processes, the film layer will inevitably extend to the side of the silicon wafer substrate to form wrap-around plating, causing the two film layers of different doping types to overlap, resulting in contact conduction, resulting in shunt resistance and leakage current loss at the edge of the heterojunction solar cell, thereby affecting the photoelectric conversion efficiency of the battery.

[0003] In current industrial production, there are attempts to use special etching technology to remove the excess coating on the edge of the substrate, but this process is often complicated, increasing the production cost of the battery, and will also damage the battery body, which in turn damages the battery structure. There are also special masks used in the PECVD process to prevent the edge of the silicon wafer from being plated to form an impurity layer, but there is a problem with the accuracy of the mask alignment. In addition, separate etching or masking adds additional equipment or processes to the original PECVD process, increasing the complexity and cost of the process. Summary of the invention

[0004] The object of the present invention is to provide a heterojunction solar cell and a method and device for manufacturing the same.

[0005] To achieve the purpose of the present invention, the present invention proposes a method for manufacturing a heterojunction solar cell, which adopts a plate-type capacitive coupled plasma enhanced chemical vapor deposition method, and includes the following steps: providing a doped silicon substrate; forming at least one front passivation layer composed of an intrinsic amorphous silicon-based material and at least one back passivation layer composed of an intrinsic amorphous silicon-based material on the front and back sides of the silicon substrate respectively; forming at least one front doping layer composed of a microcrystalline silicon-based material or a nanocrystalline silicon-based material and at least one back doping layer composed of a microcrystalline silicon-based material or a nanocrystalline silicon-based material on the at least one front passivation layer and the at least one back passivation layer respectively; in the process of depositing at least one of the front doping layer and the back doping layer, the silicon substrate is placed on a carrier, the upper surface of the carrier is provided with one or more silicon substrate accommodating areas, and at least a portion of the surroundings of the accommodating areas is provided with a retaining edge.

[0006] As a preferred implementation manner, the ratio of the height of the rib to the thickness of the silicon substrate is in the range of 1:1 to 15:1.

[0007] As a preferred implementation, the distance between the rib and the edge of the silicon substrate is less than 3 mm.

[0008] As a preferred embodiment, the front doped layer and the back doped layer are prepared by plate-type capacitive coupled plasma enhanced chemical vapor deposition, wherein the RF power frequency is in the range of 2MHz-100MHz, and the RF power density is in the range of 0.05-1W / cm 2 The process chamber reaction gases include SiH4 and H2, the SiH4:H2 flow ratio is in the range of 1:10 to 1:1000, and the process chamber reaction gas pressure is in the range of 1-20 Torr.

[0009] As a preferred embodiment, on the side edge of the heterojunction solar cell, on the edge area of ​​the silicon substrate, the order of layers exists from the inside to the outside in the following order: at least one front passivation layer, at least one back passivation layer on the at least one front passivation layer; or, at least one front passivation layer, at least one back passivation layer on the at least one front passivation layer, at least one front doped layer on the at least one back passivation layer; or, at least one front passivation layer, at least one back passivation layer on the at least one front passivation layer, at least one back doped layer on the at least one back passivation layer; or, at least one back passivation layer, at least one front passivation layer on the at least one back passivation layer; or, at least one back passivation layer, at least one front passivation layer on the at least one back passivation layer, at least one front doped layer on the at least one front passivation layer; or, at least one back passivation layer, at least one front passivation layer on the at least one back passivation layer, at least one back doped layer on the at least one front passivation layer.

[0010] As a preferred embodiment, the silicon substrate has a first conductivity type of doping; in the front doping layer and the back doping layer, one of the doping types is the first conductivity type, and the other doping type is a second conductivity type opposite to the first conductivity type.

[0011] As a preferred embodiment, the method for manufacturing a heterojunction solar cell also includes the following steps in order: forming at least one transparent back conductive layer on at least one back doped layer; forming at least one transparent front conductive layer on at least one front doped layer; forming a back electrode on at least one transparent back conductive layer; and forming a front electrode on at least one transparent front conductive layer.

[0012] The present invention also proposes a heterojunction solar cell, the structure of which includes: a doped silicon substrate; at least one front passivation layer formed on the front surface of the silicon substrate and composed of an intrinsic amorphous silicon-based material; at least one front doped layer formed on the at least one front passivation layer and composed of a microcrystalline silicon-based material or a nanocrystalline silicon-based material; at least one back passivation layer formed on the back surface of the silicon substrate and composed of an intrinsic amorphous silicon-based material; at least one back doped layer formed on the at least one back passivation layer and composed of a microcrystalline silicon-based material or a nanocrystalline silicon-based material; on the side edge of the heterojunction solar cell, on the edge region of the silicon substrate, the order of layers is from inside to outside in the following order: at least one front passivation layer, at least one back passivation layer on the at least one front passivation layer ; or, at least one front passivation layer, at least one back passivation layer on the at least one front passivation layer, and at least one front doped layer on the at least one back passivation layer; or, at least one front passivation layer, at least one back passivation layer on the at least one front passivation layer, and at least one back doped layer on the at least one back passivation layer; or, at least one back passivation layer, at least one front passivation layer on the at least one back passivation layer; or, at least one back passivation layer, at least one front passivation layer on the at least one back passivation layer, and at least one front doped layer on the at least one front passivation layer; or, at least one back passivation layer, at least one front passivation layer on the at least one back passivation layer, and at least one back doped layer on the at least one front passivation layer.

[0013] As a preferred embodiment, in the solar cell, the silicon substrate has a first conductivity type of doping; in the front doping layer and the back doping layer, one of the doping types is the first conductivity type, and the other doping type is a second conductivity type opposite to the first conductivity type.

[0014] As a preferred embodiment, in the solar cell, the silicon substrate adopts an N-type textured silicon wafer, the first conductivity type is N-type, and the second conductivity type is P-type; or, the silicon substrate adopts a P-type textured silicon wafer, the first conductivity type is P-type, and the second conductivity type is N-type.

[0015] As a preferred embodiment, in the solar cell, at least one transparent front conductive layer is formed on the at least one front doped layer; at least one transparent back conductive layer is formed on the at least one back doped layer; a front electrode is formed on the at least one transparent front conductive layer; and a back electrode is formed on the at least one transparent back conductive layer.

[0016] The present invention also proposes a device for manufacturing a heterojunction solar cell, which adopts a plate-type capacitively coupled plasma enhanced chemical vapor deposition method, and the device includes: at least one process chamber for depositing a doping layer, a gas diffuser located inside the process chamber, a radio frequency power supply electrically connected to the gas diffuser, and a heating plate for heating. During the deposition of the doping layer, the silicon substrate is placed on a carrier, and one or more silicon substrate accommodating areas are provided on the upper surface of the carrier, and at least a portion of the surrounding area of ​​the accommodating area is provided with a retaining edge.

[0017] As a preferred implementation manner, the height of the rib is greater than the thickness of the silicon substrate, and the ratio of the height of the rib to the thickness of the silicon substrate is in the range of 1:1 to 15:1.

[0018] As a preferred embodiment, the equipment also includes a DC bias device, the gas diffuser serves as an upper electrode plate, and the carrier plate or the heating plate in contact with the carrier plate serves as a lower electrode plate; during the deposition of the doping layer, the DC bias device is electrically connected to the upper electrode plate and outputs a positive DC voltage to the upper electrode plate; or, during the deposition of the doping layer, the DC bias device is electrically connected to the lower electrode plate and outputs a negative DC voltage to the lower electrode plate.

[0019] As a preferred embodiment, the equipment also includes a heating plate lifting mechanism. During the deposition of the doping layer, the carrier plate is placed on the heating plate, and the heating plate is placed on the heating plate lifting mechanism. The distance between the lower electrode plate and the upper electrode plate is adjusted by adjusting the height of the heating plate lifting mechanism. During the preparation of the front doping layer and the back doping layer, the distance between the upper and lower electrodes is in the range of 5mm-50mm.

[0020] Compared with the prior art, the present invention has the following significant advantages:

[0021] (1) In the present invention, during the deposition of the front doped layer or the back doped layer, an electric field that can act on charged particles is formed between the retaining edge and the silicon substrate by means of the retaining edge, and the charged particles bombard the edge region of the edge side of the silicon substrate under the action of the electric field, thereby preventing the edge region of the edge side of the silicon substrate from forming the front doped layer or the back doped layer. In this way, during the deposition of the microcrystalline silicon doped layer on the front or back side of the silicon substrate, the formation of the microcrystalline silicon doped layer in the edge region of the silicon substrate is simultaneously prevented, and the etching of the microcrystalline silicon doped layer in the edge region of the silicon substrate is simultaneously achieved, thereby eliminating the plating bypass, which not only improves the manufacturing efficiency of heterojunction solar cells, but also eliminates the need to add additional etching or mask equipment and processes on the edge side of the silicon substrate, thereby reducing the process complexity and manufacturing cost. In addition, there is no problem of mask alignment accuracy when using a mask to prevent the formation of a doped layer in the edge region of the silicon substrate in the prior art, thereby simplifying the manufacturing process of heterojunction solar cells and improving the performance of heterojunction solar cells.

[0022] (2) In the present invention, the process conditions such as the frequency, power, reaction gas pressure and H2 ratio of the RF power supply are adjustable. By adjusting these process conditions, the bombardment of charged particles on the side edge area of ​​the silicon substrate can be enhanced or weakened according to the requirements of the solar cell. The etching accuracy of the microcrystalline silicon doped layer in the edge area of ​​the silicon substrate is improved, and the thickness of the microcrystalline silicon doped layer in the edge area of ​​the silicon substrate can also be controlled.

[0023] (3) The present invention applies a DC voltage to the upper electrode plate or the lower electrode plate through a DC bias device, which can additionally change the sheath thickness, so that the sheath thickness on the side of the lower electrode plate is thicker and the sheath thickness on the side of the upper electrode plate is thinner, thereby adjusting the electric field strength and charged ion bombardment effect between the guard edge and the edge of the silicon substrate, and can further improve the fine control of the etching precision intensity and accuracy of the microcrystalline silicon doping layer.

[0024] (4) In the process of depositing the microcrystalline silicon doping layer of the present invention, the carrier plate is placed on the heating plate, and the heating plate is placed on the heating plate lifting mechanism. The height of the heating plate lifting mechanism is adjusted to adjust the distance between the lower electrode plate and the upper electrode plate, thereby changing the bombardment intensity of the charged particles on the edge area of ​​the silicon substrate, which can further improve the fine control of the etching precision intensity and accuracy of the microcrystalline silicon doping layer.

[0025] Other features and advantages of the present invention will be described in the following description, and part of them will become obvious from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of a solar cell structure shown in an embodiment of the present invention.

[0027] Figure 2 It is a schematic diagram of another solar cell structure shown in an embodiment of the present invention.

[0028] Figure 3 It is a schematic diagram of another solar cell structure shown in an embodiment of the present invention.

[0029] Figure 4 It is a schematic diagram of the principle of the accommodation area shown in an embodiment of the present invention.

[0030] Figure 5 It is a schematic diagram showing the principle of charged particles bombarding the edge area of ​​a silicon substrate during the manufacturing process of a solar cell shown in an embodiment of the present invention.

[0031] Figure 6 It is a schematic diagram of the effect of charged particles bombarding the edge area of ​​the silicon substrate during the solar cell manufacturing process shown in an embodiment of the present invention.

[0032] Figure 7 It is a schematic diagram of a process chamber and a DC bias device thereof in a solar cell manufacturing device shown in an embodiment of the present invention.

[0033] Figure 8 It is a schematic diagram of another process chamber and a DC bias device thereof in the solar cell manufacturing equipment shown in an embodiment of the present invention;

[0034] Description of reference numerals:

[0035] 10-silicon substrate; 11-front passivation layer; 12-front doping layer; 21-back passivation layer; 22-back doping layer; 30-rib; 41-gas diffuser; 42-carrier plate 42; heating plate-43; lifting mechanism-44; gas source-45. DETAILED DESCRIPTION

[0036] It is easy to understand that according to the technical solution of the present invention, without changing the essential spirit of the present invention, a person skilled in the art can imagine various embodiments of the present invention. Therefore, the following specific embodiments and drawings are only exemplary descriptions of the technical solution of the present invention, and should not be regarded as the whole of the present invention or as a limitation or limitation of the technical solution of the present invention. On the contrary, the purpose of providing these embodiments is to enable those skilled in the art to understand the present invention more thoroughly. The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the innovative concept of the present invention.

[0037] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0038] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0039] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0040] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0041] Combination Figures 1 to 5The heterojunction solar cell manufacturing method of the present invention adopts a plate-type capacitive coupled plasma enhanced chemical vapor deposition method, and includes the following steps: providing a doped silicon substrate 10; forming at least one front passivation layer 11 composed of an intrinsic amorphous silicon-based material and at least one back passivation layer 21 composed of an intrinsic amorphous silicon-based material on the front and back of the silicon substrate 10; forming at least one front doping layer 12 composed of a microcrystalline silicon-based material or a nanocrystalline silicon-based material and at least one back doping layer 22 composed of a microcrystalline silicon-based material or a nanocrystalline silicon-based material on the at least one front passivation layer 11 and the at least one back passivation layer 21. In the present invention, there is no specific order limit for the aforementioned steps, and those skilled in the art can change the order of the aforementioned steps in combination with the specific battery structure requirements. In the above-mentioned heterojunction solar cell manufacturing process, during the deposition of the front doping layer 12, or during the deposition of the back doping layer 22, or during the deposition of both the front doping layer 12 and the back doping layer 22, the silicon substrate 10 is placed on a carrier, and one or more silicon substrate accommodating areas are provided on the upper surface of the carrier, and at least a portion of the surrounding of the accommodating area is provided with a retaining edge 30. Due to the existence of the retaining edge 30, during the process of preparing the front doping layer 12 or the back doping layer 22 by plate-type capacitive coupled plasma enhanced chemical vapor deposition, an electric field that can act on charged particles will be formed between the retaining edge and the silicon substrate 10, and the charged particles will bombard the edge area of ​​the edge side of the silicon substrate 10 under the action of the electric field, preventing the edge area of ​​the edge side of the silicon substrate 10 from forming the front doping layer 12 and / or the back doping layer 22. In this way, the front doping layer 12 can be prevented from contacting the edge area of ​​the edge side of the silicon substrate 10 with the back doping layer 22, thereby improving the shunt resistance and leakage current loss at the edge of the solar cell. At the same time, in the process of depositing the front doping layer 12 or the back doping layer 22, the present invention forms an electric field that can act on the charged particles between the ribs 30 and the silicon substrate 10, and the charged particles bombard the edge region of the edge side of the silicon substrate 10 under the action of the electric field, thereby preventing the formation of the front doping layer 12 and / or the back doping layer 22 in the edge region of the edge side of the silicon substrate 10. In this way, in the process of depositing the front doping layer 12 or the back doping layer 22, the present invention simultaneously prevents the formation of the front doping layer 12 and / or the back doping layer 22 in the edge region of the silicon substrate 10, which not only improves the manufacturing efficiency of the heterojunction solar cell, but also does not need to add additional etching or masking equipment and processes on the edge side of the silicon substrate 10, thereby reducing the process complexity and manufacturing cost.

[0042] The silicon substrate is usually a silicon wafer that has undergone a previous texturing process, and can be a single-sided texturing silicon wafer or a double-sided texturing silicon wafer.

[0043] The present invention adopts a plate-type capacitive coupling PECVD deposition method. During the deposition of the front doping layer 12 or the back doping layer 22 in the process chamber, in the area formed by the upper electrode plate (such as a gas diffuser) and the lower electrode plate (such as a heating plate or a carrier plate), process gases such as silane and hydrogen are dissociated into plasma by radio frequency, and neutral groups and charged particles undergo chemical reactions on the surface of the silicon substrate 10 to deposit into a film, and a microcrystalline structure is formed under the action of high-energy ions and high H dilution. Although the plasma is electrically neutral, there will be a very thin positive charge area between them and the upper and lower electrode plates, respectively, which is called a sheath layer. A retaining edge 30 for fixing the position of the silicon wafer is provided on the carrier plate, and the carrier plate is adjacent to the sheath layer as a lower electrode plate. Since the electrical properties of the ribs set on the carrier are different from those of the silicon substrate 10 material itself, there are differences in charge accumulation, resulting in different potentials between the ribs 30 and the silicon substrate 10. The potential on the silicon substrate side is low, and the potential on the rib side is high. The potential difference formed between the two will generate a local electrostatic field. Under the action of the electric field, the charged particles accelerate toward the silicon substrate 10, thereby bombarding the edge area of ​​the silicon substrate 10, preventing the formation of the front doping layer 12 or the back doping layer 22 in the edge area of ​​the silicon substrate 10, thereby achieving the effect of etching the edge of the silicon substrate 10, thereby eliminating the plating phenomenon at the edge of the silicon substrate 10 during the deposition of the doping layer, that is, avoiding the front doping layer 12 and the back doping layer 22 from overlapping or contacting at the edge of the silicon substrate 10.

[0044] The height of the rib 30 is greater than the thickness of the silicon substrate 10 , and the ratio of the height of the rib 30 to the thickness of the silicon substrate 10 is in the range of 1:1 to 15:1.

[0045] The distance between the rib 30 and the edge of the silicon substrate 10 is less than 3 mm.

[0046] The front doped layer 12 and the back doped layer 22 are prepared by plate-type capacitive coupled plasma enhanced chemical vapor deposition, wherein the frequency of the radio frequency power supply is in the range of 2MHz-100MHz, that is, the plasma is excited by the radio frequency power supply with a frequency of 2MHz-100MHz, and the power density of the radio frequency power supply is 0.05-1W / cm 2 The process chamber reaction gas includes SiH4 and H2, the SiH4:H2 flow ratio is in the range of 1:10 to 1:1000, and the process chamber reaction gas pressure is in the range of 1-20Torr. In the present invention, by adjusting the process conditions, the bombardment of the charged particles on the side edge area of ​​the silicon substrate 10 can be enhanced or weakened according to the requirements of the solar cell. For example, increasing the frequency, power, reaction gas pressure and H2 proportion of the RF power supply can enhance the bombardment and etching effects. On the contrary, the bombardment and etching effects are weakened.

[0047] Under the bombardment of charged particles, different structures can be formed on the side edges of the heterojunction solar cell. For example, on the edge region of the silicon substrate 10, the order of layers from inside to outside is as follows:

[0048] like Figure 1 As shown, at least one front passivation layer 11 and at least one back passivation layer 21 on the at least one front passivation layer 11. That is, during the deposition of the front doping layer 12 and the back doping layer 22, charged particles are used to bombard the edge region of the silicon substrate 10, and the front doping layer 12 and the back doping layer 22 are not formed on the edge region of the silicon substrate 10. Under this structure, Figure 6 As shown, a bombardment effect can also be formed locally near the side edge of the silicon substrate 10, causing etching of the front doped layer 12 on the front side of the silicon substrate 10 or the back doped layer 22 on the back side (the front passivation layer / back passivation layer are not shown in the figure), and the etching width varies from 0 to 1 mm.

[0049] Or, if Figure 2 As shown, at least one front passivation layer 11, at least one back passivation layer 21 on the at least one front passivation layer 11, and at least one front doping layer 12 on the at least one back passivation layer 21. That is, in the process of depositing the back doping layer 22, charged particles are used to bombard the edge area of ​​the silicon substrate 10, and the back doping layer 22 is not formed on the edge area of ​​the silicon substrate 10. In the process of depositing the front doping layer 12, the process parameters are controlled to weaken the electric field between the silicon substrate 10 and the carrier rib, the etching rate is less than the deposition rate, and the front doping layer is deposited on the sidewall of the silicon substrate 10, so that the back doping layer 22 is not formed on the edge area of ​​the silicon substrate 10, and only the front doping layer 12 exists.

[0050] Or, if Figure 3 As shown, at least one front passivation layer 11, at least one back passivation layer 21 on the at least one front passivation layer 11, and at least one back doping layer 22 on the at least one back passivation layer 21. That is, in the process of depositing the back doping layer 22, by controlling the process parameters, the electric field between the silicon substrate 10 and the carrier rib is weakened, the etching rate is less than the deposition rate, and the back doping layer is deposited on the sidewall of the silicon substrate 10. In the process of depositing the front doping layer 12, charged particles are used to bombard the edge area of ​​the silicon substrate 10, and the front doping layer 12 is not formed on the edge area of ​​the silicon substrate 10. In this way, the front doping layer 12 is not formed on the edge area of ​​the silicon substrate 10, and only the back doping layer 22 exists.

[0051] Alternatively, at least one back passivation layer 21 and at least one front passivation layer 11 on the at least one back passivation layer 21. Figure 1The difference between the structures shown is that, in the edge region of the silicon substrate 10, the back passivation layer 21 is close to the silicon substrate 10, that is, the back passivation layer 21 is formed first and then the front passivation layer 11 is formed, and in the edge region of the silicon substrate 10, the front passivation layer 11 is located on the surface of the back passivation layer 21 on the side facing away from the silicon substrate 10.

[0052] Alternatively, at least one back passivation layer 21, at least one front passivation layer 11 on the at least one back passivation layer 21, and at least one front doping layer 12 on the at least one front passivation layer 11. Figure 2 The structure shown is different in that the back side passivation layer 21 is close to the silicon substrate 10 in the edge region of the silicon substrate 10 .

[0053] Alternatively, at least one back passivation layer 21, at least one front passivation layer 11 on the at least one back passivation layer 21, and at least one back doping layer 22 on the at least one front passivation layer 11. Figure 3 The structure shown is different in that the back side passivation layer 21 is close to the silicon substrate 10 in the edge region of the silicon substrate 10 .

[0054] The above-mentioned various specific structures can be specifically selected by those skilled in the art in combination with specific usage scenarios under the concept of the present invention.

[0055] In the present invention, the silicon substrate 10 has a first conductive type of doping; in the front doping layer 12 and the back doping layer 22, one of the doping types is the first conductive type, and the other doping type is the second conductive type opposite to the first conductive type. For example, the silicon substrate 10 adopts an N-type textured silicon wafer, the first conductive type is N-type, and the second conductive type is P-type. Alternatively, the silicon substrate 10 adopts a P-type textured silicon wafer, the first conductive type is P-type, and the second conductive type is N-type.

[0056] Here, with the help of a description of an embodiment, the preparation process of a heterojunction solar cell is introduced. A crystalline silicon substrate of a first doping type is first provided. At least one front passivation layer 11 composed of an intrinsic amorphous silicon-based material and at least one back passivation layer 21 composed of an intrinsic amorphous silicon-based material are formed on the front and back sides of the silicon substrate 10 respectively by vacuum thin film deposition technology. The front passivation layer 11 is plated around during the formation process, covering the side and back local edges of the silicon substrate 10. The back passivation layer 21 is plated around during the formation process, covering the front passivation layer 11 at the side and front local edges of the silicon substrate 10. A first microcrystalline silicon doping layer (e.g., a front doping layer) of the same doping type as the first and a second microcrystalline silicon doping layer (e.g., a back doping layer) of the opposite doping type to the first are formed on the front and back sides of the silicon substrate 10 on which the intrinsic amorphous silicon-based film layer is deposited by vacuum thin film deposition technology. The silicon substrate 10 completes the deposition of the front doping layer and the back doping layer in the silicon substrate accommodating area on the carrier. At least a portion of the accommodating area is provided with a rib 30, the height of which is higher than the thickness of the silicon wafer, and the distance between the carrier rib and the edge of the substrate is less than 3 mm. The doping layer is prepared by plate-type capacitive coupled plasma enhanced chemical vapor deposition, and the plasma is excited by a radio frequency power supply with a frequency of 2 MHz-100 MHz, and the power density of the power supply is in the range of 0.05-1 W / cm 2 The process gas includes SiH4 and H2, the flow ratio of SiH4:H2 is between 1:10 and 1:1000, and the process gas pressure is 1-20 Torr. In the process of depositing the front doping layer 12 and the back doping layer 22, charged particles are used to bombard the edge area of ​​the silicon substrate 10, and the front doping layer 12 and the back doping layer 22 are not formed on the edge area of ​​the silicon substrate 10, that is, no wrap-around plating is formed on the edge area of ​​the silicon substrate 10.

[0057] For the different heterojunction solar cell manufacturing methods shown in the above embodiments, preferably, the conductive layers and electrodes on the front and back sides of the silicon substrate 10 are formed according to the following steps in order, specifically: forming at least one transparent back conductive layer (not shown in the figure) on at least one back doped layer 22; forming at least one transparent front conductive layer (not shown in the figure) on at least one front doped layer 12; forming a back electrode (not shown in the figure) on at least one transparent back conductive layer; forming a front electrode (not shown in the figure) on at least one transparent front conductive layer, the above-mentioned front and back conductive layers and front and back electrodes belong to the conventional structure of heterojunction solar cells, and no further description is given here. However, it should be noted that in the process of manufacturing solar cells, the carrier will absorb water vapor in the air, and water vapor will also provide oxygen in each deposition step, but the incident light front side of the solar cell is sensitive to oxygen and has high oxygen control requirements. Therefore, the present invention first deposits the conductive layer on the back side of the silicon substrate 10, and then deposits the conductive layer on the front side. This is conducive to further control of water vapor during the deposition process of the front side of the solar cell.

[0058] Based on the various embodiments of the above-mentioned method for manufacturing a heterojunction solar cell of the present invention, a heterojunction solar cell with the following structure can be prepared.

[0059] The structure of the heterojunction solar cell includes: a doped silicon substrate 10; at least one front passivation layer 11 formed on the front of the silicon substrate 10 and composed of an intrinsic amorphous silicon-based material; at least one front doping layer 12 formed on the at least one front passivation layer 11 and composed of a microcrystalline silicon-based material or a nanocrystalline silicon-based material; at least one back passivation layer 21 formed on the back of the silicon substrate 10 and composed of an intrinsic amorphous silicon-based material; at least one back doping layer 22 formed on the at least one back passivation layer 21 and composed of a microcrystalline silicon-based material or a nanocrystalline silicon-based material. On the side edge of the heterojunction solar cell, on the edge region of the silicon substrate 10, the order of the layers from the inside to the outside is in the following order and there are several different structures:

[0060] at least one front passivation layer 11, and at least one back passivation layer 21 on the at least one front passivation layer 11; or,

[0061] at least one front passivation layer 11, at least one back passivation layer 21 on the at least one front passivation layer 11, at least one front doping layer 12 on the at least one back passivation layer 21; or,

[0062] at least one front passivation layer 11, at least one back passivation layer 21 on the at least one front passivation layer 11, at least one back doping layer 22 on the at least one back passivation layer 21; or,

[0063] at least one back passivation layer 21, and at least one front passivation layer 11 on the at least one back passivation layer 21; or,

[0064] at least one back passivation layer 21, at least one front passivation layer 11 on the at least one back passivation layer 21, at least one front doping layer 12 on the at least one front passivation layer 11; or,

[0065] At least one back passivation layer 21 , at least one front passivation layer 11 on the at least one back passivation layer 21 , and at least one back doping layer 22 on the at least one front passivation layer 11 .

[0066] In the heterojunction solar cells of the above structures, at least one transparent front conductive layer is formed on the at least one front doped layer 12; at least one transparent back conductive layer is formed on the at least one back doped layer 22; a front electrode is formed on the at least one transparent front conductive layer; and a back electrode is formed on the at least one transparent back conductive layer. The above front and back conductive layers and the front and back electrodes belong to the conventional structure of heterojunction solar cells and will not be further described here.

[0067] In the heterojunction solar cells of the above structures, the silicon substrate 10 has a first conductive type of doping; in the front doping layer 12 and the back doping layer 22, one of the doping types is the first conductive type, and the other doping type is the second conductive type opposite to the first conductive type. Specifically, the silicon substrate 10 adopts an N-type textured silicon wafer, the first conductive type is N-type, and the second conductive type is P-type; or, the silicon substrate 10 adopts a P-type textured silicon wafer, the first conductive type is P-type, and the second conductive type is N-type.

[0068] The present invention also proposes a device for manufacturing heterojunction solar cells suitable for the above-mentioned manufacturing method and battery structure, which adopts a plate-type capacitive coupled plasma enhanced chemical vapor deposition method. The device includes: at least one process chamber for depositing a doping layer, a gas diffuser located inside the process chamber, a radio frequency power supply RF electrically connected to the gas diffuser, and a heating plate for heating. During the deposition of the doping layer, the silicon substrate 10 is placed on a carrier, and one or more silicon substrate accommodating areas are provided on the upper surface of the carrier, and a retaining edge 30 is provided at least in part around the accommodating area.

[0069] The height of the rib 30 is greater than the thickness of the silicon substrate 10, and the ratio of the height of the rib 30 to the thickness of the silicon substrate 10 is in the range of 1:1 to 15:1. The distance between the rib 30 and the edge of the silicon substrate 10 is less than 3 mm.

[0070] The frequency of the RF power source is in the range of 2MHz-100MHz, the plasma is excited by the RF power source with a frequency of 2MHz-100MHz, and the power density of the RF power source is 0.05-1W / cm 2 The process chamber reaction gas includes SiH4 and H2, the SiH4:H2 flow ratio is in the range of 1:10 to 1:1000, and the process chamber reaction gas pressure is in the range of 1-20 Torr. By adjusting at least one of the RF power frequency, the RF power power density, the process chamber reaction gas pressure, and the H2 flow ratio, the bombardment intensity of the charged particles on the edge area of ​​the silicon substrate 10 can be changed.

[0071] like Figure 7 or Figure 8 As shown, the process chamber adopts the flat capacitor coupling technology, the process chamber is externally connected to the radio frequency power supply RF, the vacuum system, and the gas source 45, and is internally provided with a discharge structure connected to the radio frequency power supply, a heating plate 43, and a carrier plate 42 for holding the silicon substrate.

[0072] like Figure 4 As shown, the upper surface of the carrier 42 is provided with a plurality of silicon substrate accommodating areas, and a rib 30 is provided around the accommodating area, and the height of the rib 30 is higher than the thickness of the silicon substrate 10. The distance between the carrier rib 30 and the edge of the silicon substrate 10 is less than 3 mm. The ratio of the height of the rib 30 to the thickness of the silicon substrate 10 is preferably 1:1 to 15:1. If the ratio is too low, the electric field area is too small, and the charged particles cannot bombard or etch the edge area of ​​the silicon substrate. If the ratio is too large, the rib has a shadow effect, which will cause abnormal deposition of the doped layer in the local area near the edge side of the front or back side of the silicon substrate, or even the formation of no doped layer.

[0073] like Figure 7 or Figure 8 As shown, the discharge structure includes the gas diffuser 41 as an upper electrode plate, a carrier plate 42 as a lower electrode plate or a heating plate 43 in contact with the carrier plate.

[0074] Preferably, the device is also provided with a heating plate lifting mechanism 44, and the position of the lower electrode plate is adjusted by the heating plate lifting mechanism 44, so as to adjust the distance between the upper and lower electrode plates during the process, and better control the deposition quality of the microcrystalline silicon thin film and the bombardment and etching effect of the edge. During the deposition of the doped layer, the carrier plate 42 is placed on the heating plate, and the heating plate 43 is placed on the heating plate lifting mechanism 44. The distance between the lower electrode plate and the upper electrode plate is adjusted by adjusting the height of the heating plate lifting mechanism 44, so as to change the bombardment intensity of the charged particles on the edge area of ​​the silicon substrate 10.

[0075] As an optimization method, the equipment also includes a DC bias device DC, the gas diffuser 41 serves as an upper electrode plate, and the carrier plate 42 or the heating plate 43 in contact with the carrier plate serves as a lower electrode plate; during the deposition of the doping layer, the DC bias device DC is electrically connected to the upper electrode plate and outputs a positive DC voltage to the upper electrode plate; or, during the deposition of the doping layer, the DC bias device is electrically connected to the lower electrode plate and outputs a negative DC voltage to the lower electrode plate.

[0076] By applying a DC voltage to the upper electrode plate (gas diffuser) or the lower electrode plate (heating plate or carrier plate) through a DC bias device DC, the sheath thickness can be additionally changed, so that the sheath thickness on the side of the lower electrode plate is thicker and the sheath thickness on the side of the upper electrode plate is thinner, thereby adjusting the electric field strength between the guard edge and the edge of the silicon substrate and the charged ion bombardment effect, thereby controlling the strength of the etching effect.

[0077] As an embodiment, when the N-type doping layer and the P-type doping layer are prepared by using a microcrystal process, during the deposition of the doping layer, Figure 7 As shown, the DC bias device DC is electrically connected to the upper electrode plate (gas diffuser 41) and outputs a positive DC voltage to the upper electrode plate. At this time, the positive DC voltage offsets the sheath voltage near the upper electrode plate, thereby causing the sheath at the upper electrode plate to become thinner. Based on the sheath symmetry theory, the sheath near the lower electrode plate becomes thicker, thereby enhancing the electric field between the carrier plate rib and the edge of the silicon substrate, enhancing the bombardment effect of charged ions on the edge of the silicon substrate, and strengthening the etching effect.

[0078] As another embodiment, when the N-type doping layer and the P-type doping layer are prepared by using a microcrystal process, during the deposition of the doping layer, as shown in FIG. Figure 8 As shown, the DC bias device DC is electrically connected to the lower electrode plate (heating plate 43 or carrier plate 42), and outputs a negative DC voltage to the lower electrode plate. At this time, the negative DC voltage enhances the sheath voltage near the lower electrode plate, and also increases the thickness of the sheath near the lower electrode plate, and also enhances the electric field between the carrier plate rib and the edge of the silicon substrate, enhances the bombardment effect of charged ions on the edge of the silicon substrate, and strengthens the etching effect.

[0079] As a preferred embodiment, the DC power supply of the DC bias device has an output voltage range of 0-1000V, and as the DC voltage increases, the area without wrap-around plating at the edge of the silicon substrate expands.

[0080] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

[0081] It should be understood that in order to simplify the present invention and help those skilled in the art understand the various aspects of the present invention, in the above description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes described in a single embodiment or described with reference to a single figure. However, the present invention should not be interpreted as the features included in the exemplary embodiments are all necessary technical features of the patent claims.

Claims

1. A method for manufacturing a heterojunction solar cell, using a plate-type capacitively coupled plasma enhanced chemical vapor deposition method, comprising the following steps: Providing a doped silicon substrate (10); Forming at least one front passivation layer (11) made of an intrinsic amorphous silicon-based material and at least one back passivation layer (21) made of an intrinsic amorphous silicon-based material on the front and back sides of the silicon substrate (10), respectively; At least one front doping layer (12) made of a microcrystalline silicon-based material or a nanocrystalline silicon-based material and at least one back doping layer (22) made of a microcrystalline silicon-based material or a nanocrystalline silicon-based material are formed on the at least one front passivation layer (11) and the at least one back passivation layer (21), respectively; It is characterized in that During the process of depositing at least one of the front doping layer (12) and the back doping layer (22), the silicon substrate (10) is placed on a carrier, the upper surface of which is provided with one or more silicon substrate accommodating areas, and at least a portion of the periphery of the accommodating areas is provided with a retaining edge (30).

2. The method according to claim 1, characterized in that The ratio of the height of the rib (30) to the thickness of the silicon substrate (10) is in the range of 1:1 to 15:

1.

3. The method according to claim 1, characterized in that The distance between the rib (30) and the edge of the silicon substrate (10) is less than 3 mm.

4. The method according to claim 1, characterized in that: The front doping layer (12) and the back doping layer (22) are prepared by plate-type capacitive coupled plasma enhanced chemical vapor deposition, wherein the frequency of the radio frequency power source is in the range of 2 MHz to 100 MHz, and the power density of the radio frequency power source is in the range of 0.05 to 1 W / cm 2 The process chamber reaction gases include SiH4 and H2, the SiH4:H2 flow ratio is in the range of 1:10 to 1:1000, and the process chamber reaction gas pressure is in the range of 1-20 Torr.

5. The method according to claim 1, characterized in that On the side edge of the heterojunction solar cell, on the edge region of the silicon substrate (10), the film layers are arranged in the following order from inside to outside: at least one front passivation layer (11), at least one back passivation layer (21) on the at least one front passivation layer (11); or At least one front passivation layer (11), at least one back passivation layer (21) on the at least one front passivation layer (11), and at least one front doping layer (12) on the at least one back passivation layer (21); or, At least one front passivation layer (11), at least one back passivation layer (21) on the at least one front passivation layer (11), and at least one back doping layer (22) on the at least one back passivation layer (21); or, at least one back passivation layer (21), at least one front passivation layer (11) on the at least one back passivation layer (21); or At least one back passivation layer (21), at least one front passivation layer (11) on the at least one back passivation layer (21), and at least one front doping layer (12) on the at least one front passivation layer (11); or, At least one back passivation layer (21), at least one front passivation layer (11) on the at least one back passivation layer (21), and at least one back doping layer (22) on the at least one front passivation layer (11).

6. The method according to claim 1, characterized in that The silicon substrate (10) has a first conductive type of doping; in the front doping layer (12) and the back doping layer (22), one of the doping types is the first conductive type, and the other doping type is a second conductive type opposite to the first conductive type.

7. The method according to claim 6, characterized in that It also includes the following sequence of steps: forming at least one transparent back conductive layer on at least one back doping layer (22); forming at least one transparent front conductive layer on at least one front doped layer (12); forming a back electrode on at least one transparent back conductive layer; A front electrode is formed on at least one transparent front conductive layer.

8. A heterojunction solar cell, characterized in that: The structure of the heterojunction solar cell comprises: A doped silicon substrate (10); At least one front passivation layer (11) formed on the front side of the silicon substrate (10) and composed of an intrinsic amorphous silicon-based material; At least one front doping layer (12) formed on the at least one front passivation layer (11) and composed of a microcrystalline silicon-based material or a nanocrystalline silicon-based material; At least one back passivation layer (21) formed on the back side of the silicon substrate (10) and composed of an intrinsic amorphous silicon-based material; At least one back doping layer (22) formed on the at least one back passivation layer (21) and made of a microcrystalline silicon-based material or a nanocrystalline silicon-based material; On the side edge of the heterojunction solar cell, on the edge region of the silicon substrate (10), the order of layers is present from inside to outside in the following order: at least one front passivation layer (11), at least one back passivation layer (21) on the at least one front passivation layer (11); or At least one front passivation layer (11), at least one back passivation layer (21) on the at least one front passivation layer (11), and at least one front doping layer (12) on the at least one back passivation layer (21); or, At least one front passivation layer (11), at least one back passivation layer (21) on the at least one front passivation layer (11), and at least one back doping layer (22) on the at least one back passivation layer (21); or, at least one back passivation layer (21), at least one front passivation layer (11) on the at least one back passivation layer (21); or At least one back passivation layer (21), at least one front passivation layer (11) on the at least one back passivation layer (21), at least one front doping layer (12) on the at least one front passivation layer (11); or, At least one back passivation layer (21), at least one front passivation layer (11) on the at least one back passivation layer (21), and at least one back doping layer (22) on the at least one front passivation layer (11).

9. The solar cell according to claim 8, characterized in that: The silicon substrate (10) has a first conductive type of doping; in the front doping layer (12) and the back doping layer (22), one of the doping types is the first conductive type, and the other doping type is a second conductive type opposite to the first conductive type.

10. The solar cell according to claim 9, characterized in that: The silicon substrate (10) is an N-type textured silicon wafer, the first conductivity type is N-type, and the second conductivity type is P-type; or, The silicon substrate (10) is a P-type textured silicon wafer, the first conductivity type is P-type, and the second conductivity type is N-type.

11. The solar cell according to claim 8, characterized in that at least one transparent front conductive layer formed on the at least one front doped layer (12); at least one transparent back conductive layer formed on the at least one back doping layer (22); a front electrode formed on the at least one transparent front conductive layer; A back electrode is formed on the at least one transparent back conductive layer.

12. A device for manufacturing a heterojunction solar cell, using a plate-type capacitively coupled plasma enhanced chemical vapor deposition method, the device comprising: at least one process chamber for depositing a doping layer, The gas diffuser located inside the process chamber, a radio frequency power source electrically connected to the gas diffuser, Heating plate for heating, It is characterized in that During the deposition of the doped layer, the silicon substrate (10) is placed on a carrier, the upper surface of which is provided with one or more silicon substrate accommodating areas, and at least a portion of the periphery of the accommodating areas is provided with a retaining edge (30).

13. The device according to claim 12, characterized in that The height of the rib (30) is greater than the thickness of the silicon substrate (10), and the ratio of the height of the rib (30) to the thickness of the silicon substrate (10) is in the range of 1:1 to 15:

1.

14. The device according to claim 12, characterized in that The distance between the rib (30) and the edge of the silicon substrate (10) is less than 3 mm.

15. The device according to claim 12, characterized in that The front doping layer (12) and the back doping layer (22) are prepared by plate-type capacitive coupled plasma enhanced chemical vapor deposition, the radio frequency power supply frequency is in the range of 2 MHz-100 MHz, and the radio frequency power supply power density is in the range of 0.05-1 W / cm 2 The process chamber reaction gases include SiH4 and H2, the SiH4:H2 flow ratio is in the range of 1:10 to 1:1000, and the process chamber reaction gas pressure is in the range of 1-20 Torr.

16. The device according to claim 12, characterized in that The device also includes a DC bias device, the gas diffuser (41) serves as an upper electrode plate, and the carrier plate (42) or the heating plate (43) in contact with the carrier plate serves as a lower electrode plate; During the deposition of the doped layer, the DC bias device is electrically connected to the upper electrode plate to output a positive DC voltage to the upper electrode plate; or, During the deposition of the doped layer, the DC bias device is electrically connected to the lower electrode plate and outputs a negative DC voltage to the lower electrode plate.

17. The device according to claim 16, characterized in that It also includes a heating plate lifting mechanism (44). During the deposition of the doped layer, the carrier plate (42) is placed on the heating plate (43), and the heating plate (43) is placed on the heating plate lifting mechanism (44). The distance between the lower electrode plate and the upper electrode plate is adjusted by adjusting the height of the heating plate lifting mechanism (44). During the preparation of the front doped layer (12) and the back doped layer (22), the distance between the upper and lower electrodes is within the range of 5 mm to 50 mm.

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