Silicon wafer and preparation method thereof, solar cell and photovoltaic module

Abstract

The invention provides a silicon wafer, a preparation method of the silicon wafer, a solar cell and a photovoltaic module, and relates to the technical field of photovoltaics. The silicon wafer comprises a first surface and a second surface which are opposite; the resistivity of the first surface is smaller than that of the second surface; the change rate of the radial resistivity of the first surface and / or the second surface is smaller than or equal to 20%. Compared with the prior art, the carrier transmission performance at each position on the same surface is relatively uniform, and the transmission effect of the carriers on the surface is not reduced due to overlarge resistivity at some positions on the same surface, so that the carrier transmission in the silicon substrate of the solar cell is effectively improved, and the efficiency of the solar cell is further improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a silicon wafer and a preparation method thereof, a solar cell and a photovoltaic module. Background Art

[0002] At present, the production process of silicon wafers usually uses the Czochralski method to pull silicon rods, which are then sliced. During the growth of silicon rods, the solid-liquid interface is either a convex liquid surface or a concave liquid surface, and it is difficult to reach a horizontal liquid surface. Moreover, the faster the crystallization rate, the greater the convexity or concavity of the solid-liquid interface. The greater the convexity or concavity, the greater the difference in resistivity between the center and edge of the silicon rod, that is, the greater the radial resistivity change rate of the silicon rod.

[0003] The improvement of solar cell conversion efficiency is inseparable from the support of high-quality silicon wafers. It can be said that, to a certain extent, the quality of silicon wafers determines the conversion efficiency of solar cells.

[0004] However, as mentioned above, the large radial resistivity variation of the silicon rod will result in a large resistivity variation from the center to the edge of the same surface of the obtained silicon wafer, which will restrict further improvement of solar cell efficiency. Summary of the invention

[0005] The present invention provides a silicon wafer and a preparation method thereof, a solar cell and a photovoltaic module, aiming to solve the problem that the resistivity of the same surface of the existing silicon wafer varies greatly from the center to the edge, thus affecting the efficiency improvement of the solar cell.

[0006] A first aspect of the present invention provides a silicon wafer, comprising:

[0007] A first surface and a second surface opposite to each other; the resistivity of the first surface is less than the resistivity of the second surface;

[0008] A change rate of radial resistivity of the first surface and / or the second surface is less than or equal to 20%.

[0009] The resistivity of the first surface and the second surface of the silicon wafer provided by the present application are different. The resistivity of the first surface is less than that of the second surface, that is, a resistivity gradient is roughly formed from the second surface to the first surface. The second surface of the silicon wafer has a high resistivity, and the minority carrier lifetime of the silicon wafer on this surface is higher, and the minority carrier recombination is less; the first surface of the silicon wafer has a low resistivity, which is conducive to the transmission of carriers. The silicon wafer of the present application has the characteristics of high minority carrier lifetime and low resistivity. At the same time, the change rate of radial resistivity on the same surface is less than or equal to 20%, that is, the resistivity distribution on the same surface is relatively uniform, and the carrier transmission performance at various positions on the same surface is relatively uniform. The resistivity at certain positions on the same surface is too large, which will not reduce the transmission effect of the sub-carriers on the surface, thereby effectively improving the minority carrier lifetime and carrier transmission of the solar cell prepared by the silicon wafer, thereby improving the efficiency of the solar cell.

[0010] Optionally, the resistivity of the first surface is greater than or equal to 0.02 Ω.cm, and the resistivity of the second surface is less than or equal to 450 Ω.cm.

[0011] By adopting the technical solution of the present application, the resistivity on the two opposite surfaces of the silicon wafer is within the above-mentioned range, so that the silicon wafer has the characteristics of high minority carrier lifetime and low resistivity at the same time. The resistivity within the above-mentioned range can prevent the difference between the first surface and the second surface of the silicon wafer from being too large, resulting in the electric field between the two surfaces being too strong, thereby increasing the risk of breakdown.

[0012] Optionally, the silicon wafer further includes: a body portion located between the first surface and the second surface;

[0013] In the silicon wafer, the doping concentration of the first surface is greater than the doping concentration of the second surface, and the doping concentration of the first surface is greater than the doping concentration of the main body.

[0014] In the silicon wafer of the present application, the doping concentration of the first surface is greater than the doping concentration of the second surface, and the doping concentration of the first surface is greater than the doping concentration of the main body, that is, a gradient doping is roughly formed from the second surface to the first surface, and the high and low gradient resistivity makes the silicon wafer have better carrier transmission performance, and the resistivity tends to decrease from the second surface to the first surface. When a solar cell is prepared on such a silicon wafer, the majority carriers separated by the PN junction in the cell will be accelerated by the gradient junction electric field from one end of the PN junction to the other end of the silicon wafer due to the existence of the resistivity gradient junction, thereby achieving better carrier transmission in the direction of decreasing gradient doping resistivity, thereby reducing the intrinsic series resistance of the solar cell, and thus improving the efficiency of the solar cell.

[0015] Optionally, the doping concentration of the main body portion decreases from a side close to the first surface to a side close to the second surface.

[0016] By adopting the technical solution of the present application, the doping concentration of the main part of the silicon wafer changes, so that the resistivity changes gradually, the transmission of carriers is improved, and the efficiency of the solar cell can be effectively improved.

[0017] Optionally, the doping concentration of the first surface is less than or equal to 7×10 18 atoms / cm 3 , the doping concentration of the second surface is greater than or equal to 1×10 13 atoms / cm 3 .

[0018] By adopting the technical solution of the present application, the doping concentration of the first surface of the silicon wafer is less than or equal to 7×10 18 atoms / cm 3 The resistance of the silicon wafer will be smaller, so the carrier transmission speed in the silicon wafer will be faster; the doping concentration of the second surface of the silicon wafer is greater than or equal to 1×10 13 atoms / cm 3 The less impurity content in the silicon wafer, the higher the minority carrier lifetime of the silicon wafer. Such silicon wafers have good carrier transmission speed and higher minority carrier lifetime, so the efficiency of the prepared solar cells is higher.

[0019] Optionally, the doping concentration of the first surface is 2×10 15 atoms / cm 3 Up to 5×10 18 atoms / cm 3 , the doping concentration of the second surface is 3×10 13 atoms / cm 3 Up to 1×10 16 atoms / cm 3 .

[0020] By adopting the technical solution of the present application, the doping concentration on the two opposite surfaces of the silicon wafer is within the above range, thereby preventing the difference in doping concentration on the two surfaces of the silicon wafer from causing the electric field between the two surfaces to be too strong, thereby increasing the risk of breakdown.

[0021] Optionally, the silicon wafer is a silicon wafer of a first doping type; when the first doping type is N-type doping, the doping concentration of the first surface is 2×10 16 atoms / cm 3 Up to 6×10 18 atoms / cm 3 , the doping concentration of the second surface is 1×10 13 atoms / cm 3 Up to 5×10 16 atoms / cm 3 ;or,

[0022] When the first doping type is P-type doping, the doping concentration of the first surface is 3×10 16 atoms / cm 3 Up to 7×10 18 atoms / cm 3 , the doping concentration of the second surface is 2×10 14 atoms / cm 3 Up to 6×10 16 atoms / cm 3 .

[0023] A second aspect of the present invention provides a solar cell, comprising: a PN junction and any of the aforementioned silicon wafers;

[0024] The PN junction is located on one side of the second surface.

[0025] By adopting the technical solution of the present application, the PN junction of the solar cell can be located on the side of the second surface with high resistivity. On the one hand, the PN junction of the solar cell is located on the side of the second surface with high resistivity, the resistivity of the side close to the PN junction in the silicon wafer is higher, the reverse breakdown voltage of the PN junction is larger, and the reverse leakage is smaller, thereby improving the conversion efficiency of the solar cell; on the other hand, the resistivity of the second surface is larger, the impurities are less, and the minority carrier lifetime is higher, which can effectively reduce the electron-hole recombination in the second surface and the vicinity of the PN junction, thereby improving the efficiency of the solar cell; on the other hand, the high and low gradient resistivity makes the silicon wafer have better carrier transport performance, and the resistivity tends to decrease from the second surface to the first surface. The majority carriers separated by the PN junction will be accelerated by the gradient junction electric field from one end of the PN junction to the other end of the silicon wafer due to the existence of the resistivity gradient junction, thereby achieving better carrier transport in the direction of the gradient doping resistivity reduction, thereby reducing the intrinsic series resistance of the solar cell, thereby improving the efficiency of the solar cell. In summary, in the present application, the efficiency of the solar cell is improved by the combination of the resistivity of the silicon wafer and the setting of the PN junction.

[0026] Optionally, the silicon wafer is a silicon wafer of a first doping type; the solar cell further comprises: a first doping layer of a second doping type, the first doping layer forming a PN junction of the solar cell on the second surface side of the silicon wafer; or,

[0027] The solar cell further comprises: a second doping layer of a first doping type and a first doping layer of a second doping type, the second doping layer and the first doping layer are sequentially stacked on one side of the second surface, and the first doping layer and the second doping layer form a PN junction of the solar cell;

[0028] The first doping type and the second doping type are different.

[0029] A third aspect of the present invention provides a photovoltaic assembly, comprising: a plurality of any of the aforementioned solar cells.

[0030] A fourth aspect of the present invention provides a method for preparing a silicon wafer, comprising:

[0031] Slicing a silicon rod of a first doping type to obtain a plurality of slices;

[0032] A first doping type of high-temperature diffusion or ion implantation doping is performed on at least one surface of the slice to form a silicon wafer; the silicon wafer comprises: a first surface and a second surface opposite to each other; the resistivity of the first surface is less than the resistivity of the second surface; and the rate of change of radial resistivity of the first surface and / or the second surface is less than or equal to 20%.

[0033] The above-mentioned silicon wafer and preparation method thereof, solar cell and photovoltaic module have the same or similar beneficial effects, and will not be described again here to avoid repetition. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0035] Figure 1 A schematic diagram of doping concentration of a silicon wafer in an embodiment of the present invention is shown.

[0036] Description of the accompanying drawings:

[0037] 1-silicon wafer, 11-first surface, 12-second surface, 13-doping element atoms of the first doping type. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] The minority carrier lifetime and resistivity of silicon wafers are the most important factors affecting the efficiency of solar cells. Generally speaking, silicon wafers with high minority carrier lifetime and low resistivity are the most ideal silicon wafers for solar cells, because high minority carrier lifetime is conducive to reducing minority carrier recombination, and low resistivity is conducive to carrier transmission. However, the higher the doping concentration of silicon wafers corresponding to low resistivity, the more serious the recombination and the lower the minority carrier lifetime. To a certain extent, the minority carrier lifetime and resistivity of silicon wafers are a pair of realistic contradictions, so in order to prepare more efficient solar cells, it is necessary to balance the resistivity and minority carrier lifetime of silicon wafers. Moreover, on the side of the silicon wafer close to the PN junction, the lower the resistivity and the lower the doping concentration, the lower the reverse breakdown voltage of the PN junction, and the greater the reverse leakage, thereby reducing the conversion efficiency of the solar cell, so the resistivity of the silicon wafer cannot be too low, that is, the requirements for the optimal doping concentration of different parts of the silicon wafer in the solar cell are different. Existing silicon wafers are usually prepared by slicing silicon rods obtained by the Czochralski method. Since the solid-liquid interface will have convexity or concavity during the crystal growth process, the resistivity difference between the center and edge of the silicon wafer is large, which affects the quality of the silicon wafer and thus restricts the further improvement of battery efficiency.

[0040] In view of the above technical problems, the present application provides a silicon wafer, referring to Figure 1 The silicon wafer comprises: a first surface 11 and a second surface 12 opposite to each other, one of the first surface 11 and the second surface 12 being a light-facing surface and the other being a backlight surface. During the normal operation of the solar cell, the surface of the silicon wafer 1 that mainly receives light is its light-facing surface, and the backlight surface is opposite to the light-facing surface. The resistivity of the first surface 11 is less than the resistivity of the second surface 12, that is, a gradient resistivity is roughly formed from the second surface 12 to the first surface 11. The change rate of the radial resistivity of the first surface 11 and / or the second surface 12 is less than or equal to 20%, for example, it can also be 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, etc. Here, the change rate of the radial resistivity of only the first surface 11 can be less than or equal to 20%. Alternatively, the change rate of the radial resistivity of only the second surface 12 can be less than or equal to 20%. Alternatively, the radial resistivity change rates of the first surface 11 and the second surface 12 may both be less than or equal to 20%.

[0041] It should be noted that the rate of change of radial resistivity of a surface is: the ratio of the average of multiple resistivities at several positions from the center to the edge of the surface to any resistivity of the multiple resistivities. Alternatively, the radial resistivity change rate can be measured according to the measurement method for the change of radial resistivity of silicon wafers in GB / T11073-2007. Radial resistivity change rate = [(ρa-ρc) / ρc] × 100%. Among them, ρc is the average of at least two resistivities measured at the center point on a surface of the silicon wafer, and ρa is the average of at least four resistivities measured at the midpoint of an edge or at a position 6 mm away from the edge of the center point on the surface of the silicon wafer.

[0042] The resistivity detection in the present application may be carried out by a four-probe method, direct detection by a sorting machine, etc., and the present application does not limit this. The resistivity obtained in the present application may be obtained after detection by a sorting machine.

[0043] In the silicon wafer provided by the present application, due to the different resistivity on the first surface and the second surface of the silicon wafer, by controlling the resistivity on different surfaces of the silicon wafer within a certain range, it can be ensured that the change of resistivity from the center to the edge on the same surface of the silicon wafer is small, and the change rate of radial resistivity on the same surface is less than or equal to 20%, that is, the resistivity distribution on the same surface is relatively uniform, and the carrier transmission performance at various positions on the same surface is relatively uniform, and the resistivity at certain positions on the same surface is not too large, which will reduce the transmission effect of the sub-carriers on the surface, thereby effectively improving the carrier transmission in the silicon substrate of the solar cell, thereby improving the efficiency of the solar cell. At the same time, the resistivity of the first surface is less than the resistivity of the second surface, that is, a gradient resistivity silicon wafer is roughly formed from the second surface to the first surface. The second surface of the silicon wafer adopts a high resistivity, and the minority carrier lifetime of the silicon wafer on this surface is higher, and the minority carrier recombination is less; the first surface of the silicon wafer has a low resistivity, which is conducive to the transmission of carriers. The silicon wafer of the present application has the characteristics of high minority carrier lifetime and low resistivity.

[0044] The silicon wafer is a silicon wafer 1 of a first doping type, that is, the entire silicon wafer has a first doping type, and the first doping type may be N-type or P-type, and the specific doping type is not limited.

[0045] The silicon wafer of the present application has a resistivity of greater than or equal to 0.02Ω.cm on the first surface and a resistivity of less than or equal to 450Ω.cm on the second surface. Since the resistivity on the two opposite surfaces of the silicon wafer is within the above range, the silicon wafer has the characteristics of high minority carrier lifetime and low resistivity at the same time. The resistivity within the above range can prevent the difference between the first surface and the second surface of the silicon wafer from being too large, resulting in an excessively strong electric field between the two surfaces, thereby increasing the risk of breakdown.

[0046] For example, the resistivity of the first surface may be 0.02 Ω.cm, 0.05 Ω.cm, 0.1 Ω.cm, 0.5 Ω.cm, 1 Ω.cm, 2 Ω.cm, 5 Ω.cm, 8 Ω.cm, 10 Ω.cm. The resistivity of the second surface may be 450 Ω.cm, 420 Ω.cm, 400 Ω.cm, 350 Ω.cm, 300 Ω.cm, 250 Ω.cm, 200 Ω.cm, 150 Ω.cm, 120 Ω.cm.

[0047] The silicon wafer 1 further includes: a body portion located between the first surface 11 and the second surface 12, where the body portion is the portion of the silicon wafer 1 other than the first surface 11 and the second surface 12. In the silicon wafer 1, the doping concentration of the first surface 11 is greater than the doping concentration of the second surface 12, and the doping concentration of the first surface 11 is greater than the doping concentration of the body portion. In the silicon wafer 1, the doping concentration of the first surface 11 is the highest, that is, a gradient doping is roughly formed from the second surface 12 to the first surface 11. For example, Figure 1 In the embodiment, the number or density of the doping element atoms 13 of the first doping type in the first surface 11 is significantly greater than the number or density of the doping element atoms 13 of the first doping type in the second surface 12. At the same time, the number or density of the doping element atoms 13 of the first doping type in the first surface 11 is also significantly greater than the number or density of the doping element atoms 13 of the first doping type in the body part. The doping concentration of the first surface is greater than the doping concentration of the second surface, and the doping concentration of the first surface is greater than the doping concentration of the body part, that is, a gradient doping is roughly formed from the second surface to the first surface. The gradient-doped silicon wafer will be able to achieve the same gradient doping from the center to the edge on the same surface of the silicon wafer, which can effectively improve the radial resistivity change rate of the silicon wafer, thereby effectively improving the carrier transmission of the solar cell prepared by the silicon wafer, and then improving the battery efficiency.

[0048] The PN junction of the solar cell is used to separate holes and electrons. The PN junction of the solar cell is located on the second surface 12 side of the silicon wafer 1 , that is, the PN junction of the solar cell is located on the side of the second surface 12 with low doping concentration.

[0049] The technical solution of the present application is as follows: first, the PN junction of the solar cell is located on the side of the second surface 12 with low doping concentration, the side of the silicon wafer close to the PN junction, i.e., the second surface 12, has a higher resistivity, a larger reverse breakdown voltage of the PN junction, and a smaller reverse leakage, thereby improving the conversion efficiency of the solar cell; second, the PN junction of the solar cell is located on the side of the second surface 12 with low doping concentration, and the second surface 12 with low doping concentration has a higher minority carrier lifetime due to the low impurity content, which reduces the recombination probability of electrons and holes, thereby improving the efficiency of the solar cell; third, high and low gradient concentration doping makes the silicon wafer have better carrier transport performance, and the gradient doping from the second surface 12 to the first surface 11 causes the resistivity from the second surface 12 to the first surface 11 to tend to decrease, and the majority carriers separated by the PN junction will be accelerated by the gradient junction electric field from one end of the PN junction to the other end of the silicon wafer 1 due to the existence of the doped gradient junction, thereby achieving better carrier transport in the direction of decreasing gradient doping resistivity, thereby reducing the intrinsic series resistance of the solar cell, thereby improving the efficiency of the solar cell. In summary, in the present application, the efficiency of the solar cell is improved by cooperating with the doping of the silicon wafer 1 and the setting of the PN junction.

[0050] Optionally, the doping concentration of the main body of the silicon wafer 1 decreases from the side close to the first surface 11 of the silicon wafer to the side close to the second surface 12, which enhances the gradient doping from the second surface 12 to the first surface 11, making the tendency of the resistivity reduction from the second surface 12 to the first surface 11 in the silicon wafer 1 more obvious. Due to the existence of the doped gradient junction, the majority of carriers separated by the PN junction will be accelerated by the gradient junction electric field from one end of the PN junction to the other end of the silicon wafer 1, thereby achieving better carrier transmission in the direction of the gradient doping resistivity reduction, further reducing the intrinsic series resistance of the solar cell, and further improving the efficiency of the solar cell. In addition, the above-mentioned change in the doping concentration of the main body of the silicon wafer causes the resistivity to change gradually, improves the transmission of carriers, and can effectively improve the efficiency of the solar cell.

[0051] It should be noted that the doping concentration of the main body of the silicon wafer 1 decreases from the side close to the first surface 11 of the silicon wafer to the side close to the second surface 12. The reduction here means that the doping concentration of the main body of the silicon wafer 1 has a decreasing trend from the side close to the first surface 11 of the silicon wafer to the side close to the second surface 12. The specific reduction method is not limited, and it can be a linear reduction, exponential reduction, logarithmic reduction, etc.

[0052] Optionally, the silicon wafer 1 may include a single crystal silicon wafer. Compared with a polycrystalline silicon wafer, a single crystal silicon wafer has fewer defects, less recombination, and a higher minority carrier lifetime. Moreover, the fewer defects in the single crystal silicon wafer are not directly related to the doping concentration. That is, without affecting the doping concentration or resistivity, a higher minority carrier lifetime is achieved, thereby further improving the efficiency of the solar cell.

[0053] Optionally, the doping concentration of the first surface 11 of the silicon wafer 1 is less than or equal to 7×10 18 atoms / cm 3 The smaller the resistivity of the silicon wafer, the faster the carriers are transmitted in the silicon wafer. The doping concentration of the second surface 12 is greater than or equal to 1×10 13 atoms / cm 3 , the less impurity content in the silicon wafer, the higher the minority carrier lifetime of the silicon wafer, such a silicon wafer has a good carrier transmission speed and a high minority carrier lifetime, so the prepared solar cell has a higher efficiency. At the same time, the doping concentration of the first surface 11 is not too high, which is easy to achieve based on the existing process, and the doping concentration of the second surface 12 is not too low. On the basis of ensuring a high minority carrier lifetime, the resistivity is not too large. That is to say, the doping concentration of the first surface 11 and the second surface 12 is within the corresponding above range, which is not only compatible with the existing process, but also achieves a better balance between the doping concentration or resistivity and the minority carrier lifetime.

[0054] For example, the doping concentration of the first surface 11 of the silicon wafer 1 may be 7×10 18 atoms / cm 3 , 6×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 , 4×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 , 1×10 18 atoms / cm 3 , 0.7×10 18 atoms / cm 3 , 0.5×10 18 atoms / cm 3 , 1×10 17 atoms / cm 3 , 0.9×10 17 atoms / cm 3, 0.5×10 17 atoms / cm 3 , 0.1×10 17 atoms / cm 3 , 1×10 16 atoms / cm 3 , 0.8×10 16 atoms / cm 3 , 0.6×10 16 atoms / cm 3 , 0.5×10 16 atoms / cm 3 The doping concentration of the second surface 12 may be 1×10 13 atoms / cm 3 , 6×10 13 atoms / cm 3 , 5×10 13 atoms / cm 3 ,9×10 13 atoms / cm 3 , 10 14 atoms / cm 3 , 5×10 14 atoms / cm 3 , 8×10 14 atoms / cm 3 , 1×10 15 atoms / cm 3 , 5×10 15 atoms / cm 3 ,9×10 15 atoms / cm 3 , 2×10 16 atoms / cm 3 It should be noted that, in the process of respectively taking values ​​of the two, it is necessary to ensure that the doping concentration of the first surface 11 is greater than the doping concentration of the second surface 12 .

[0055] Furthermore, the doping concentration of the first surface 11 of the silicon wafer 1 may be 2×10 15 atoms / cm 3 Up to 5×10 18 atoms / cm 3 The doping concentration of the second surface 12 can be 3×10 13 atoms / cm 3 Up to 1×10 16 atoms / cm 3, using the technical solution of the present application, the doping concentrations on the two opposite surfaces of the silicon wafer are within the above range, preventing the difference in doping concentrations on the two surfaces of the silicon wafer from causing the electric field between the two surfaces to be too strong, thereby increasing the risk of breakdown. At the same time, the doping concentration range of the first surface 11 is easy to achieve based on the existing process, and the doping concentration range of the second surface 12 is such that the resistivity is not too large while ensuring a relatively high minority carrier lifetime. That is to say, the doping concentrations of the first surface 11 and the second surface 12 are within the corresponding above ranges, which not only have good compatibility with the existing process, but also achieve a better balance between the doping concentration or resistivity and the minority carrier lifetime.

[0056] For example, the doping concentration of the first surface 11 of the silicon wafer 1 may be 4×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 , 1×10 18 atoms / cm 3 , 0.9×10 18 atoms / cm 3 , 0.1×10 18 atoms / cm 3 , 1×10 17 atoms / cm 3 , 0.8×10 17 atoms / cm 3 , 0.4×10 17 atoms / cm 3 , 0.2×10 17 atoms / cm 3 , 1×10 16 atoms / cm 3 , 0.9×10 16 atoms / cm 3 , 0.7×10 16 atoms / cm 3 , 1×10 15 atoms / cm 3 , 2×10 15 atoms / cm 3 The doping concentration of the second surface 12 may be 3×10 13 atoms / cm 3 , 2×10 13 atoms / cm 3 , 1×10 13 atoms / cm 3 , 8×1013 atoms / cm 3 , 5×10 13 atoms / cm 3 , 3×10 13 atoms / cm 3 , 1×10 14 atoms / cm 3 , 5×10 14 atoms / cm 3 ,9×10 14 atoms / cm 3 , 1×10 15 atoms / cm 3 , 4×10 15 atoms / cm 3 , 8×10 15 atoms / cm 3 , 1×10 16 atoms / cm 3 It should be noted that, in the process of respectively taking values ​​of the two, it is necessary to ensure that the doping concentration of the first surface 11 is greater than the doping concentration of the second surface 12 .

[0057] Optionally, when the first doping type is N-type doping, the doping concentration of the first surface 11 is 2×10 16 atoms / cm 3 Up to 6×10 18 atoms / cm 3 , the doping concentration of the second surface 12 is 1×10 13 atoms / cm 3 Up to 5×10 16 atoms / cm 3 For N-type doping, the doping concentrations of the first surface 11 and the second surface 12 are within the above ranges, respectively, and the lifetime of minority carriers and resistivity are better balanced, further improving the efficiency of the solar cell. Moreover, it is more compatible with the existing N-type doping preparation process and is easy to prepare. Or, when the first doping type is P-type doping, the doping concentration of the first surface 11 is 3×10 16 atoms / cm 3 Up to 7×10 18 atoms / cm 3 , the doping concentration of the second surface 12 is 2×10 14 atoms / cm 3 Up to 6×10 16 atoms / cm 3For P-type doping, the doping concentrations of the first surface 11 and the second surface 12 are respectively within the above ranges, and the minority carrier lifetime and resistivity achieve a better balance, further improving the efficiency of the solar cell. Moreover, it is more compatible with the existing P-type doping preparation process and is easy to prepare.

[0058] The crystal rod can be doped at a low concentration during crystal pulling, and then sliced ​​to obtain slices, and then the slices are doped with the same doping element on one side at high temperature or by ion implantation. 13 atoms / cm 3 Up to 5×10 16 atoms / cm 3 concentration doping; 2×10 16 atoms / cm -3 Up to 6×10 18 atoms / cm -3 The concentration of doping is 1×10 13 atoms / cm 3 Up to 5×10 16 atoms / cm 3 , the doping concentration of the first surface 11 is 2×10 16 atoms / cm 3 Up to 6×10 18 atoms / cm 3 For P-type silicon wafers, 2×10 14 atoms / cm -3 Up to 6×10 16 atoms / cm -3 concentration doping, single-sided high-temperature diffusion or ion implantation to obtain 3×10 16 atoms / cm -3 Up to 7×10 18 atoms / cm -3 The doping concentration of the second surface 12 is 2×10 14 atoms / cm 3 Up to 6×10 16 atoms / cm 3 , the doping concentration of the first surface 11 is 3×10 16 atoms / cm 3 Up to 7×10 18 atoms / cm 3 .

[0059] For example, the doping concentration of the first surface 11 of the N-type doped silicon wafer 1 may be 6×1018 atoms / cm 3 、5×10 18 atoms / cm 3 、4×10 18 atoms / cm 3 、3×10 18 atoms / cm 3 、2×10 18 atoms / cm 3 、1×10 18 atoms / cm 3 、0.7×10 18 atoms / cm 3 、0.2×10 18 atoms / cm 3 、1×10 17 atoms / cm 3 、0.6×10 17 atoms / cm 3 、0.5×10 17 atoms / cm 3 、0.1×10 17 atoms / cm 3 、1×10 16 atoms / cm 3 、2×10 16 atoms / cm 3 , the doping concentration of the second surface 12 can be 1×10 13 atoms / cm 3 、7×10 13 atoms / cm 3 、5×10 13 atoms / cm 3 、2×10 13 atoms / cm 3 、10 14 atoms / cm 3 、5×10 14 atoms / cm 3 、8×10 14 atoms / cm 3 、10 15 atoms / cm 3 、3×10 15 atoms / cm 3 、9×10 15 atoms / cm 3 、1×10 16 atoms / cm 3 、2×1016 atoms / cm 3 , 3×10 16 atoms / cm 3 , 4×10 16 atoms / cm 3 , 5×10 16 atoms / cm 3 It should be noted that, in the process of respectively taking values ​​of the two, it is necessary to ensure that the doping concentration of the first surface 11 is greater than the doping concentration of the second surface 12 .

[0060] For another example, the doping concentration of the first surface 11 of the P-type doped silicon wafer 1 may be 7×10 18 atoms / cm 3 , 6×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 , 4×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 , 1×10 18 atoms / cm 3 , 0.5×10 18 atoms / cm 3 , 0.2×10 18 atoms / cm 3 , 1×10 17 atoms / cm 3 , 0.6×10 17 atoms / cm 3 , 0.5×10 17 atoms / cm 3 , 0.2×10 17 atoms / cm 3 , 1×10 16 atoms / cm 3 , 2×10 16 atoms / cm 3 , 3×10 16 atoms / cm 3 The doping concentration of the second surface 12 can be 1×10 14 atoms / cm 3 , 2×10 14 atoms / cm 3 , 5×10 14atoms / cm 3 , 8×10 14 atoms / cm 3 , 10 15 atoms / cm 3 , 5×10 15 atoms / cm 3 ,9×10 15 atoms / cm 3 , 1×10 16 atoms / cm 3 , 2×10 16 atoms / cm 3 , 3×10 16 atoms / cm 3 , 4×10 16 atoms / cm 3 , 5×10 16 atoms / cm 3 , 6×10 16 atoms / cm 3 It should be noted that, in the process of respectively taking values ​​of the two, it is necessary to ensure that the doping concentration of the first surface 11 is greater than the doping concentration of the second surface 12 .

[0061] The present application also provides a solar cell, which includes a PN junction and any of the aforementioned silicon wafers, wherein the PN junction is located on the side of the second surface. In both the first surface and / or the second surface of the silicon wafer, the change rate of the radial resistivity on the same surface is less than or equal to 20%, that is, the resistivity distribution on the same surface is relatively uniform, and the carrier transmission performance at various positions on the same surface is relatively uniform, and the transmission effect of the sub-carriers on the surface will not be reduced due to the excessive resistivity of certain positions on the same surface, thereby effectively improving the carrier transmission in the silicon substrate of the solar cell, thereby improving the efficiency of the solar cell. And the resistivity of the first surface is less than the resistivity of the second surface, that is, a gradient resistivity is roughly formed from the second surface to the first surface, that is, the PN junction of the solar cell is located on the side of the second surface with high resistivity. On the one hand, the PN junction of the solar cell is located on the side of the second surface with high resistivity, the resistivity of the side close to the PN junction in the silicon wafer is higher, the reverse breakdown voltage of the PN junction is larger, and the reverse leakage is smaller, thereby improving the conversion efficiency of the solar cell; on the other hand, the resistivity of the second surface is larger, and the second surface has a higher minority carrier lifetime, which can effectively reduce the electron-hole recombination in the second surface and the area near the PN junction, thereby improving the efficiency of the solar cell; on the third hand, the high and low gradient resistivity makes the base region have better carrier transport performance, and the resistivity tends to decrease from the second surface to the first surface. The majority carriers separated by the PN junction will be accelerated by the gradient junction electric field from one end of the PN junction to the other end of the silicon wafer due to the existence of the resistivity gradient junction, thereby achieving better carrier transport in the direction of the gradient doping resistivity reduction, thereby reducing the intrinsic series resistance of the solar cell, thereby improving the efficiency of the solar cell. In summary, in this application, the efficiency of the solar cell is improved by coordinating the resistivity of the silicon wafer and the setting of the PN junction.

[0062] The solar cell also includes: a first doping layer of a second doping type, located on the side of the second surface 12, the first doping layer and the silicon wafer 1 form a PN junction of the solar cell, that is, the silicon wafer 1 constitutes the PN junction as a part of the PN junction of the solar cell, the first doping type and the second doping type here are different, one is P-type doping, and the other is N-type doping. Alternatively, the solar cell may also include: a second doping layer of a first doping type and a first doping layer of a second doping type, the second doping layer and the first doping layer are sequentially stacked on the side of the second surface, the second doping layer is closer to the second surface 12, and the second doping layer and the silicon wafer 1 have the same doping type, here the first doping layer of the second doping type and the first doping layer of the first doping type together form the PN junction of the solar cell, that is, the silicon wafer 1 here is a part of the PN junction, and a high-low junction is formed by the first doping layer of the first doping type and the second doping layer of the first doping type, here the first doping type and the second doping type are different, one is P-type doping, and the other is N-type doping. The way to form a PN junction in the solar cell is flexible and diverse.

[0063] Optionally, the solar cell may include: crystalline silicon PERC solar cell, crystalline silicon Topcon cell, crystalline silicon HIT cell, crystalline silicon-perovskite stacked solar cell, wherein in the crystalline silicon back contact solar cell, there is basically no electrode on the light-facing side of the silicon wafer, which reduces the shading of the front electrode and further improves the efficiency. The silicon wafer in the crystalline silicon back contact solar cell may be an N-type silicon wafer. In the crystalline silicon bifacial solar cell, electrodes may be provided on both the light-facing side and the backlight side of the silicon wafer. In the crystalline silicon bifacial solar cell, the silicon wafer may be N-type or P-type. For example, the crystalline silicon bifacial solar cell may be a PERC (emitter back passivation) solar cell of a P-type silicon wafer. The structure of the PERC solar cell of the P-type silicon wafer from the light-facing side to the backlight side may be: a front electrode, a front silicon nitride layer, a silicon oxide layer, an N-type doped layer, a P-type silicon wafer, an aluminum oxide layer, a back silicon nitride layer, and a back electrode. The front electrode will sequentially penetrate the front silicon nitride layer and the silicon oxide layer to make electrical contact with the N-type doped layer. The back electrode will sequentially penetrate the back silicon nitride layer and the aluminum oxide layer to make electrical contact with the P-type silicon wafer. For another example, the Topcon (passivated contact) solar cell of the crystalline silicon N-type silicon wafer. The Topcon solar cell of the N-type silicon wafer contains an N-type silicon wafer, and a tunneling oxide layer and a doped polysilicon layer sequentially located on the N-type silicon wafer. For another example, a HIT (crystalline silicon heterojunction) solar cell of a crystalline silicon N-type silicon wafer, and a HIT solar cell of an N-type silicon wafer contain an N-type silicon wafer. In the crystalline silicon-perovskite stacked solar cell here, the crystalline silicon solar cell is located at the bottom, and the perovskite solar cell is stacked on the top of the crystalline silicon solar cell. The crystalline silicon solar cell is mainly responsible for converting visible light and near-infrared light, while the perovskite solar cell is mainly responsible for efficiently converting visible light. The crystalline silicon solar cell may include the aforementioned crystalline silicon Topcon solar cell, HIT solar cell, and BC solar cell.

[0064] The present application also provides a photovoltaic module, which includes a number of any of the aforementioned solar cells. The photovoltaic module may also include a packaging film located on opposite sides of the solar cell, and other structures of the photovoltaic module are not specifically limited. The photovoltaic module has the same or similar beneficial effects as any of the aforementioned solar cells, and will not be described again here to avoid repetition.

[0065] The present application also provides a method for preparing a silicon wafer, which comprises the following process steps.

[0066] Step 101: Slice a silicon rod of a first doping type to obtain a plurality of slices.

[0067] The slice can be obtained by slicing silicon rods. At present, silicon rods are mainly obtained by direct pulling. During the pulling process of the silicon rod, the solid-liquid interface is either a convex liquid surface or a concave liquid surface, and it is difficult to reach a horizontal liquid surface. Moreover, the faster the crystallization rate, the greater the convexity or concavity of the solid-liquid interface. The greater the convexity or concavity, the greater the difference in resistivity between the center and edge of the silicon rod, that is, the greater the radial resistivity inhomogeneity of the silicon rod. Moreover, due to the large difference in resistivity between the center and edge of the silicon rod, the rate of change of the resistivity or doping concentration at different positions on the same surface of the silicon wafer after slicing is large. On the same surface of the silicon wafer, the resistivity or doping concentration at different positions is relatively non-uniform, which will restrict the improvement of the efficiency of solar cells.

[0068] Step 102, performing high-temperature diffusion or ion implantation doping of a first doping type on at least one surface of the slice to form a silicon wafer; the silicon wafer comprises: a first surface and a second surface opposite to each other; the resistivity of the first surface is less than the resistivity of the second surface; and the rate of change of radial resistivity of the first surface and / or the second surface is less than or equal to 20%.

[0069] In the related art, solar cells are prepared directly from sliced ​​slices. Since the resistivity or doping concentration at different positions on the same surface of the slices after slicing varies greatly, the efficiency of the solar cells is restricted. In view of the above technical problems, in the present application, after slicing, by performing high-temperature diffusion or ion implantation doping of a first doping type on at least one surface of the slice, the resistivity of different surfaces of the silicon wafer is changed, so that the resistivity or doping concentration at different positions on the surface can be improved. The resistivity or doping concentration at each position on the same surface of the silicon wafer is more uniform, thereby achieving effective improvement of the silicon wafer carrier transmission of the solar cell, and further improving the efficiency of the solar cell.

[0070] The silicon wafer here may also include two opposite surfaces. The step may be to perform high-temperature diffusion or ion implantation doping of the first doping type on one or both of the two opposite surfaces of the silicon wafer. The surface of the silicon wafer that has been subjected to high-temperature diffusion or ion implantation doping of the first doping type is the surface of the silicon wafer whose radial resistivity change rate is less than or equal to 20%. There is no specific limitation on the depth of the high-temperature diffusion or ion implantation here. In the case where both surfaces are subjected to high-temperature diffusion or ion implantation doping of the first doping type, the process parameters such as the high-temperature diffusion or ion implantation doping time of the first doping type on the first surface are large, so that the resistivity of the first surface is less than the resistivity of the second surface. In the case where only one surface is subjected to high-temperature diffusion or ion implantation doping of the first doping type, the surface that has been subjected to high-temperature diffusion or ion implantation doping of the first doping type is the first surface here.

[0071] The method for forming a solar cell may further include the following step of forming a PN junction on one side of the second surface.

[0072] Here, a PN junction is further prepared on the second surface 12 of the silicon wafer 1. The silicon wafer 1 can be used as a part of the PN junction. The silicon wafer here and the related parts mentioned above can be cross-referenced. The doping layer can be prepared by diffusion and the specific preparation method of the doping layer is not limited.

[0073] The method for preparing the solar cell can prepare any of the aforementioned solar cells. The method for preparing the solar cell and the relevant parts of any of the aforementioned solar cells can refer to each other and can achieve the same or similar beneficial effects. In order to avoid repetition, they will not be described here.

[0074] The present application is further described below in conjunction with specific embodiments.

[0075] Example 1

[0076] The present application adopts ion implantation to prepare silicon wafers, wherein 100 PCS of silicon wafers with a resistivity of 0.1 Ω.cm on the first surface and 450 Ω.cm on the second surface are selected to prepare solar cells, and the average value of the cell conversion efficiency is recorded, as shown in Table 1 below;

[0077] Comparative Example 1

[0078] Different from Example 1, the resistivity of the first surface of the silicon wafer is selected to be 0.01Ω.cm, and the resistivity of the second surface is selected to be 400Ω.cm, and the average value of the battery conversion efficiency is recorded, as shown in Table 1 below;

[0079] Comparative Example 2

[0080] Different from Comparative Example 1, the resistivity of the first surface of the silicon wafer is selected to be 0.1Ω.cm, and the resistivity of the second surface is selected to be 500Ω.cm, and the average value of the battery conversion efficiency is recorded, as shown in Table 1 below;

[0081] Comparative Example 3

[0082] The resistivity of the first surface of the silicon wafer is selected to be 0.01Ω.cm, and the resistivity of the second surface is selected to be 500Ω.cm, and the average value of the battery conversion efficiency is recorded, as shown in Table 1 below;

[0083] Comparative Example 4

[0084] A conventional resistivity range silicon wafer is used, that is, the resistivity range of the silicon wafer is 1.2Ω.cm.

[0085] Table 1: Parameter comparison table of embodiments and comparative examples

[0086]

[0087] From the above data, it can be seen that the radial resistivity change rate of the silicon wafers with different resistivities on the first and second surfaces of Example 1 and Comparative Examples 1 to Comparative Examples 3 is smaller than that of the conventional silicon wafers with constant resistivity. For cells prepared by the same cell preparation process, the smaller the radial resistivity change rate of the silicon wafer is, the more obvious the effect of improving the cell conversion efficiency is.

[0088] Therefore, the silicon wafer of the present application has relatively uniform carrier transport performance at various positions on the same surface, and will not reduce the carrier transport on the surface due to the excessive resistivity at certain positions on the same surface, that is, the radial resistivity change rate of the silicon wafer is small, thereby effectively improving the carrier transport in the silicon substrate of the solar cell, thereby improving the efficiency of the solar cell.

[0089] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0090] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A silicon wafer, characterized in that: include: A first surface and a second surface opposite to each other; the resistivity of the first surface is less than the resistivity of the second surface; A change rate of radial resistivity of the first surface and / or the second surface is less than or equal to 20%.

2. The silicon wafer according to claim 1, characterized in that: The resistivity of the first surface is greater than or equal to 0.02 Ω.cm, and the resistivity of the second surface is less than or equal to 450 Ω.cm.

3. The silicon wafer according to claim 1, characterized in that: The silicon wafer further includes: a body portion located between the first surface and the second surface; In the silicon wafer, the doping concentration of the first surface is greater than the doping concentration of the second surface, and the doping concentration of the first surface is greater than the doping concentration of the main body.

4. The silicon wafer according to claim 3, characterized in that: The doping concentration of the body portion decreases from a side close to the first surface to a side close to the second surface.

5. The silicon wafer according to claim 1, characterized in that: The doping concentration of the first surface is less than or equal to 7×10 18 atoms / cm 3 , the doping concentration of the second surface is greater than or equal to 1×10 13 atoms / cm 3 .

6. The silicon wafer according to claim 1, characterized in that: The doping concentration of the first surface is 2×10 15 atoms / cm 3 Up to 5×10 18 atoms / cm 3 , the doping concentration of the second surface is 3×10 13 atoms / cm 3 Up to 1×10 16 atoms / cm 3 .

7. The silicon wafer according to claim 1, characterized in that: The silicon wafer is a silicon wafer of a first doping type; when the first doping type is N-type doping, the doping concentration of the first surface is 2×10 16 atoms / cm 3 Up to 6×10 18 atoms / cm 3 , the doping concentration of the second surface is 1×10 13 atoms / cm 3 Up to 5×10 16 atoms / cm 3 ; or, When the first doping type is P-type doping, the doping concentration of the first surface is 3×10 16 atoms / cm 3 Up to 7×10 18 atoms / cm 3 , the doping concentration of the second surface is 2×10 14 atoms / cm 3 Up to 6×10 16 atoms / cm 3 .

8. A solar cell, characterized in that: include: PN junction and the silicon wafer according to any one of claims 1 to 7; The PN junction is located on one side of the second surface.

9. The solar cell according to claim 8, characterized in that The silicon wafer is a silicon wafer of a first doping type; The solar cell further comprises: a first doping layer of a second doping type, wherein the first doping layer forms a PN junction of the solar cell on the second surface side of the silicon wafer; or, The solar cell further comprises: a second doping layer of a first doping type and a first doping layer of a second doping type, the second doping layer and the first doping layer are sequentially stacked on one side of the second surface, and the first doping layer and the second doping layer form a PN junction of the solar cell; The first doping type and the second doping type are different.

10. A photovoltaic module, characterized in that: include: A solar cell as claimed in any one of claims 8 to 9.

11. A method for preparing a silicon wafer, characterized in that: include: Slicing a silicon rod of a first doping type to obtain a plurality of slices; Performing high temperature diffusion or ion implantation doping of a first doping type on at least one surface of the slice to form a silicon slice; The silicon wafer comprises: a first surface and a second surface opposite to each other; the resistivity of the first surface is less than the resistivity of the second surface; and the change rate of radial resistivity of the first surface and / or the second surface is less than or equal to 20%.

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