Function safety verification circuit for chip power-on

Abstract

The functional safety verification circuit comprises a level conversion circuit, a main power supply domain and an AON power supply domain, wherein the main power supply domain consists of an MCU (Microprogrammed Control Unit) and a low-voltage domain detection and inspection circuit; the AON power supply domain consists of a power-on detection circuit, an overtime counting circuit group, an initial state circuit, an AON initial state detection circuit and a secondary restart circuit; the AON initial state detection circuit and the low-voltage domain detection and verification circuit carry out CRC verification on the initial state circuit at the same time; the power-on detection circuit detects whether the voltage of the initial state circuit exceeds the detection threshold voltage or not during power-on; the secondary restart circuit is used for judging whether the initial state circuit is restarted or not. According to the invention, two circuits with different power supply domains are combined to carry out CRC verification, and two low-voltage comparators are introduced, so that power-on abnormity can be identified more accurately; and a secondary restart circuit is also arranged, so that the initial state circuit is restarted in time when any power-on problem occurs, the influence on other circuits in the chip is reduced, the necessity of repeated welding is also eliminated, and the efficiency is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of automotive electronic sensor integrated circuits, and in particular to a functional safety verification circuit for powering on a chip. Background Art

[0002] The TPMS sensor in the car tire is powered by a battery, so there is a welding power-on process when the sensor module is produced. During the welding process, due to the consistency distribution of process control, the sensor module will undergo a short unstable power-on process. The duration of this unstable period generally ranges from milliseconds to seconds. As a result, the sensor chip part will switch back and forth between normal operation and abnormal operation during this period of unstable power supply, resulting in greater device loss and increased safety hazards.

[0003] At present, sensor chips often have ultra-low power consumption characteristics due to the need to match the design of service life, and a normally charged area is designed in the chip, also called the AON power domain. The AON power domain is a circuit that will only be reset when the battery is completely powered off, that is, there are some circuit initial states that only rely on one power-on. The detection of voltage stability when the sensor chip is powered on is often performed using the power-on detection circuit in the AON power domain, but this detection efficiency is poor and the accuracy is low, and it cannot control the sensor chip in a timely and accurate manner. For example, complex analog circuits cannot be initialized again by software due to the large number of configuration register tables. However, if the reset is performed after the battery is completely powered off, it is likely to affect the system state and even cause errors in the intermediate calculation process; for another example, after the acceleration sensor is judged to be in motion, it will send wireless data to the ECU at a higher frequency than when it is stationary. If it is also reset after the battery is completely powered off, it will cause unnecessary power consumption and device loss. In addition, the AON power domain and the reset processing after power-on may require re-soldering of the corresponding chip pins to address voltage instability. After each soldering, the test is retested and then soldering is continued, entering a cycle until the requirements are met. This method further reduces work efficiency and seriously prolongs the time spent on actual chip production testing.

[0004] In other words, the current detection measures for power instability on sensor chips include at least the following three problems: 1) The processing is performed only after the power-on is completed, which is too slow and difficult to ensure that the initial circuit in the chip is processed correctly. It is even impossible to avoid the adverse consequences that may have been caused by unstable power-on; 2) The single detection method makes the test results not necessarily accurate; 3) After a problem is detected, repeated welding and repeated retesting may be required, resulting in inefficiency and excessive time consumption. Summary of the invention

[0005] In view of the above three problems, the purpose of the present invention is to propose a functional safety verification circuit for chip power-on, which utilizes circuits in two different power domains to jointly perform CRC verification, so as to identify unstable power-on situations more timely and accurately; on the basis of using the power-on detection circuit in the AON power domain, a fast low-voltage comparator and a slow low-voltage comparator are introduced to more accurately identify power-on anomalies; in addition, a secondary restart circuit is provided to restart the initial state circuit in time when any power-on problem occurs, thereby reducing the impact on other circuits in the chip, eliminating the necessity of repeated welding, and greatly improving efficiency.

[0006] This is achieved through the following technical solutions: A functional safety verification circuit for powering on a chip comprises a level conversion circuit, a main power domain consisting of an MCU and a low-voltage domain detection and verification circuit, and an AON power domain consisting of a power-on detection circuit, a timeout counting circuit group, an initial state circuit, an AON initial state detection circuit and a secondary restart circuit; wherein the AON initial state detection circuit and the low-voltage domain detection and verification circuit are used to simultaneously perform CRC verification on the initial state circuit; the power-on detection circuit is used to detect whether the voltage of the initial state circuit exceeds a detection threshold voltage when power is on; the timeout counting circuit group is used to start timeout counting when the power-on detection circuit detects that the voltage of the initial state circuit exceeds the detection threshold voltage, and then transmit the result of the timeout counting to the secondary restart circuit; the secondary restart circuit determines whether to restart the initial state circuit based on the result of the timeout counting or the result of the CRC verification; the level conversion circuit is used to assist the AON initial state detection circuit and the low-voltage domain detection and verification circuit in performing CRC verification; when the voltage of the initial state circuit does not exceed the detection threshold voltage and there is no abnormality in the CRC verification, the MCU starts to operate.

[0007] By jointly performing CRC check on circuits in two different power domains, unstable power-on situations can be identified more promptly and accurately. On the basis of using the power-on detection circuit in the AON power domain, a fast low-voltage comparator and a slow low-voltage comparator are introduced to more accurately identify power-on anomalies. In addition, a secondary restart circuit is set up to restart the initial state circuit in time when any power-on problem occurs, reducing the impact on other circuits in the chip, eliminating the need for repeated soldering, and greatly improving efficiency.

[0008] Preferably, the timeout counting circuit group includes a timeout counter 1 and a timeout counter 2; both the timeout counter 1 and the timeout counter 2 have a counting value frequency of 32KHz, a width of N bits, and a maximum counting value of 2 NAnd after the power-on detection circuit is released, the count is started at the same time, N is a positive integer; timeout counter 1 adopts subtraction counting, and each time the rising edge of the 32KHz clock signal arrives, the count value decreases once until the count is 0; timeout counter 2 adopts addition counting in the form of asynchronous clock counting, and each time the rising edge of the 32KHz clock signal arrives, the count value increases once until the count is 2 N ; When the CRC check is abnormal, the count of timeout counter 1 is 0 and the count of timeout counter 2 is 2 N , a timeout flag is generated, indicating a timeout overflow, which is used to indicate a restart; when there is no abnormality in the CRC check, the timeout counter is set to 2 N , the second timeout counter is set to 0, and continues counting to wait for the next timeout overflow. Using two different timeout counters for timeout counting can effectively improve the reliability and accuracy of timing. At the same time, the timeout counting result also corresponds to the CRC check result, which can reflect whether there is a power-on abnormality problem.

[0009] Preferably, the initial state circuit includes a FIFO storage area, a sensor measurement register area, a power supply LDO and a low-frequency clock circuit; wherein the power supply LDO is used to power the FIFO storage area, the sensor measurement register area, the low-frequency clock circuit and the MCU; the FIFO storage area and the sensor measurement register area are both used to store the voltage at power-on and initialization-related parameters, which are used as the calculation basis for CRC verification; the low-frequency clock circuit provides a low-frequency clock signal to the low-voltage domain detection and verification circuit via a level conversion circuit. The various parts in the initial state circuit work together to ensure normal initialization and convenient detection of existing faults at power-on.

[0010] Preferably, the AON initial state detection circuit includes a CRC_HV initial state register detection circuit, and the low voltage domain detection and verification circuit includes a CRC_LV initial state register detection circuit; wherein, when the CRC_HV initial state register detection circuit and the CRC_LV initial state register detection circuit are both in normal operation, the CRC_HV initial state register detection circuit uses the CRC16 polynomial to calculate the parameters stored in the FIFO memory and the sensor measurement register area to obtain the CRC_VAL_A result; the CRC_LV initial state register detection circuit also uses the CRC16 polynomial to calculate the parameters stored in the FIFO memory and the sensor measurement register area via the level conversion circuit to obtain the CRC_VAL_B result; the CRC_VAL_B result and the CRC_VAL_A result are XORed, and the result of the XOR operation is used as the result of the CRC verification. The two initial state register detection circuits are used to perform CRC16 polynomial calculations respectively, and finally the result of the CRC verification is obtained. It can be combined with two different power domains to determine whether the voltage is stable when powered on, which greatly improves the accuracy and timeliness of recognition.

[0011] Preferably, the low-voltage domain detection and verification circuit also includes a crystal oscillator circuit, a clock count calibration circuit and an XOR comparison circuit; wherein the crystal oscillator circuit is used to provide a crystal oscillator clock signal; the clock count calibration circuit is used to calibrate the low-frequency clock signal; and the XOR comparison circuit is used to perform an XOR operation. An XOR operation is performed in the low-voltage domain detection and verification circuit, and then the initial state circuit can be restarted in the event of any abnormality, thereby improving the accuracy of recognition.

[0012] Preferably, the crystal oscillator circuit starts to read the timeout count result after power-on, and when the timeout count result is valid, the low-frequency clock circuit is calibrated with the help of the clock count calibration circuit. The crystal oscillator circuit can effectively determine whether clock calibration is required based on the count result, thereby ensuring the synchronous operation of various parts in the chip and avoiding starting calibration when the circuit is unstable, resulting in inaccurate low-frequency clocks, thereby affecting time accuracy.

[0013] Preferably, the AON initial state detection circuit also includes a fast low voltage comparator and a slow low voltage comparator; wherein the fast low voltage comparator is used to detect whether there is a fast power jitter in the initial state circuit; the slow low voltage comparator is used to detect whether there is a slow power jitter in the initial state circuit; when there is a fast power jitter or a slow power jitter, the secondary restart circuit restarts the initial state circuit. The fast low voltage comparator and the slow low voltage comparator can detect different power jitter problems respectively, and then feed back to the secondary restart circuit for restart, reducing the adverse effects of power jitter.

[0014] Preferably, the functional safety verification circuit is applied in the 0.11um~0.18um cmos integrated circuit platform, and the capacity of the FIFO storage area does not exceed 256 bytes. The capacity of the FIFO storage area is limited. For the low-power scenario requirements in the AON area, the 256-byte capacity is a critical selection point for SRAM implementation and FIFO implementation. In terms of power consumption balance, for TPMS scenarios below 0.5uA, the 0.11um process integrated circuit is basically the limit configuration. The choice of reducing power consumption is very critical.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention utilizes circuits in two different power domains to jointly perform CRC verification, which can identify unstable power-on situations more timely and accurately; on the basis of using a power-on detection circuit in the AON power domain, a fast low-voltage comparator and a slow low-voltage comparator are introduced to more accurately identify power-on anomalies; in addition, a secondary restart circuit is provided to restart the initial state circuit in time when any power-on problem occurs, thereby reducing the impact on other circuits in the chip, eliminating the need for repeated welding, and greatly improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of a functional safety verification circuit for powering on a chip; Figure 2 It is a structural schematic diagram of an initial circuit; Figure 3 The schematic diagram is a structural diagram of a low voltage domain detection and verification circuit connected to an AON initial state circuit. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0018] like Figure 1 As shown, it is a structural schematic diagram of a functional safety verification circuit for chip power-on, the functional safety verification circuit includes a level conversion circuit, a main power domain composed of an MCU and a low-voltage domain detection and verification circuit, and an AON power domain composed of a power-on detection circuit, a timeout counting circuit group, an initial state circuit, an AON initial state detection circuit and a secondary restart circuit. The AON initial state detection circuit and the low-voltage domain detection and verification circuit are used to perform CRC verification on the initial state circuit at the same time, and the power-on detection circuit is used to detect whether the voltage of the initial state circuit exceeds the detection threshold voltage when power is on. By using two power domains for joint detection and restarting in time when an abnormality is detected, the power-on abnormality can be accurately identified and the adverse effects can be reduced in time. When the voltage of the initial state circuit does not exceed the detection threshold voltage and there is no abnormality in the CRC verification, it means that there is no power-on abnormality or the power-on abnormality has been resolved. At this time, the MCU starts to operate, that is, the chip starts to operate normally.

[0019] like Figure 2As shown, it is a structural schematic diagram of an initial circuit, and the initial circuit includes a FIFO storage area, a sensor measurement register area, a power supply LDO and a low-frequency clock circuit. The power supply LDO is a low-voltage difference linear regulator used for power supply, which is used to power the FIFO storage area, the sensor measurement register area, the low-frequency clock circuit and the MCU. The power supply LDO also has an external capacitor, such as a 100nf or 1uf capacitor. Due to the filtering and energy storage effect of the capacitor, the low-voltage domain detection and verification circuit can have a longer stable time to ensure the correct verification result. The FIFO storage area and the sensor measurement register area are both used to store the voltage and initialization-related parameters at power-on, which can be used as the calculation basis for CRC verification, and then determine whether the power-on is stable. When the functional safety verification circuit is applied in a 0.11um~0.18um cmos integrated circuit platform, the capacity of the FIFO storage area does not exceed 256 bytes. The capacity of the FIFO storage area does not exceed 256 bytes. Limiting the capacity of the FIFO storage area can read and write data faster, reduce delays, and reduce the use of excessive internal resources and reduce power consumption. For the low-power scenario requirements in the AON area, the 256-byte capacity is a critical selection point for SRAM implementation and FIFO implementation. In terms of power consumption balance, it is basically an extreme configuration for TPMS sensors with a 0.11um process integrated circuit below the 0.5uA scenario, and the choice of reducing power consumption is very critical. The low-frequency clock circuit provides a low-frequency clock signal to the low-voltage domain detection and verification circuit via a level conversion circuit. The various parts of the initial state circuit work together to ensure normal initialization and convenient detection of existing faults when powered on. Initialization-related parameters include the adjustment value of the voltage reference and the configuration option value of the sensor measurement, such as gain amplification, sensor channel selection configuration, and other sensor initialization configurations.

[0020] Both the low-frequency clock circuit and the power supply LDO have enable bits, and the enable bits of both are turned on by default. The basis for judging whether to turn on is the AND operation of multiple registers in the initial circuit, that is, if any one of the multiple registers is 0, it is turned on. The requirements for multiple registers are no less than 16 bits. The correct initial value of each register is that all bits are 0. Only when all bits are 1 does it mean that the low-frequency clock circuit and the power supply LDO are turned off, which can avoid incorrect shutdown caused by incorrect power-on. The center value of the low-frequency clock is 32KHz, but the initial value frequency is set to be slower, less than 32KHz, so as to ensure that the shortest time can be guaranteed when counting overtime.

[0021] In this embodiment, the timeout counting circuit is enabled when the initial state circuit has indicated that the output voltage of the initial state circuit is higher than the detection voltage. The timeout counting circuit group is used to start the timeout counting when the power-on detection circuit detects that the voltage of the initial state circuit exceeds the detection threshold voltage, and then transmits the result of the timeout counting to the secondary restart circuit. The timeout counting circuit group includes timeout counter 1 and timeout counter 2. The counting value frequency of timeout counter 1 and timeout counter 2 is both 32KHz and they are started and stopped at the same time, and the maximum range supports 30 seconds. Timeout counter 1 and timeout counter 2 both have a counting value frequency of 32KHz, Nbit width, and a maximum count value of 2 N And after the power-on detection circuit is released and starts running, the start counting is performed at the same time, N is a positive integer; timeout counter 1 adopts subtraction counting, and each time the rising edge of the 32KHz clock signal arrives, the count value decreases once until the count is 0; timeout counter 2 adopts addition counting in the form of asynchronous clock counting, and each time the rising edge of the 32KHz clock signal arrives, the count value increases once until the count is 2 N ; When the CRC check is abnormal, the count of timeout counter 1 is 0 and the count of timeout counter 2 is 2 N , a timeout flag is generated, indicating a timeout overflow, which is used to instruct the main power domain or initial state circuit to restart; when there is no abnormality in the CRC check, the timeout counter is set to 2 N , timeout counter 2 is set to 0, and continues counting to wait for the next timeout overflow.

[0022] like Figure 3 As shown, it is a structural schematic diagram of a low-voltage domain detection and verification circuit connected to an AON initial state circuit, the AON initial state detection circuit includes a CRC_HV initial state register detection circuit, the low-voltage domain detection and verification circuit includes a CRC_LV initial state register detection circuit, and the level conversion circuit is used to assist the CRC_HV initial state register detection circuit and the CRC_LV initial state register detection circuit to perform CRC verification. The CRC_HV initial state register detection circuit and the CRC_LV initial state register detection circuit will first calculate a set of fixed number CRC values ​​for comparison to confirm that CRC_HV and CRC_LV can currently work normally.

[0023] When the CRC_HV initial state register detection circuit and the CRC_LV initial state register detection circuit are both in normal operation, the CRC_HV initial state register detection circuit uses the CRC16 polynomial to calculate the parameters stored in the FIFO memory and the sensor measurement register area to obtain the CRC_VAL_A result. The CRC_LV initial state register detection circuit also uses the CRC16 polynomial to calculate the parameters stored in the FIFO memory and the sensor measurement register area via the level conversion circuit to obtain the CRC_VAL_B result. The CRC_VAL_B result and the CRC_VAL_A result are subjected to an XOR operation, and the result of the XOR operation is used as the result of the CRC check. When performing the XOR comparison operation, if it is 0, the power-on is correct, that is, the result of the CRC check indicates normal; otherwise, if it is 1, the power-on error, that is, the result of the CRC check indicates an error, and the secondary restart circuit is started to restart and reset the initial state circuit. The result of CRC check is corresponding to the result of timeout calculation. If there is a power-on anomaly, the result of CRC check will also point to an anomaly, and the result of timeout calculation will be output normally. On the contrary, when there is no power-on anomaly, the result of CRC check points to normal, and there is no result of timeout calculation. By using two initial state register detection circuits to perform CRC16 polynomial calculations respectively, the result of CRC check is finally obtained. It can be combined with two different power domains to determine whether the voltage is stable when powered on, which greatly improves the accuracy and timeliness of recognition.

[0024] It should be noted that CRC16 polynomial calculation is a polynomial division, and the form of the polynomial is X 16 +X 12 +X 5 +1. When calculating, if the highest bit is 1, the CRC register is shifted left by one bit and an XOR operation is performed with the above polynomial; if the highest bit is 0, the CRC register is only shifted left by one bit; repeat the above steps until all data bytes are processed and the CRC16 check code can be generated.

[0025] In this embodiment, the low-voltage domain detection and verification circuit also includes a crystal oscillator circuit, a clock count calibration circuit, and an XOR comparison circuit; wherein the crystal oscillator circuit is used to provide a crystal oscillator clock signal; the clock count calibration circuit is used to calibrate the low-frequency clock signal; and the XOR comparison circuit is used to perform an XOR operation. An XOR operation is performed in the low-voltage domain detection and verification circuit, and then the initial state circuit can be restarted in the event of any abnormality, thereby improving the accuracy of recognition.

[0026] In this embodiment, the crystal oscillator circuit starts to read the timeout counting result after power-on. When the timeout counting result is valid, it is considered that the power-on is stable; otherwise, the low-frequency clock circuit is calibrated with the help of the clock counting calibration circuit, so that the low-frequency clock circuit can output a normal and accurate low-frequency clock signal. The crystal oscillator circuit can effectively determine whether clock calibration is required based on the counting result, thereby ensuring the synchronous operation of various parts in the chip, avoiding starting calibration when the circuit is unstable, resulting in inaccurate low-frequency clock, and further affecting time accuracy.

[0027] In this embodiment, the AON initial state detection circuit also includes a fast low-voltage comparator and a slow low-voltage comparator; wherein, the output time of the fast low-voltage comparator is less than 100ns, the purpose is to catch the fast power jitter, and is used to detect whether the initial state circuit has fast power jitter. The width range of the slow low-voltage comparator is 30us-300us, and the typical value at room temperature is around 200us. The purpose is to catch the burrs with a longer width, and is used to detect whether the initial state circuit has slow power jitter. Here, the burrs are also a kind of slow power jitter. The two low-voltage comparators are turned on by default after power-on. After the initial state circuit is running, they are turned off after the default timeout time of 30 seconds. 30 seconds is the estimated time of the maximum impact time that the welding jitter of the chip may have on the corresponding pin under normal conditions. The default timeout time of 30s is set, which does not consume power, but can ensure the normal operation of the AON power domain. The timeout counter group is responsible for counting the timeout time with a low-frequency clock. When the timeout time is generated, a timeout flag is generated and saved to the AON power domain. When the power supply jitters quickly or slowly, the secondary restart circuit will restart the initial state circuit.

[0028] It should be noted that when the CRC check result indicates an abnormality, when the fast low-voltage comparator detects the presence of rapid power supply jitter, and when the slow low-voltage comparator detects the presence of slow power supply jitter, any of the three situations occurs, indicating that an abnormality occurred when the chip was powered on. The secondary restart circuit will restart the initial state circuit, so that the initial state circuit is reset in time to achieve state reset, thereby avoiding the impact of any abnormality as much as possible.

[0029] In summary, the present invention utilizes circuits in two different power domains to jointly perform CRC verification, which can identify unstable power-on situations more timely and accurately; on the basis of using a power-on detection circuit in the AON power domain, a fast low-voltage comparator and a slow low-voltage comparator are introduced to more accurately identify power-on anomalies; in addition, a secondary restart circuit is provided to restart the initial state circuit in time when any power-on problem occurs, thereby reducing the impact on other circuits in the chip, eliminating the need for repeated welding, greatly improving efficiency, and having significant progressiveness.

[0030] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A functional safety verification circuit for powering on a chip, characterized in that: It includes a level conversion circuit, a main power domain composed of an MCU and a low-voltage domain detection and verification circuit, and an AON power domain composed of a power-on detection circuit, a timeout counting circuit group, an initial state circuit, an AON initial state detection circuit, and a secondary restart circuit; Among them, the AON initial state detection circuit and the low-voltage domain detection and verification circuit are used to perform CRC verification on the initial state circuit at the same time; the power-on detection circuit is used to detect whether the voltage of the initial state circuit exceeds the detection threshold voltage when power is turned on; the timeout counting circuit group is used to start the timeout counting when the power-on detection circuit detects that the voltage of the initial state circuit exceeds the detection threshold voltage, and then transmit the result of the timeout counting to the secondary restart circuit; the secondary restart circuit determines whether to restart the initial state circuit based on the result of the timeout counting or the result of the CRC verification; the level conversion circuit is used to assist the AON initial state detection circuit and the low-voltage domain detection and verification circuit in performing CRC verification; when the voltage of the initial state circuit does not exceed the detection threshold voltage and there is no abnormality in the CRC verification, the MCU starts to operate.

2. A functional safety verification circuit for chip power-on according to claim 1, characterized in that: The timeout counting circuit group includes a timeout counter 1 and a timeout counter 2; Among them, both timeout counter 1 and timeout counter 2 have a counting frequency of 32KHz, a width of N bits, and a maximum counting value of 2 N And after the power-on detection circuit is released, the count is started at the same time, N is a positive integer; timeout counter 1 adopts subtraction counting, and each time the rising edge of the 32KHz clock signal arrives, the count value decreases once until the count is 0; timeout counter 2 adopts addition counting in the form of asynchronous clock counting, and each time the rising edge of the 32KHz clock signal arrives, the count value increases once until the count is 2 N ; When the CRC check is abnormal, the count of timeout counter 1 is 0 and the count of timeout counter 2 is 2 N , a timeout flag is generated, indicating a timeout overflow, which is used to indicate a restart; when there is no abnormality in the CRC check, the timeout counter is set to 2 N , timeout counter 2 is set to 0, and continues counting to wait for the next timeout overflow.

3. A functional safety verification circuit for chip power-on according to claim 1, characterized in that: The initial state circuit includes a FIFO storage area, a sensor measurement register area, a power supply LDO and a low-frequency clock circuit; wherein the power supply LDO is used to power the FIFO storage area, the sensor measurement register area, the low-frequency clock circuit and the MCU; the FIFO storage area and the sensor measurement register area are both used to store the voltage at power-on and initialization-related parameters, which are used as the calculation basis for CRC verification; the low-frequency clock circuit provides a low-frequency clock signal to the low-voltage domain detection verification circuit via a level conversion circuit.

4. A functional safety verification circuit for chip power-on according to claim 3, characterized in that: The AON initial state detection circuit includes a CRC_HV initial state register detection circuit, and the low voltage domain detection and verification circuit includes a CRC_LV initial state register detection circuit; Among them, when the CRC_HV initial state register detection circuit and the CRC_LV initial state register detection circuit are in normal operation, the CRC_HV initial state register detection circuit uses the CRC16 polynomial to calculate the parameters stored in the FIFO memory and the sensor measurement register area to obtain the CRC_VAL_A result; the CRC_LV initial state register detection circuit also uses the CRC16 polynomial to calculate the parameters stored in the FIFO memory and the sensor measurement register area via the level conversion circuit to obtain the CRC_VAL_B result; the CRC_VAL_B result and the CRC_VAL_A result are XOR-operated, and the result of the XOR operation is used as the result of the CRC check.

5. A functional safety verification circuit for chip power-on according to claim 4, characterized in that: The low-voltage domain detection and verification circuit also includes a crystal oscillator circuit, a clock count calibration circuit and an XOR comparison circuit; wherein the crystal oscillator circuit is used to provide a crystal oscillator clock signal; the clock count calibration circuit is used to calibrate the low-frequency clock signal; and the XOR comparison circuit is used to perform an XOR operation.

6. A functional safety verification circuit for chip power-on according to claim 5, characterized in that: The crystal oscillator circuit starts to read the timeout counting result after power-on, and when the timeout counting result is valid, the low-frequency clock circuit is calibrated with the help of the clock counting calibration circuit.

7. A functional safety verification circuit for chip power-on according to claim 1, characterized in that: The AON initial state detection circuit also includes a fast low voltage comparator and a slow low voltage comparator; wherein the fast low voltage comparator is used to detect whether there is fast power supply jitter in the initial state circuit; the slow low voltage comparator is used to detect whether there is slow power supply jitter in the initial state circuit; when fast power supply jitter or slow power supply jitter occurs, the secondary restart circuit restarts the initial state circuit.

8. A functional safety verification circuit for chip power-on according to claim 3, characterized in that: The functional safety verification circuit is applied in the 0.11um~0.18um CMOS integrated circuit platform, and the capacity of the FIFO storage area does not exceed 256 bytes.

Images