Heterogeneous hybrid integration method of planar optical waveguide device

Abstract

The invention discloses a heterogeneous hybrid integration method of a planar optical waveguide device, and relates to the technical field of integrated silicon photonics, the method is used for heterogeneous hybrid integration of PLC chips with large waveguide feature size difference in different material systems, and the method comprises the following steps: firstly, carrying out large-angle grinding on a light emitting end of a front-end chip to enable a waveguide to form a reflection angle; a grating coupler is arranged on a front-end chip, a device surface of the front-end chip is opposite to a device surface of a rear-end chip, so that emergent light of the front-end chip can be reflected to the device surface of the rear-end chip and is aligned with the grating coupler on the device surface of the rear-end chip, and finally the two aligned chips are packaged to realize optical interconnection of the two chips. According to the technical scheme, when heterogeneous integration is carried out, emergent light of the front-end chip can be directly aligned to the grating coupler of the rear-end chip, the height difference problem of the two chips does not need to be considered, the problems that in an existing end face coupling technology, the chip height difference is sensitive, and coupling modes are difficult to match are solved, and the coupling efficiency is improved. And the integration level of the discrete device optical network system is effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated silicon photonics, and in particular to a heterogeneous hybrid integration method of planar optical waveguide devices. Background Art

[0002] Silicon-based planar optical waveguide (PLC) technology continues the advantages of high integration and low cost of complementary metal oxide semiconductor (CMOS) technology, but is limited by the material properties of silicon materials and cannot realize all the functions of optical links. Silicon-based heterogeneous integration technology can be compatible with more high-performance optoelectronic materials such as lithium niobate, III-V, silicon dioxide, silicon nitride, yttrium iron garnet, etc. while taking advantage of CMOS. It can realize monolithic integration or heterogeneous hybrid integration of devices such as lasers, modulators, detectors, isolators, and low-loss waveguides, and is the main development direction of optoelectronic integration technology in the future.

[0003] Silicon photonics technology is currently mainly based on the silicon-on-insulator (SOI) material platform. SOI is generally composed of a silicon substrate, a buried oxide layer, and a top silicon layer. After etching the waveguide, a layer of silicon dioxide is generally grown as a cladding. Silicon photonics technology is highly mature, and silicon-based integration of various optoelectronic devices has been achieved, including passive devices such as waveguides, beam splitters, and couplers, as well as active devices such as silicon germanium detectors and silicon modulators. However, the refractive index difference between the silicon waveguide and the silicon dioxide cladding on the SOI platform is large, and the waveguide device has a small characteristic size and high integration. At the same time, it also brings problems such as large device phase error and small process tolerance. It does not have advantages in application fields with high process tolerance requirements, such as arrayed waveguide gratings (AWG). Compared with the silicon-based SOI platform, the silicon dioxide material platform has the advantages of low optical loss, large process tolerance, low material cost, and low process precision requirements. It is compatible with CMOS technology, and the waveguide end face can be well matched with the single-mode fiber mode field. It is one of the advantageous material platforms for manufacturing passive devices such as AWG.

[0004] With the exponential growth of data traffic in global optical network links, the demand for high-speed and large-capacity data transmission has made high-capacity optical communications a research hotspot. In order to expand the communication capacity of optical links, an effective means is to use dense wavelength division multiplexing technology, that is, to simultaneously transmit multiple independent wavelength optical carriers in the same optical waveguide, greatly increasing the data transmission capacity of a single waveguide. This technology has broad application prospects in the fields of microwave photonics, optical communication networks, etc. AWG is a typical integrated PLC device in wavelength division multiplexing technology, with the advantages of small size, large number of channels, and mass production, and has high research and application value.

[0005] At present, AWGs in optical network links mostly exist in the form of discrete devices, which makes the overall volume of optical network systems larger and the integration level lower. Due to the material properties of silicon photonic platforms, it is not suitable to be used to prepare AWG devices. Therefore, heterogeneous integration of silica-based AWG chips and silicon-based SOI optical waveguides is a feasible way to simultaneously take advantage of the technical advantages of the two material platforms and improve the system integration level. Due to the order of magnitude difference in the characteristic dimensions of the PLC chip waveguides of the two material systems, end-face coupling mode matching is difficult, and a specially designed mode spot converter is required, which is difficult to develop. In addition, end-face coupling is more sensitive to chip height differences, and packaging is more difficult. Therefore, it is urgent to propose a new type of heterogeneous integration coupling method to realize the coupling and packaging integration of two PLC chips of different material systems such as silicon-based and silica-based. Summary of the invention

[0006] The purpose of the present application is to provide a method for heterogeneous hybrid integration of PLC chips with greatly different waveguide characteristic dimensions of different material systems, to achieve optical interconnection of two PLC chips, and to solve the problems of difficult mode matching and packaging in existing end-face coupling.

[0007] The technical solution of the present application is to provide a heterogeneous hybrid integration method of a planar optical waveguide device, the method comprising:

[0008] Step 1, preparing a first PLC chip and a second PLC chip of different material systems, wherein the first PLC chip includes a first waveguide structure, and the second PLC chip includes a grating coupler and a second waveguide structure;

[0009] Step 2, using one end of the first PLC chip outputting the optical signal as the grinding end, and determining the grinding angle according to the refractive index of the waveguide materials of the two PLC chips and the optical signal input angle required by the grating coupler, so that the output light of the first PLC chip can be emitted from the device surface of the first PLC chip under the reflection of the grinding end surface;

[0010] Step 3, grinding the end face of the first PLC chip according to the grinding angle to form a smooth reflection waveguide end face, wherein the angle between the device surface of the first PLC chip and the reflection waveguide end face is equal to the grinding angle;

[0011] Step 4, fix the first PLC chip and the second PLC chip in a way that the device surfaces are opposite to each other, align the light output of the first PLC chip to the grating coupler of the second PLC chip, measure the output optical power of the second PLC chip in real time, adjust the position of the first PLC chip, make the output optical power of the second PLC chip reach the maximum value, and determine the relative position of the two PLC chips for optimal coupling;

[0012] Step 5: Package and fix the two PLC chips according to the relative position of optimal coupling.

[0013] Furthermore, a device surface of the first PLC chip is parallel to a device surface of the second PLC chip.

[0014] Furthermore, the expression of the grinding angle in step 2 is:

[0015]

[0016] Wherein, θ is the grinding angle, θ1 is the incident angle required for the second PLC chip grating coupler, the range of θ1 is 10±5°, n1 is the refractive index of the second PLC chip cladding, and n2 is the refractive index of the first PLC chip cladding.

[0017] Furthermore, step 4 specifically includes: fixing the first PLC chip and the second PLC chip on the alignment platform of the high-precision coupling alignment system respectively, arranging the device surfaces of the two chips relative to each other, adjusting the position of the first PLC chip so that its output light is incident on the grating coupler of the second PLC chip, using an optical power meter to monitor the output optical power of the second PLC chip in real time, and adjusting the relative position of the first PLC chip and the second PLC chip using the alignment platform of the high-precision coupling alignment system, wherein the adjustment axes include three translation axes X, Y, and Z and three rotation axes pitch, roll, and yaw, until the output optical power of the second PLC chip reaches a maximum value, and taking the relative position of the two chips when the output optical power of the second PLC chip reaches a maximum value as the relative position for optimal coupling.

[0018] The technical solution of the present application also provides a planar optical waveguide device prepared by a heterogeneous hybrid integration method of a planar optical waveguide device, the device comprising a first PLC chip and a second PLC chip;

[0019] The first PLC chip is used to receive an optical signal from an external light source, and conduct and output the optical signal through a waveguide structure arranged thereon;

[0020] The first PLC chip comprises a first PLC chip PLC device surface and a reflection waveguide end surface, a first waveguide structure is arranged in the first PLC chip PLC device surface, and the reflection waveguide end surface is located at the optical signal output end of the first PLC chip and is used to reflect the light wave output by the first waveguide structure;

[0021] The second PLC chip is used to access the optical signal output by the first PLC chip through the grating coupler arranged thereon, and conduct and output the optical signal through the waveguide structure;

[0022] The second PLC chip includes a second PLC chip PLC device surface, in which a grating coupler and a second waveguide structure are arranged, and the grating coupler is used to receive the output optical signal of the first PLC chip and couple the optical signal into the second waveguide structure.

[0023] Furthermore, the first PLC chip further comprises a first PLC chip substrate, and the PLC device surface of the first PLC chip is arranged on the first PLC chip substrate;

[0024] The end face of the reflection waveguide is formed by grinding each layer of the first PLC chip substrate and the first PLC chip PLC device surface at a predetermined angle, and the angle between the end face of the reflection waveguide and the first PLC chip PLC device surface is the grinding angle.

[0025] Furthermore, the device surface of the first PLC chip is arranged opposite to the device surface of the second PLC chip, and the device surface of the first PLC chip is parallel to the device surface of the second PLC chip.

[0026] Furthermore, the light output from the first PLC chip is irradiated onto the surface of the grating coupler, and the relative position of the first PLC chip and the second PLC chip is an optimal coupling position when the output optical power of the second PLC chip reaches a maximum value.

[0027] Furthermore, the second PLC chip further includes a second PLC chip substrate, and the PLC device surface of the second PLC chip is arranged on the second PLC chip substrate.

[0028] The beneficial effects of this application are:

[0029] The technical solution in the present application grinds the light-emitting end face of the first PLC chip at a large angle to form a reflection angle for the waveguide, and then sets the PLC device face of the first PLC chip relative to the PLC device face of the second PLC chip, so that the emitted light of the first PLC chip after grinding can be reflected to the device face of the second PLC chip, and aligned with the grating coupler in the device face of the second PLC chip, and the two PLC chips after coupling alignment are packaged and solidified to achieve optical interconnection of the two PLC chips. The technical solution in the present application can directly align the light emitted by the front-end chip to the grating coupler of the back-end chip during heterogeneous integration, without considering the height difference between the two chips, avoiding the problems of being sensitive to the chip height difference and the difficulty in coupling mode matching in the existing end face coupling technology, and does not need to set a mode spot converter. The heterogeneous integration method in the technical solution of the present application is simple and easy to implement, and can be applied to heterogeneous hybrid integration of two PLC chips with different material systems and large differences in waveguide characteristic dimensions.

[0030] The technical solution in the present application can maximize the output optical power of the back-end chip by position adjustment when aligning the light output of the front-end chip to the grating coupler of the back-end chip, so that the two chips reach the optimal coupling position, which not only completes the heterogeneous integration but also ensures the performance of the two chip combinations; the technical solution in the present application effectively improves the integration of discrete device optical network systems, reduces packaging difficulty and optical coupling losses, and is beneficial to the overall performance improvement of optical communication optical networks or microwave photonic systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The advantages of the above and / or additional aspects of the present application will become apparent and easily understood in the description of the embodiments in conjunction with the following drawings, in which:

[0032] Figure 1 is a schematic structural diagram of a planar optical waveguide device after heterogeneous hybrid integration using the method of the present application according to an embodiment of the present application;

[0033] Figure 2 is a schematic diagram of the structure of a silicon dioxide-based AWG chip after grinding according to an embodiment of the present application;

[0034] Figure 3 It is a schematic diagram of the incident angle and the emission angle of the light wave when two PLC chips are coupled and aligned according to an embodiment of the present application.

[0035] Among them, 1-first PLC chip substrate, 2-first PLC chip PLC device surface, 21-first waveguide structure, 22-first PLC chip cladding, 3-reflection waveguide end face, 31-grinding angle, 4-second PLC chip substrate, 5-second PLC chip PLC device surface, 51-grating coupler, 52-second waveguide structure, 53-second PLC chip cladding. DETAILED DESCRIPTION

[0036] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0037] In the following description, many specific details are elaborated to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present application is not limited to the specific embodiments disclosed below.

[0038] like Figure 1 As shown, this embodiment provides a heterogeneous hybrid integration method of a planar optical waveguide device, comprising:

[0039] Step 1: prepare a first PLC chip and a second PLC chip of different material systems, wherein the first PLC chip includes a first waveguide structure 21 , and the second PLC chip includes a grating coupler and a second waveguide structure 52 .

[0040] Step 2, use one end of the first PLC chip that outputs the optical signal as the grinding end, and determine the grinding angle according to the refractive index of the waveguide materials of the two PLC chips and the optical signal input angle required by the grating coupler 51. The setting of the grinding angle enables the output light of the first PLC chip to be reflected by the grinding end surface and emitted from the direction of the first PLC chip device surface, so that the output light of the first PLC chip can be irradiated onto the second PLC chip in the subsequent coupling alignment.

[0041] It should be noted that the refraction of light at the interface between two media satisfies the following formula m1sinΦ1=m2sinΦ2, where m1 is the refractive index of the first medium, Φ1 is the incident angle of light in the first medium, m2 is the refractive index of the second medium, and Φ2 is the exit angle of light in the second medium.

[0042] like Figure 3 It is a schematic diagram of the coupling between the first PLC chip and the second PLC chip. The arrow is the path of light. The expression of the grinding angle is:

[0043]

[0044] In the formula, θ is the grinding angle, θ1 is the incident angle required for the second PLC chip grating coupler 51, the range of θ1 is 10±5°, π=180°, n1 is the refractive index of the second PLC chip cladding 53, and n2 is the refractive index of the first PLC chip cladding 22.

[0045] Among them, the calculation process of the grinding angle expression is as follows:

[0046] Assuming that the refractive index of air is n3, the light wave in the first waveguide structure 21 enters the first PLC chip cladding 22 after being reflected by the reflective waveguide end face 3, and then emerges into the air. The light wave is refracted at the interface between the first PLC chip cladding 22 and the air to satisfy the following formula:

[0047] n2sinθ4=n3sinθ3

[0048] Wherein, n2 is the refractive index of the first PLC chip cladding 22, n3 is the refractive index of air, θ4 is the incident angle of light in the first PLC chip cladding 22, and θ3 is the exit angle of light in air;

[0049] The light wave is incident from the air into the second PLC chip cladding 53 and irradiated onto the second PLC chip grating coupler 51. The light wave is refracted at the interface between the air and the second PLC chip cladding 53 to satisfy the following formula:

[0050] n1sinθ1=n3sinθ2

[0051] Where θ2 is the incident angle of light in the air. Since the device surface of the first PLC chip is parallel to the device surface of the second PLC chip, θ2 = θ3, and the equation n2sinθ4 = n1sinθ1 holds, resulting in:

[0052]

[0053] like Figure 3 As shown, from the relationship between the interior angles of a triangle, we get:

[0054] θ4+2θ ＝ 90°

[0055] Substituting θ4 into the equation, we get:

[0056]

[0057] In this embodiment, when the first PLC chip cladding layer 22 is made of SiO2 material, and the second PLC chip cladding layer 53 is also made of SiO2 material, n1=n4 and θ1=θ4 are obtained.

[0058] Step 3, using a grinder to grind the end face of the first PLC chip according to a grinding angle to form a smooth reflection waveguide end face 3, wherein the angle between the device surface of the first PLC chip and the reflection waveguide end face 3 is equal to the grinding angle.

[0059] After the grinding is completed, it is tested whether the angle of the emitted light of the first PLC chip is within the range. If the angle of the emitted light is not within the range, grinding adjustment is performed until the requirements are met.

[0060] In this embodiment, the grinder may be the existing Newfiber FPM-380 grinder, which is a highly efficient precision grinding device commonly used for end face processing of precision optical components.

[0061] Step 4, fix the first PLC chip and the second PLC chip in a manner where their device surfaces are opposite to each other, align the light output of the first PLC chip to the grating coupler 51 of the second PLC chip, measure the output optical power of the second PLC chip in real time, adjust the position of the first PLC chip so that the output optical power of the second PLC chip reaches a maximum value, and determine the relative position of the two PLC chips for optimal coupling; wherein the device surface of the first PLC chip is parallel to the device surface of the second PLC chip.

[0062] The first PLC chip and the second PLC chip are respectively fixed on the alignment platform of the high-precision coupling alignment system by using a clamp or a vacuum nozzle, the device surfaces of the two chips are arranged relative to each other, the position of the first PLC chip is adjusted so that its output light is incident on the grating coupler 51 of the second PLC chip, and the output optical power of the second PLC chip is monitored in real time by using an optical power meter. At the same time, the relative position of the first PLC chip and the second PLC chip is continuously adjusted by using the alignment platform of the high-precision coupling alignment system, wherein the adjustment axes include three translation axes X, Y, and Z and three rotation axes: pitch axis (i.e., rotation around X-axis, usually chip tilting up and down), roll axis (rotation around Y-axis, usually chip tilting left and right), and yaw axis (rotation around Z-axis, usually chip rotation around vertical axis), until the output optical power of the second PLC chip reaches the maximum value, so that the coupling optical power loss between the two chips is minimized, and the relative position of the two chips when the output optical power of the second PLC chip reaches the maximum is taken as the relative position of the optimal coupling.

[0063] In this embodiment, the coupling state of the two PLC chips is determined by observing the reading of the optical power meter. When the output optical power of the second PLC chip reaches the maximum, it is considered that the two PLC chips have reached the optimal coupling state.

[0064] In this embodiment, the high-precision coupling alignment system can adopt the Suruga Precision E2200B series 6-axis fine-tuning stage, which is a device used for high-precision adjustment and positioning, suitable for precision optical coupling scenarios that require delicate fine-tuning; it can provide X, Y, Z axis translation and pitch, roll, yaw and other directions of fine-tuning, achieving simultaneous high-precision adjustment in multiple directions.

[0065] Step 5: Package and fix the two PLC chips according to the relative position of optimal coupling.

[0066] After the coupling alignment is completed, the two chips are packaged and fixed using corresponding gaskets and tube shells according to the relative positions of the best coupling.

[0067] In this embodiment, the gasket and the tube shell are commonly used packaging components, which can fix the chips together at a predetermined position and provide mechanical protection for the chips to maintain the long-term stability of the packaged assembly; wherein, the gasket is a material used to fix the chip position and ensure the precise distance between chips, and the gasket provides support for the chip to prevent chip displacement caused by external force; the tube shell is the external structure of the packaging system, which is used to provide mechanical protection for the package, and the tube shell fixes the gasket and two PLC chips together, and keeps the positions of the two chips from shifting through a precisely designed inner cavity.

[0068] In this embodiment, the PLC chips of the two material systems usually have a large characteristic size difference, which is more than one order of magnitude. When conventional end-face coupling is performed, the two chips are more sensitive to the height difference, the mode matching between the chips, and the packaging difficulty are relatively large, making heterogeneous integration difficult to complete or the coupling effect is poor. When the method of the present invention is used for heterogeneous integration, there is no need to consider the height difference between the two chips. The light output of the front-end chip can be directly aligned to the grating coupler 51 of the back-end chip, and the output optical power of the back-end chip can be adjusted to the maximum by position adjustment, that is, the heterogeneous integration is completed, and the performance of the two chip assemblies can be guaranteed. The coupling method of the present invention avoids the difficulties of heterogeneous integration in existing coupling methods, and can effectively improve the integration of discrete device optical network systems.

[0069] like Figures 1 to 2 As shown, this embodiment also provides a planar optical waveguide device prepared by using the above-mentioned heterogeneous hybrid integration method of the planar optical waveguide device, and the device includes a first PLC chip and a second PLC chip.

[0070] The first PLC chip is used to receive optical signals from an external light source and conduct and output the optical signals through a first waveguide structure 21 arranged thereon; the first PLC chip includes a first PLC chip substrate 1, a first PLC chip PLC device surface 2 and a reflective waveguide end surface 3.

[0071] The first PLC chip substrate 1 is located at the bottom of the first PLC chip and is used to provide support for the first PLC chip as a whole.

[0072] The first PLC chip PLC device surface 2 is arranged on the first PLC chip substrate 1. The first PLC chip PLC device surface 2 includes at least an upper cladding layer, a core layer and a lower cladding layer from top to bottom. A first waveguide structure 21 is arranged in the core layer. The first waveguide structure 21 is used to guide the optical signal to propagate in space.

[0073] In this embodiment, the cladding, core layer and lower cladding can be stacked layer by layer on the substrate of the chip through existing material deposition and etching processes, and the first waveguide structure 21 in the core layer can be prepared on the first PLC chip substrate 1 through existing epitaxy, photolithography, etching, stripping and other process flows, which will not be repeated here.

[0074] The reflecting waveguide end face 3 is located at the optical signal output end of the first PLC chip. It is a smooth and flat end face, which is used to reflect the light waves output by the first waveguide structure 21; the reflecting waveguide end face 3 is formed by grinding each layer of the first PLC chip substrate 1 and the first PLC chip PLC device surface 2 at a predetermined angle, wherein the angle between the reflecting waveguide end face 3 and the first PLC chip PLC device surface 2 is a grinding angle 31.

[0075] In this embodiment, in order to realize the reflection of light at the end face of the waveguide of the first PLC chip, it is necessary to perform large-angle grinding on the end face of the first PLC chip. During the grinding, the various layers of the PLC device surface and the substrate of the first PLC chip are ground at the same time to ensure that the interface is smooth and flat, so that the end face formed by grinding can reflect the light output by the first waveguide structure 21, thereby reducing the light loss caused by scattering, refraction factors, etc.

[0076] The second PLC chip is used to access the optical signal output by the first PLC chip through the grating coupler arranged thereon, and to conduct and output the optical signal through the second waveguide structure 52; the second PLC chip includes a second PLC chip substrate 4 and a second PLC chip PLC device surface 5.

[0077] The second PLC chip substrate 4 is located at the bottom of the second PLC chip and is used to provide support for the second PLC chip as a whole.

[0078] The second PLC chip PLC device surface 5 is arranged on the second PLC chip substrate 4, and the second PLC chip PLC device surface 5 includes at least an upper cladding, a core layer and a lower cladding from top to bottom, and a grating coupler 51 and a second waveguide structure 52 are arranged in the core layer; the grating coupler 51 is used to receive the output optical signal of the first PLC chip and couple the optical signal to the second waveguide structure 52. Specifically, when the optical signal is incident on the surface of the grating coupler 51, the grating structure of the grating coupler 51 guides the optical signal to the second waveguide structure 52 by changing the propagation path and diffraction angle of the optical signal; the second waveguide structure 52 is used to guide the optical signal to propagate in space.

[0079] In this embodiment, the grating coupler 51 and the second waveguide structure 52 in the core layer can be prepared on the second PLC chip substrate 4 through existing epitaxy, photolithography, etching, stripping and other process flows, which will not be described in detail here.

[0080] When the first PLC chip and the second PLC chip are packaged, they are arranged in a manner that the device surfaces are opposite to each other, and the device surface 2 of the first PLC chip is parallel to the device surface 5 of the second PLC chip; the first PLC chip and the second PLC chip are arranged at an optimal coupling position, wherein the light output from the first PLC chip is irradiated to the surface of the grating coupler 51 on the second PLC chip, and the output optical power of the second PLC chip reaches a maximum value.

[0081] In this embodiment, after the first PLC chip and the second PLC chip are coupled and aligned, the two chips are packaged and fixed using corresponding gaskets and tube shells according to the relative positions of the two PLC chips; since PLC chips are very sensitive to temperature, temperature changes may cause changes in their performance, such as power transmission efficiency, bandwidth, stability, etc., a thermoelectric cooler TEC (Thermoelectric Cooler, a device based on thermoelectric effect, used to achieve heat transfer and temperature control) can be set outside the packaging assembly after packaging and fixing, and the thermoelectric cooler TEC is used for temperature control to keep the internal temperature of the packaging assembly stable and improve the reliability of the device.

[0082] Example: Taking a silica-based AWG chip and a silicon-based SOI waveguide chip as an example, the method of the present invention is used to perform heterogeneous hybrid integration of the silica-based AWG chip and the silicon-based SOI waveguide chip.

[0083] The silica-based AWG chip adopts a silicon-based substrate, on which a PLC device surface is arranged. The device surface includes a lower cladding layer, a core layer and an upper cladding layer from bottom to top, and the waveguide structure of the silica-based AWG chip is located in the core layer. Specifically, a lower cladding layer of silica material is first arranged on the silicon-based substrate by processes such as thermal oxidation, and then epitaxial growth of the core layer material is performed by plasma enhanced chemical vapor deposition (PECVD). Then, according to the photolithography pattern of the predetermined PLC structure, the waveguide structure of the silica-based AWG chip is prepared in the core layer by processes such as ultraviolet lithography, electron beam exposure or inductively coupled plasma etching (ICP), and the size of the waveguide structure is about 6μm×6μm. Finally, a doped upper cladding layer is made by PECVD.

[0084] In order to realize the reflection of light on the waveguide end face of the silica-based AWG chip, the end face of the light-emitting end is ground at a large angle, and the layers of the device surface and the substrate are ground at the same time to ensure that the interface is smooth and flat; according to the refractive index of the silica-based AWG chip, the refractive index of the silicon-based SOI waveguide chip and the input angle of the grating coupler, the grinding angle of the silica-based AWG chip is determined. In this example, the incident angle required for the second PLC chip grating coupler is 8°. According to the expression of the grinding angle in the above step 2, the grinding angle θ=41° is calculated, and the grinding angle of the silica-based AWG chip is set to 41°.

[0085] The silicon-based SOI waveguide chip adopts a silicon substrate, on which a PLC device surface is arranged, which includes a lower cladding layer, a core layer and an upper cladding layer from bottom to top, and the grating coupler and waveguide structure of the silicon-based SOI waveguide chip are located in the core layer; specifically, a 2-3 μm thick SiO2 buried oxide layer is arranged on the silicon substrate as the lower cladding layer, a silicon with a thickness of about 220 nm and a size of about 220 nm×500 nm is used as the waveguide core layer, and a layer of 1-3 μm thick SiO2 is grown by PECVD as the upper cladding layer; wherein, the waveguide structure and the grating coupler are manufactured on the core layer by photolithography or etching, the grating tooth width of the grating coupler is about 315 nm, the duty cycle is 1:1, and the coupling angle for a wavelength of 1550 nm is 8°. Since the waveguide and grating tooth line widths of the silicon-based SOI waveguide chip are relatively small, deep ultraviolet lithography or electron beam exposure is used for photolithography, and ICP (Inductively Coupled Plasma Etching) process is used for etching.

[0086] During coupling alignment, a vacuum suction nozzle is used to adsorb the silica-based AWG chip invertedly, and the silicon-based SOI waveguide chip is clamped on the vacuum adsorption sample stage. The light output of the silica-based AWG chip is aligned to the silicon-based SOI waveguide chip grating coupler through a high-precision coupling alignment system. An optical power meter is set at the output end of the silicon-based SOI waveguide chip, and the coupling state of the two PLC chips is determined by observing the reading of the optical power meter. The maximum value of the optical power meter reading indicates that the two PLC chips have reached the best coupling state. During the alignment process, the relative positions of the two chips need to be adjusted through a high-precision coupling alignment system, including the angles of the three translation axes of X, Y, and Z and the three rotation axes of pitch, roll, and yaw, so that the optical power meter reading reaches the maximum, that is, the coupling loss is minimized, among which the optimal coupling loss is less than 5dB per end face. When aligning the multi-channel coupling of two PLC chips, the waveguide spacing of the silica-based AWG chip and the grating coupler spacing of the silicon-based SOI waveguide chip can be set to 127μm, and a reference waveguide is designed to align the corresponding channel of the silica-based AWG chip with the reference waveguide. The coupling position of the two PLC chips is determined by monitoring the output optical power of the reference waveguide.

[0087] After coupling alignment, the two chips are packaged and fixed using corresponding gaskets and tube shells based on the relative positions of the two PLC chips. Since AWG is a temperature-sensitive chip, TEC is required to control the temperature of the package assembly.

[0088] In this example, Figure 1 The schematic diagram of the structure of the silicon dioxide-based AWG chip after grinding. The dotted line in the figure is the path of light in the silicon dioxide-based AWG chip and after reflection on the end face. Figure 2The position relationship shown in the figure is for heterogeneous integration and vertical coupling. The upper part of the figure is the silicon dioxide-based AWG chip, and the lower part is the silicon-based SOI waveguide chip. The dotted line in the figure is the light propagation path after the two PLC chips are heterogeneously integrated. The PLC device surfaces of the two chips are placed opposite each other during packaging.

[0089] The steps in this application can be adjusted in order, combined, and deleted according to actual needs.

[0090] The units in the device of the present application can be combined, divided and deleted according to actual needs.

[0091] Although the present application is disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and are not intended to limit the application of the present application. The scope of protection of the present application is defined by the appended claims and may include various modifications, alterations and equivalents made to the invention without departing from the scope and spirit of the present application.

Claims

1. A method for heterogeneous hybrid integration of planar optical waveguide devices, characterized in that: The heterogeneous hybrid integration method of the planar optical waveguide device comprises: Step 1, preparing a first PLC chip and a second PLC chip of different material systems, wherein the first PLC chip includes a first waveguide structure (21), and the second PLC chip includes a grating coupler (51) and a second waveguide structure (52); Step 2, using one end of the first PLC chip outputting the optical signal as the grinding end, and determining the grinding angle according to the refractive index of the waveguide materials of the two PLC chips and the optical signal input angle required by the grating coupler (51), so that the output light of the first PLC chip can be emitted from the device surface of the first PLC chip under the reflection effect of the grinding end surface; Step 3, grinding the end face of the first PLC chip according to a grinding angle to form a smooth reflection waveguide end face (3), wherein the angle between the device surface of the first PLC chip and the reflection waveguide end face (3) is equal to the grinding angle; Step 4, fixing the first PLC chip and the second PLC chip in a manner that the device surfaces are opposite to each other, aligning the light output of the first PLC chip to the grating coupler (51) of the second PLC chip, measuring the output optical power of the second PLC chip in real time, adjusting the position of the first PLC chip so that the output optical power of the second PLC chip reaches a maximum value, and determining the relative position of the two PLC chips for optimal coupling; Step 5: Package and fix the two PLC chips according to the relative position of optimal coupling.

2. The heterogeneous hybrid integration method of planar optical waveguide devices according to claim 1, characterized in that: The device surface of the first PLC chip is parallel to the device surface of the second PLC chip.

3. The heterogeneous hybrid integration method of planar optical waveguide devices according to claim 2, characterized in that: The expression of the grinding angle in step 2 is: Wherein, θ is the grinding angle, θ1 is the incident angle required by the second PLC chip grating coupler (51), the range of θ1 is 10±5°, n1 is the refractive index of the second PLC chip cladding (53), and n2 is the refractive index of the first PLC chip cladding (22).

4. The heterogeneous hybrid integration method of planar optical waveguide devices according to claim 2, characterized in that: The step 4 specifically includes: The first PLC chip and the second PLC chip are respectively fixed on an alignment platform of a high-precision coupling alignment system, the device surfaces of the two chips are arranged relative to each other, the position of the first PLC chip is adjusted so that its output light is incident on the grating coupler (51) of the second PLC chip, the output optical power of the second PLC chip is monitored in real time by an optical power meter, and the relative position of the first PLC chip and the second PLC chip is adjusted by the alignment platform of the high-precision coupling alignment system, wherein the adjustment axis includes three translation axes of X, Y, and Z and three rotation axes of pitch axis, roll axis, and yaw axis, until the output optical power of the second PLC chip reaches a maximum value, and the relative position of the two chips when the output optical power of the second PLC chip reaches a maximum value is used as the relative position of optimal coupling.

5. A planar optical waveguide device manufactured by the heterogeneous hybrid integration method of a planar optical waveguide device according to any one of claims 1 to 4, characterized in that: The planar optical waveguide device comprises a first PLC chip and a second PLC chip; The first PLC chip is used to receive an optical signal from an external light source, and conduct and output the optical signal through a waveguide structure arranged thereon; The first PLC chip comprises a first PLC chip PLC device surface (2) and a reflection waveguide end surface (3); a first waveguide structure (21) is arranged in the first PLC chip PLC device surface (2); the reflection waveguide end surface (3) is located at the optical signal output end of the first PLC chip and is used to reflect the light wave output by the first waveguide structure (21); The second PLC chip is used to access the optical signal output by the first PLC chip through the grating coupler arranged thereon, and conduct and output the optical signal through the waveguide structure; The second PLC chip comprises a second PLC chip PLC device surface (5), in which a grating coupler (51) and a second waveguide structure (52) are arranged, and the grating coupler (51) is used to receive the output optical signal of the first PLC chip and couple the optical signal into the second waveguide structure (52).

6. The planar optical waveguide device according to claim 5, characterized in that: The first PLC chip further comprises a first PLC chip substrate (1), and the first PLC chip PLC device surface (2) is arranged on the first PLC chip substrate (1); The reflection waveguide end face (3) is formed by grinding each layer of the first PLC chip substrate (1) and the first PLC chip PLC device surface (2) at a predetermined angle, and the angle between the reflection waveguide end face (3) and the first PLC chip PLC device surface (2) is a grinding angle (31).

7. The planar optical waveguide device according to claim 5, characterized in that: The device surface (2) of the first PLC chip and the device surface (5) of the second PLC chip are arranged opposite to each other, and the device surface (2) of the first PLC chip and the device surface (5) of the second PLC chip are parallel to each other.

8. The planar optical waveguide device according to claim 5, characterized in that: The light output from the first PLC chip is irradiated onto the surface of the grating coupler (51), and the relative position of the first PLC chip and the second PLC chip is an optimal coupling position when the output optical power of the second PLC chip reaches a maximum value.

9. The planar optical waveguide device according to claim 5, characterized in that: The second PLC chip further comprises a second PLC chip substrate (4), and the second PLC chip PLC device surface (5) is arranged on the second PLC chip substrate (4).

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