Function safety test circuit and method, neural network processor and storage medium

Abstract

The invention discloses a function safety test circuit and method, a neural network processor and a storage medium, and relates to the technical field of function safety, and the function safety test circuit comprises a configurator which is used for generating and outputting configuration information for testing a to-be-tested integrated circuit; the plurality of test data generators are used for generating and outputting first test data respectively corresponding to each test data generator in the plurality of test data generators based on the configuration information; the to-be-tested integrated circuit is used for processing the plurality of first test data to obtain and output a plurality of second test data; and the first comparator is used for comparing the consistency of the plurality of second test data to obtain a first test result of the integrated circuit to be tested. According to the technical scheme, the whole to-be-tested integrated circuit can be covered, the expected functional safety standard requirement is met, parity check bits do not need to be added to the transmission data of the to-be-tested integrated circuit, the area overhead can be saved, and the transmission power consumption can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a functional safety test circuit, method, device and storage medium. Background Art

[0002] At present, the functional safety (FuSa) test of integrated circuits is mainly carried out by parity check. When the integrated circuit is tested by the parity check method, it is necessary to add parity check bits to the transmission data in the integrated circuit, so as to detect possible faults in the line used for data transmission through the transmission data with the added parity check bits. However, the parity check method can only detect whether the line used for data transmission in the integrated circuit is abnormal, and cannot detect whether the operation circuit used for logical operation of the transmission data in the integrated circuit fails. Therefore, in the case where the integrated circuit includes an operation circuit, it is very easy to fail to meet the expected functional safety standards by performing FuSa testing by the parity check method. In addition, when the integrated circuit is tested by the parity check method, it is necessary to add parity check bits to the transmission data, which leads to a large area overhead of the integrated circuit and high power consumption of data transmission. Summary of the invention

[0003] The current functional safety test circuits cannot meet the expected functional safety standards, and the data transmission power consumption is high and the circuit area overhead is large.

[0004] In order to solve the above technical problems, the present disclosure provides a functional safety test circuit, comprising:

[0005] A configurator, used to generate configuration information for testing the integrated circuit under test and output the configuration information;

[0006] A plurality of test data generators are coupled to the configurator and are used to generate and output a plurality of first test data corresponding to each of the plurality of test data generators based on the configuration information;

[0007] The integrated circuit to be tested is coupled to the plurality of test data generators and is used to process the plurality of first test data to obtain and output a plurality of second test data;

[0008] The first comparator is coupled to the integrated circuit to be tested and is used to compare the consistency of a plurality of second test data to obtain a first test result of the integrated circuit to be tested.

[0009] A second aspect of the present disclosure provides a functional safety testing method for an integrated circuit, comprising:

[0010] generating, by a configurator, configuration information for testing the integrated circuit under test;

[0011] Generate, by means of multiple test data generators based on the configuration information, multiple first test data corresponding to each of the multiple test data generators;

[0012] Processing the plurality of first test data by the integrated circuit to be tested to obtain a plurality of second test data;

[0013] The consistency of the plurality of second test data is compared by the first comparator to obtain a first test result of the integrated circuit to be tested.

[0014] According to a third aspect of the present disclosure, a neural network processor is provided, which includes at least one functional safety test circuit according to the first aspect.

[0015] According to a fourth aspect of the present disclosure, an electronic device is provided, the electronic device comprising:

[0016] A memory for storing processor executable instructions;

[0017] The processor is used to read the executable instructions from the memory and execute the executable instructions to implement the functional safety testing method for integrated circuits of the second aspect.

[0018] According to a fifth aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program for executing the functional safety testing method for integrated circuits according to the second aspect.

[0019] The functional safety test circuit provided by the embodiment of the present disclosure can determine the first detection result of the integrated circuit under test based on the consistency of the obtained multiple second test data by only processing the multiple first test data by the integrated circuit under test, thereby realizing the FuSa test of the circuit in the integrated circuit under test. When the safety test circuit provided by the present disclosure performs functional safety testing on the integrated circuit under test, it can not only meet the expected functional safety standards, but also does not need to add parity bits to the transmission data of the integrated circuit under test, thereby reducing the area overhead of the integrated circuit and reducing the power consumption of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural schematic diagram of a functional safety test circuit for FuSa protection through a parity check scheme provided by an exemplary embodiment of the present disclosure.

[0021] Figure 2 It is a structural schematic diagram of a functional safety test circuit provided by an exemplary embodiment of the present disclosure.

[0022] Figure 3It is a structural schematic diagram of another functional safety test circuit provided by an exemplary embodiment of the present disclosure.

[0023] Figure 4 It is a structural schematic diagram of another functional safety test circuit provided by an exemplary embodiment of the present disclosure.

[0024] Figure 5 It is a structural schematic diagram of another functional safety test circuit provided by an exemplary embodiment of the present disclosure.

[0025] Figure 6 It is a structural schematic diagram of another functional safety test circuit provided by an exemplary embodiment of the present disclosure.

[0026] Figure 7 It is a schematic diagram of an implementation flow of a functional safety testing method for an integrated circuit provided by an exemplary embodiment of the present disclosure.

[0027] Figure 8 It is a schematic diagram of an implementation flow of another integrated circuit functional safety testing method provided by an exemplary embodiment of the present disclosure.

[0028] Fig. 9 It is a schematic diagram of an implementation flow of another integrated circuit functional safety testing method provided by an exemplary embodiment of the present disclosure.

[0029] Fig.10 It is a schematic diagram of an implementation flow of another integrated circuit functional safety testing method provided by an exemplary embodiment of the present disclosure.

[0030] Fig.11 It is a structural diagram of a neural network processor provided by an exemplary embodiment of the present disclosure.

[0031] Fig.12 It is a structural schematic diagram of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0033] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0034] Application Overview

[0035] In the field of integrated circuits, the FuSa mechanism is an important technical means to ensure that integrated circuit systems (eg, System on Chip (SOC)) can operate safely and reliably. Generally, different FuSa test methods can be used for circuits with different functions and characteristics in the integrated circuit system.

[0036] In the related art, for integrated circuits with relatively simple logic, more operation circuits, and relatively large circuit area, the parity check method is mainly used for FuSa testing. Taking the tensor computing core (tesnor core) in the neural network processor as an example, when the tensor computing core is FuSa tested by the parity check method, it is necessary to add parity check bits to the transmission data of the tensor computing core during actual operation, and detect whether the line used for data transmission is faulty based on the transmission data with the added parity check bits, so as to realize the FuSa test of the tensor computing core.

[0037] Figure 1 1 is a schematic diagram of a functional safety test circuit for performing a FuSa test by a parity check method provided by an exemplary embodiment of the present disclosure. The functional safety test circuit 10 is used to perform a FuSa test on a tensor computing core 11. Figure 1 As shown, the functional safety test circuit 10 may include a first operation circuit 101, an encoder 103, a decoder 104 and a second operation circuit 102 coupled in sequence. The tensor computing core 11 includes the first operation circuit 101 and the second operation circuit 102. The encoder 103 and the decoder 104 are detection circuits arranged between the first operation circuit 101 and the second operation circuit 102 when the tensor computing core 11 is subjected to a FuSa test.

[0038] The following describes the process of performing FuSa testing on the tensor computing core 11 using a parity check method.

[0039] First, the encoder 103 adds a parity check bit to the output signal SIG_0 of the first operation circuit 101 to obtain and output the encoded signal SIG_1. Then, the decoder 104 decodes the encoded signal SIG_1 to obtain a decoded signal SIG_2 and outputs it to the second operation circuit 102. The second operation circuit 102 performs corresponding operation processing on the decoded signal SIG_2 to obtain and output an operation signal SIG_3.

[0040] When performing FuSa testing on the tensor computing core 11, the decoder 104 can also calculate the number of logic values ​​"1" in the received coding signal SIG_1 to determine the parity of the received SIG_1; and based on the consistency of the parity represented by the number of logic values ​​"1" and the parity represented by the parity check bit, determine whether an abnormality occurs when transmitting the coding signal SIG_1 between the first operation circuit 101 and the second operation circuit 102, thereby realizing FuSa testing of the first operation circuit 101 and the second operation circuit 102.

[0041] In the case where the second operation circuit 102 is further coupled to other operation circuits at the subsequent stage, an encoder and a decoder coupled in sequence may be provided between the second operation circuit 102 and the other operation circuits. Similarly, the operation signal SIG_3 is decoded and encoded in sequence by the encoder and the decoder to implement FuSa testing of the second operation circuit 102 and the other operation circuits.

[0042] When the tensor computing core is FuSa tested using the above-mentioned parity check method, only the lines used for data transmission in the tensor computing core can be detected. It is impossible to detect whether the operation circuits in the tensor computing core are abnormal, and it is impossible to perform FuSa testing on all circuits in the entire tensor computing core, so the expected functional safety standards cannot be met. In addition, since the coded signal is a signal after adding a parity check bit to the transmission data, the bit width is larger than the transmission data. Therefore, in order to transmit the coded signal through the lines between the operation circuits, it is necessary to increase the line area between the operation circuits, which will increase the area overhead of the integrated circuit. At the same time, when the coded signal after adding the parity check bit is transmitted through the lines between the operation circuits, greater data transmission power consumption will also be generated.

[0043] Based on the above technical problems, an embodiment of the present disclosure provides a functional safety test circuit, in which a configurator generates configuration information for performing functional safety testing on an integrated circuit to be tested, and then multiple test data generators generate multiple first test data based on the configuration information; then, the multiple first test data are processed by the integrated circuit to be tested to obtain multiple second test data; finally, a first comparator is used to compare the consistency of the multiple second test data to obtain a first test result of the integrated circuit to be tested.

[0044] In this way, the first detection result of the integrated circuit to be tested can be determined based on the consistency of the obtained multiple second test data only through the integrated circuit to be tested. FuSa test of the integrated circuit to be tested is realized. When the safety test circuit provided by the present disclosure performs functional safety test on the integrated circuit to be tested, it can not only meet the expected functional safety standards, but also does not need to add parity check bits to the transmission data of the integrated circuit to be tested. Therefore, it can reduce the area overhead of the integrated circuit and reduce the power consumption of data transmission.

[0045] Example Circuit

[0046] Figure 2 FIG. 1 is a schematic diagram of a functional safety test circuit provided by an exemplary embodiment of the present disclosure. Figure 2 As shown, the functional safety test circuit 20 includes a configurator 201 , a plurality of test data generators 202 , an integrated circuit to be tested 203 , and a first comparator 204 .

[0047] Among them, the configurator 201 is used to generate configuration information for testing the integrated circuit 203 under test and output the configuration information; multiple test data generators 202 are coupled to the configurator 201, and are used to generate and output first test data corresponding to each test data generator 202 in the multiple test data generators 202 based on the configuration information; the integrated circuit 203 under test is coupled to the multiple test data generators 202 to process the multiple first test data to obtain and output multiple second test data; the first comparator 204 is coupled to the integrated circuit 203 under test, and is used to compare the consistency of the multiple second test data to obtain the first test result of the integrated circuit 203 under test.

[0048] Exemplarily, the configurator 201 may be an address generation unit (AGU) on the vehicle-mounted SOC for instruction parsing and control. The configurator 201 may include a control input terminal and a configuration output terminal. The control input terminal of the configurator 201 is used to receive the test instruction output by the compiler. The configurator 201 is used to generate configuration information for performing functional safety testing on the integrated circuit 203 under test in response to the test instruction, and output the configuration information through the configuration output terminal.

[0049] In some embodiments, the configuration information may include instructions for configuring the test data generator 202 to generate test data, and the type of instructions included in the configuration information is related to a test method for performing a functional safety test on the integrated circuit 203 under test.

[0050] Exemplarily, the test method for performing functional safety testing on the integrated circuit 203 under test may include random data testing and preset data testing. If the test method is random data testing, the configuration information includes a start test instruction and a close test instruction. If the test method is preset data testing, that is, testing is performed using fixed test data, the configuration information includes not only a start test instruction and a close test instruction, but also a control instruction for controlling the test data generator 202 to generate preset test data. The embodiments of the present disclosure do not limit the specific content of the configuration information, and the following embodiments are exemplified by taking the configuration information including the start test instruction and the close test instruction as an example.

[0051] Exemplarily, according to different test modes, the multiple test data generators 202 may include at least one type of data generator. In some examples, the multiple test data generators 202 may include multiple random data generators or multiple preset data generators.

[0052] The random data generator is used to generate random test data, and the random test data is uncontrollable unknown test data. Therefore, the random data generator can generate different test data at different times in response to the start test instruction.

[0053] The preset data generator is used to generate preset test data, and the preset test data is test data corresponding to the control instruction. Therefore, the preset data generator can generate preset test data corresponding to each control instruction in response to the start test instruction and different control instructions.

[0054] In some other examples, the plurality of test data generators 202 may include at least one random data generator and at least one preset data generator. The type of data generators included in the plurality of test data generators 202 is related to the circuit structure of the integrated circuit 203 to be tested.

[0055] For example, if the integrated circuit 203 under test includes multiple data processing circuits, and each data processing circuit includes multiple identical data processing sub-circuits, then the same test data can be used to perform FuSa testing on the integrated circuit 203 under test, or different test data can be used to perform FuSa testing on the integrated circuit 203 under test. Therefore, the multiple test data generators 202 can be random data generators or preset data generators.

[0056] For another example, if the integrated circuit 203 under test includes multiple data processing circuits, and at least some of the multiple data processing circuits include different data processing sub-circuits, then only the same test data can be used to perform FuSa testing on the integrated circuit 203 under test, so the multiple test data generators 202 can be preset data generators.

[0057] The number of the multiple test data generators 202 is related to the circuit structure of the integrated circuit under test 203. In some examples, the number of the multiple test data generators 202 corresponds to the number of data input terminals included in the integrated circuit under test 203. For example, if the integrated circuit under test 203 includes 3 data input terminals, the multiple test data generators 202 include 3 test data generators 202. Taking the test data generator 202 as a random data generator as an example, the multiple test data generators 202 may include a first random data generator, a second random data generator, and a third random data generator.

[0058] Exemplarily, each of the plurality of test data generators 202 includes a configuration input terminal and a data output terminal. The configuration input terminal of each test data generator 202 is coupled to the configuration output terminal of the configurator 201 .

[0059] Take the test data generator 202 as a random data generator, and the configuration information includes a startup test instruction as an example. In some examples, the test data generator 202 is used to receive the startup test instruction output by the configurator 201, generate random test data in response to the startup test instruction, and output the random test data through the data output terminal. In this case, the first test data corresponding to the test data generator 202 is random test data.

[0060] Take the test data generator 202 as a preset data generator, and the configuration information includes a start test instruction and a control instruction for generating preset test data as an example. In other examples, the test data generator 202 is used to receive the start test instruction and the control instruction output by the configurator 201, generate preset test data corresponding to the control instruction in response to the start test instruction and the control instruction, and output the preset test data through the data output terminal. In this case, the first test data corresponding to the test data generator 202 is the preset test data.

[0061] Exemplarily, the first test data may be a test sequence including a plurality of first levels and a second level. In some examples, the first level may be a logic low level "0", and the second level may be a logic high level "1"; in other examples, the first level may be a logic high level "1", and the second level may be a logic low level "0". The embodiments of the present disclosure do not limit the specific levels of the first level and the second level. The embodiments of the present disclosure are exemplified by taking the first level as a logic low level "0" and the second level as a logic high level "1".

[0062] In some examples, in order to cover multiple possibilities to improve test accuracy, the first test data may be a test sequence in which the number of high and low level flips is greater than a preset number. Taking the preset number of 5, flipping from low level 0 to high level 1, and then from high level 1 to low level 0 as one flip, for example, the first test data may be 010110001001110011110000.

[0063] In some examples, the first test data may correspond to the type of the test data generator 202. If the type of the test data generator 202 is a random data generator, the first test data is a random test sequence, which may also be referred to as random test data; if the type of the test data generator 202 is a preset data generator, the first test data is a preset test sequence, which may also be referred to as preset test data.

[0064] The first test data generated by each test data generator 202 in the multiple test data generators 202 may be the same or different. The embodiment of the present disclosure does not limit the consistency of the first test data generated by each test data generator 202. The embodiment of the present disclosure takes the example that the first test data generated by each test data generator 202 is different as an example for illustrative description.

[0065] In some examples, if each test data generator 202 is a random data generator, there are different situations for the first test data generated by each test data generator 202. In other examples, if each test data generator 202 is a preset data generator, and each test data generator 202 receives and responds to the same test instruction, each test data generator 202 generates the same first test data.

[0066] In the embodiment of the present disclosure, the integrated circuit 203 to be tested may be any integrated circuit in the SOC that has relatively simple logic, relatively more operation circuits and relatively large area. In some examples, the integrated circuit 203 to be tested may be an integrated circuit other than the neural network processor on the SOC. For example, the integrated circuit 203 to be tested may be a tensor computing core other than the neural network processor of the SOC. In other examples, the integrated circuit 203 to be tested may also be an integrated circuit in the neural network processor of the SOC, for example, the integrated circuit 203 to be tested may be a tensor computing core in the neural network processor of the SOC. The embodiment of the present disclosure takes the case where the integrated circuit 203 to be tested is a tensor computing core in the neural network processor of the SOC as an example for illustrative explanation.

[0067] The data input terminal of the IC under test 203 is coupled to the data output terminals of the multiple test data generators 202 for receiving the first test data output by each test data generator 202 to obtain multiple first test data.

[0068] Exemplarily, the configurator 201 further includes a control output terminal. The configurator 201 is also used to generate a circuit control signal for controlling the IC under test 203 to perform corresponding data processing based on the test instruction output by the compiler, and output the circuit control signal through the control output terminal.

[0069] The integrated circuit under test 203 also includes a control signal input terminal. The control signal input terminal is coupled to the control output terminal of the configurator 201 and is used to receive a circuit control signal. The integrated circuit under test 203 is used to perform pre-processing, arithmetic operation processing and post-processing on the plurality of first test data in response to the circuit control signal to obtain a plurality of second test data.

[0070] Exemplarily, the number of the first comparator 204 may be one or more, and the number of the first comparator 204 is related to the number of the plurality of second test data. In some examples, the number of the first comparator 204 is half the number of the plurality of second test data. For example, if the number of the plurality of second test data is 64, the number of the first comparator 204 is 32.

[0071] For example, the number of the plurality of second test data is 64 and the number of the first comparators 204 is 32. The 64 second test data can be divided into two groups of second test data to obtain 32 groups of second test data; the 32 comparators can be used to perform consistency comparison on the 32 groups of second test data to obtain 32 first comparison results. Furthermore, the 32 first comparison results can be determined as the first test results of the integrated circuit 203 to be tested.

[0072] In some examples, if the first level indicates that a set of test data to be compared is the same, and the second level indicates that a set of test data to be compared is different, then when the 32 first comparison results are all the first level, it can be determined that the first test result of the integrated circuit 203 to be tested is a test pass; when at least one of the 32 first comparison results is the second level, it is determined that the first test result of the integrated circuit 203 to be tested is a test fail.

[0073] In other examples, if the first level indicates that a set of test data to be compared is different, and the second level indicates that a set of test data to be compared is the same, then when the 32 first comparison results include at least one first level, it can be determined that the first test result of the integrated circuit 203 to be tested is a test failure; when the 32 first comparison results are all second levels, it is determined that the first test result of the integrated circuit 203 to be tested is a test pass. Since the specific implementation of the first level and the second level has been described above, the embodiments of the present disclosure will not be repeated here.

[0074] The functional safety test circuit provided by the embodiment of the present disclosure can determine the first test result of the integrated circuit under test based on the consistency of the obtained multiple second test data by only processing the multiple first test data by the integrated circuit under test, thereby realizing FuSa protection of the circuit in the integrated circuit under test. When the safety test circuit provided by the present disclosure performs functional safety testing on the integrated circuit under test, it can not only meet the expected functional safety standards, but also does not need to add parity bits to the transmission data of the integrated circuit under test, thereby reducing the area overhead of the integrated circuit and reducing the power consumption of data transmission.

[0075] Since the configuration information is related to the test mode of the integrated circuit 203 under test, and the test mode of the integrated circuit 203 under test is related to the circuit structure of the integrated circuit 203 under test, the configurator 201 can generate different configuration information for the integrated circuit 203 under test with different structures. Furthermore, the test data generator 202 can generate corresponding first test data in response to different configuration information.

[0076] In some embodiments of the present disclosure, the first test data may include random test data or preset test data. The test data generator 202 is used to generate random test data in response to the configuration information including first sub-configuration information corresponding to the random data test; or the test data generator 202 is used to generate preset test data in response to the configuration information including second sub-configuration information corresponding to the preset data test.

[0077] Exemplarily, if the test mode of the functional safety test on the IC 203 under test is a random data test, the first sub-configuration information may include instructions for configuring the test data generator 202 to generate random test data. For example, the first sub-configuration information may include a start test instruction and a stop test instruction.

[0078] If the test mode of the functional safety test on the IC 203 to be tested is a preset data test, the second sub-configuration information may include an instruction for configuring the test data generator 202 to generate preset test data. For example, the second sub-configuration information may include a start test instruction, a stop test instruction, and a control instruction for controlling the test data generator 202 to generate preset test data.

[0079] In the functional safety test circuit provided by the embodiment of the present disclosure, when the configuration information includes the first sub-configuration information corresponding to the random test data, the test data generator can generate the random test data for performing the random data test on the integrated circuit under test, so that the random data test can be performed on the integrated circuit under test based on the random test data, which meets the actual test requirements for performing the functional safety test on the integrated circuit under test. When the configuration information includes the second sub-configuration information corresponding to the preset data test, the test data generator can generate the preset test data for performing the preset data test on the integrated circuit under test, so that the preset data test can be performed on the integrated circuit under test based on the preset test data, which meets the actual test requirements for performing the functional safety test on the integrated circuit under test.

[0080] In other embodiments of the present disclosure, if the test method for the functional safety test of the integrated circuit 203 to be tested is a preset data test, the functional safety test circuit 20 may not include the configurator 201 and the multiple test data generators 202. The method for the functional safety test circuit 20 to obtain the first test data may include: first writing the preset test data of the integrated circuit 203 to be tested into a preset storage area, and reading the preset test data from the preset storage area through an external bus when the functional safety test is performed on the integrated circuit 203 to be tested. In this way, the area overhead of the integrated circuit to be tested can be reduced.

[0081] Take the tensor calculation core in the neural network processor of the SOC in which the integrated circuit 203 to be tested is used as an example. The integrated circuit 203 to be tested may include multiple first data conversion circuits, arithmetic logic circuits and second data conversion circuits. Among them, the multiple first data conversion circuits can be used to pre-process multiple first test data to obtain and output multiple pre-processed first test data. The arithmetic logic circuit can be used to perform arithmetic operations on the multiple pre-processed first test data to obtain multiple arithmetic operation data. The second data conversion circuit is used to post-process multiple arithmetic operation data to obtain multiple second test data.

[0082] like Figure 3 As shown in the above Figure 2 Based on the illustrated embodiment, the integrated circuit under test 203 may include a plurality of first data conversion circuits 2031 , an arithmetic logic circuit 2032 , and a second data conversion circuit 2033 .

[0083] Among them, the data input end of the multiple first data conversion circuits 2031 is the data input end of the integrated circuit under test 203, and the data input end of each first data conversion circuit 2031 is coupled to the data output end of the multiple test data generators 202, and the data output end of the multiple first data conversion circuits 2031 is coupled to the data input end of the arithmetic logic circuit 2032.

[0084] The plurality of first data conversion circuits 2031 are used to perform first data conversion on the plurality of first test data to obtain and output a plurality of first conversion data.

[0085] The data output terminal of the arithmetic logic circuit 2032 is coupled to the data input terminal of the second data conversion circuit 2033. The arithmetic logic circuit 2032 is used to receive a plurality of first conversion data, perform arithmetic operations on the plurality of first conversion data, and obtain and output a plurality of arithmetic operation data.

[0086] The data output terminal of the second data conversion circuit 2033 is the data output terminal of the IC 203 under test and is coupled to the first comparator 204. The second data conversion circuit 2033 is used to perform second data conversion on a plurality of arithmetic operation data to obtain and output a plurality of second test data.

[0087] Exemplarily, the first data conversion may correspond to the above-mentioned preprocessing, and the first data conversion may include data structure or data format conversion, data beating, data selection and other processing. The first conversion data may be data obtained after the data structure or data format conversion, data beating, data selection and other processing are performed on a plurality of first test data. The purpose of performing the first data conversion processing on the first test data is to convert the first test data into data that meets the input requirements of the arithmetic logic circuit 2032, and therefore, the first conversion data meets the input requirements of the arithmetic logic circuit 2032.

[0088] For example, reference Figure 3 As shown, each of the multiple first data conversion circuits 2031 may include multiple first data conversion sub-circuits connected in parallel, and the data input end of each of the multiple first data conversion sub-circuits is coupled to the data output end of the multiple test data generators 202. In some examples, each of the first data conversion sub-circuits in the first data conversion circuit 2031 may simultaneously receive multiple first test data output by the multiple test data generators 202, and simultaneously process the multiple first test data. For example, each first data conversion sub-circuit may be used to receive multiple first test data, perform data structure or data format conversion, data beat and data selection on the multiple first test data, and obtain first conversion data that meets the input requirements of the arithmetic logic circuit 2032. Furthermore, multiple first conversion data can be obtained through the first data conversion circuit 2031.

[0089] In the disclosed embodiment, the number of the plurality of first data conversion circuits 2031 and the number of first data conversion sub-circuits in each first data conversion circuit 2031 are related to the circuit structure of the integrated circuit 203 under test.

[0090] In some examples, the number of the plurality of first data conversion circuits 2031 corresponds to the number of data input terminals included in the integrated circuit under test 203. Among them, one data input terminal can correspond to receiving data from a group of data sources. For example, if the integrated circuit under test 203 receives data from three groups of data sources, that is, the integrated circuit under test 203 includes three data input terminals, then the number of the plurality of first data conversion circuits 2031 is 3. The embodiment of the present disclosure does not limit the number of the plurality of first data conversion circuits 2031. The following embodiment is exemplified by taking the number of the plurality of first data conversion circuits 2031 as 3 as an example.

[0091] In other examples, the number of first data conversion sub-circuits in each first data conversion circuit 2031 corresponds to the parallelism of the integrated circuit 203 to be tested, and the parallelism refers to the number of corresponding data that the integrated circuit 203 to be tested can process simultaneously. For example, if the integrated circuit to be tested can process 8 data at the same time, then the first data conversion circuit 2031 may include 8 first data conversion sub-circuits. For another example, if the integrated circuit to be tested can process 32 data at the same time, then the first data conversion circuit 2031 may include 32 first data conversion sub-circuits. The embodiment of the present disclosure does not limit the number of first data conversion sub-circuits in the first data conversion circuit 2031. The embodiment of the present disclosure takes the number of first data conversion circuits 2031 as 3, wherein the first data conversion circuit 2031a may include 8 first data conversion sub-circuits, the first data conversion circuit 2031b includes 32 second data conversion sub-circuits, and the first data conversion circuit 2031c includes 8 third data conversion sub-circuits as an example for exemplary description.

[0092] Exemplarily, each of the plurality of first data conversion circuits 2031 includes a control signal terminal, and the control signal terminal is coupled to the control output terminal of the configurator 201 .

[0093] For example, the first data conversion circuit 2031a includes a first control signal terminal, and the first control signal terminal is coupled to the control output terminal of the configurator 201. The circuit control signal output by the configurator 201 may include a first control signal corresponding to the first data conversion circuit 2031a. The first data conversion circuit 2031a is used to receive the first control signal, and in response to the first control signal, select multiple first data conversion sub-circuits from the 8 first data conversion sub-circuits included in the first data conversion circuit 2031a to perform structure or data format conversion, data pacing, data selection and other processing on multiple first test data to obtain multiple first conversion data.

[0094] Exemplarily, the arithmetic logic circuit 2032 may be an arithmetic logic unit (ALU), and may include a plurality of adders, a plurality of multipliers, a plurality of saturation logic circuits, and a plurality of shift logic circuits.

[0095] In some examples, the arithmetic logic circuit 2032 also includes a control signal terminal, and the control signal terminal of the arithmetic logic circuit 2032 is coupled to the control output terminal of the configurator 201. Correspondingly, the circuit control signal output by the configurator 201 may include a second control signal corresponding to the arithmetic logic circuit 2032. The arithmetic logic circuit 2032 is used to receive the second control signal, and select at least one adder, at least one multiplier, at least one saturation logic circuit, and at least one shift logic circuit in the arithmetic logic circuit 2032 to perform arithmetic operations on the plurality of first conversion data in response to the second control signal to obtain a plurality of arithmetic operation data.

[0096] Exemplarily, the second data conversion process may also be referred to as post-processing, and the second data conversion is similar to the first data conversion, and the second data conversion may also include data structure or data format conversion, data beating, data selection and other processing. The second conversion data may be data obtained after the arithmetic operation data is subjected to data structure or data format conversion, data beating, data selection and other processing. The purpose of the present disclosure performing the second data conversion process on the arithmetic operation data is to convert the arithmetic operation data into data that meets the input requirements of the subsequent stage circuit of the integrated circuit 203 under test, so the second conversion data meets the input requirements of the subsequent stage circuit of the integrated circuit 203 under test.

[0097] Similar to the first data conversion circuit 2031, the second data conversion circuit 2033 may include a plurality of fourth data conversion sub-circuits. The data input terminals of the fourth data conversion sub-circuits are respectively coupled to the data output terminals of the arithmetic logic circuit 2032. The fourth data conversion sub-circuits are used to receive arithmetic operation data, perform data structure or data format conversion on the arithmetic operation data, and obtain second test data that meets the input requirements of the subsequent circuit of the integrated circuit 203 to be tested.

[0098] In some examples, the second data conversion circuit 2033 may also include a control signal terminal, and the control signal terminal is coupled to the configurator 201. Correspondingly, the circuit control signal output by the configurator 201 may include a third control signal corresponding to the second data conversion circuit 2032. The second data conversion circuit 2033 is used to receive the third control signal, and in response to the third control signal, select at least one fourth data conversion subcircuit from a plurality of fourth data conversion subcircuits included in the second data conversion circuit 2033, and perform data structure or data format conversion, data pacing, data selection and other processing on the plurality of operation processing data through the selected at least one fourth data conversion, so as to obtain a plurality of second test data.

[0099] In the functional safety test circuit provided by the embodiment of the present disclosure, a plurality of first test data are converted into first data by a plurality of first data conversion circuits, so that a plurality of first conversion data suitable for processing by an arithmetic logic circuit can be obtained. The arithmetic logic circuit performs arithmetic operations on the plurality of first conversion data, so that data operation processing of the first test data can be realized. Furthermore, the second data conversion circuit performs a second data conversion on the plurality of arithmetic operation data, so that a plurality of second test data suitable for data processing by a subsequent circuit can be obtained. Thus, the functional safety test of the integrated circuit to be tested can be realized.

[0100] In some embodiments of the present disclosure, the arithmetic logic circuit 2032 may include at least one logic operation circuit, and the number of logic operation circuits included in the arithmetic logic circuit 2032 and the function of each logic operation circuit are related to the function and design of the integrated circuit under test 203. The embodiments of the present disclosure do not limit the number and function of the logic operation circuits included in the arithmetic logic circuit 2032. The embodiments of the present disclosure are exemplified by taking the arithmetic logic circuit 2032 including the first logic operation circuit and the second logic operation circuit as an example.

[0101] like Figure 4 As shown in the above Figure 3 Based on the illustrated embodiment, the arithmetic logic circuit 2032 includes a first logic operation circuit 401 and a second logic operation circuit 402 .

[0102] The data input terminal of the first logic operation circuit 401 is the data input terminal of the arithmetic logic circuit 2032, and is coupled to the data output terminals of the plurality of first data conversion circuits 2032. The data output terminal of the first logic operation circuit 401 is coupled to the data input terminal of the second logic operation circuit 402. The first logic operation circuit 401 is used to perform a first logic operation on the plurality of first conversion data to obtain and output a plurality of first operation data.

[0103] The data output terminal of the second logic operation circuit 402 is the data output terminal of the arithmetic logic circuit 2032 and is coupled to the data input terminal of the second data conversion circuit 2033. The second logic operation circuit 402 is used to perform a second logic operation on a plurality of first operation data to obtain and output a plurality of arithmetic operation data.

[0104] Exemplarily, the first logic operation circuit 401 may include a plurality of adders with the same calculation logic and / or a plurality of multipliers with the same calculation logic. For example, the first logic operation circuit 401 may include 4k (thousand) adders and 4k multipliers. For another example, the first logic operation circuit 401 may include 8k adders and 8k multipliers. Correspondingly, the first logic operation circuit 401 may be used to perform addition and multiplication operations on a plurality of first conversion data to obtain a plurality of first operation data.

[0105] In some examples, the first logic operation circuit 401 includes a first control signal sub-terminal, and the first control signal sub-terminal is coupled to the configurator 201. Correspondingly, the second control signal may include a first sub-control signal corresponding to the first logic operation circuit 401. The first logic operation circuit 401 is used to receive the first sub-control signal, and select at least one adder and at least one multiplier to perform addition and multiplication operations on multiple first conversion data in response to the first sub-control signal to obtain multiple first operation data.

[0106] Similarly, the second logic operation circuit 402 may be a logic matrix including a plurality of identical logic circuits. Each logic circuit in the logic matrix may receive a first operation data output by the first logic operation circuit 401, and perform operations such as addition, saturation, shift, quantization, table lookup, etc. on the first operation data to obtain arithmetic operation data.

[0107] In some examples, the second logic operation circuit 402 includes a second control signal sub-terminal, and the second control signal sub-terminal is coupled to the configurator 201. Correspondingly, the second control signal may include a second sub-control signal corresponding to the second logic operation circuit 402. The second logic operation circuit 402 is used to receive the second sub-control signal, and select to perform at least one of addition, saturation, shift, quantization, table lookup, etc. on each of the plurality of first operation data in response to the second sub-control signal to obtain arithmetic operation data.

[0108] Since there are fuzzy operations such as saturation and quantization in each logic circuit in the second logic operation circuit 402, when determining the first detection result of the integrated circuit 203 under test based on the consistency of the second test data corresponding to the multiple arithmetic operation data output by the second logic operation circuit 402, it is impossible to cover all faults in the previous stage circuit of the second logic operation circuit 402 in the integrated circuit 203 under test. That is, it is impossible to cover all faults of the multiple test data generators 202 and the first logic operation circuit 401, and the test coverage rate of the integrated circuit 203 under test can only reach 90%, and cannot reach 100%. In order to improve the test coverage rate of the integrated circuit under test, in the embodiment of the present disclosure, when multiple first operation data are input into the second logic operation circuit 402, a second comparator can also be set at the output end of the first logic operation circuit 401, and the consistency of the multiple first operation data output by the first logic operation circuit 401 is compared by the second comparator to realize the detection of the previous stage circuit of the second logic operation circuit 402.

[0109] like Figure 5 As shown in the above Figure 4 Based on the illustrated embodiment, the functional safety test circuit 20 further includes a second comparator 205 .

[0110] The comparison data input terminal of the second comparator 205 is coupled to the output terminal of the first logic operation circuit 401. The second comparator 205 is used to compare the consistency of a plurality of first operation data to obtain a second test result of the integrated circuit under test.

[0111] Similar to the first comparator 204, the second comparator 205 also includes at least one comparator, and the number of comparators in the second comparator 205 is related to the data volume of the plurality of first operation data. The implementation of the second comparator 205 in the embodiment of the present disclosure is not described in detail here.

[0112] Exemplarily, the second test result of the integrated circuit under test 203 may correspond to the detection result of the previous stage circuit of the second logic operation circuit 402 in the integrated circuit under test 203, and may be determined according to the consistency of the plurality of first operation data. In some examples, if the plurality of first operation data are consistent, it is determined that the test of the previous stage circuit of the second logic operation circuit 402 has passed. In other examples, if the plurality of first operation data are inconsistent, it is determined that the test of the previous stage circuit of the second logic operation circuit 402 has failed.

[0113] Take the case where the number of the plurality of first operation data is 64 and the second comparator 205 includes 32 comparators as an example. The 64 first operation data can be divided into two first operation data as a group to obtain 32 groups of first operation data. Then, the consistency of the 32 groups of first operation data is compared respectively by the 32 second comparators 204, that is, a group of first operation data is compared for one comparator, and 32 second comparison results can be obtained. And the 32 second comparison results can be determined as the second test results of the integrated circuit 203 to be tested. Since the implementation of the second comparison result is similar to that of the first comparison result, the second comparison result will not be described in detail in the embodiment of the present disclosure.

[0114] If the second comparison results among the 32 second comparison results are the same, for example, the 32 second comparison results are all the first level or the second level, then the second test result of the integrated circuit under test 203 is determined to be a test pass. If there are different second comparison results among the 32 second comparison results, for example, the 32 second comparison results include one first level and 31 second levels, then the second test result of the integrated circuit under test 203 is determined to be a test fail.

[0115] The functional safety test circuit provided by the embodiment of the present disclosure compares the consistency of multiple first operation data through the second comparator to obtain the second test result of the integrated circuit to be tested. In this way, the detection of the front-stage circuit of the second logic operation circuit in the integrated circuit to be tested can be realized, and the test coverage of the integrated circuit to be tested can be improved.

[0116] In some embodiments of the present disclosure, the second comparator 205 is further used to determine expected data corresponding to the preset test data in response to the first test data being preset test data, compare the consistency of the first operation data and the expected data, and obtain a second test result; or, in response to the first test data being random detection data, compare the consistency of multiple first operation data to obtain a second test result.

[0117] Exemplarily, the expected data may be data output by the first logic operation circuit 401 when preset test data is input to the integrated circuit 203 under test. In some examples, the expected data may be determined by inference based on the circuit structure of the integrated circuit 203 under test. In other examples, the expected data may be determined by testing the integrated circuit 203 under test. The embodiment of the present disclosure does not limit the method for obtaining the expected data, and the embodiment of the present disclosure takes the example of inferring the expected data based on the circuit structure of the integrated circuit 203 under test as an example for exemplary description.

[0118] In the embodiment of the present disclosure, when the functional safety test is performed on the integrated circuit 203 to be tested by using the preset test data, the data output by the first logic operation circuit 401 can be compared with the expected data for consistency by the second comparator 205 to obtain the second test result of the integrated circuit 203 to be tested. Therefore, the functional safety test of the previous stage circuit of the second logic operation circuit 402 can be accurately performed according to the second test result.

[0119] In the disclosed embodiment, when the functional safety test is performed on the IC 203 under test by using random test data, the consistency comparison of the number output by the first logic operation circuit 401 can be directly performed by the second comparator 205 to obtain the second test result of the IC 203 under test. Thus, the preceding circuit of the second logic operation circuit 402 can be accurately detected according to the second test result.

[0120] like Figure 6 As shown in the above Figure 3 Based on the illustrated embodiment, the integrated circuit under test 203 further includes a beater 2034 .

[0121] The data input terminal of the beater 2034 is coupled to the data output terminal of the arithmetic logic circuit 2032, and the output terminal of the beater 2034 is coupled to the data input terminal of the second data conversion circuit 2033. The beater 2034 is used to temporarily store multiple arithmetic operation data and output the multiple arithmetic operation data after temporary storage.

[0122] Correspondingly, the second data conversion circuit 2033 is used to receive the multiple arithmetic operation data after temporary storage, perform second data conversion processing on the multiple arithmetic operation data after temporary storage, obtain multiple second test data, and output the multiple second test data to the first comparator 204.

[0123] Exemplarily, the beater 2034 may include at least one register. The number of registers in the beater 2034 is related to the timing requirements of the integrated circuit to be tested, and the embodiment of the present disclosure does not limit the number of registers.

[0124] The functional safety test circuit provided in the embodiment of the present disclosure can temporarily store multiple arithmetic operation data through a beater, thereby adjusting the timing of the multiple arithmetic operation data and ensuring the correctness of the timing of the integrated circuit to be tested.

[0125] Exemplary Methods

[0126] Figure 7 1 is a schematic diagram of an implementation flow of a functional safety test method for an integrated circuit provided by an exemplary embodiment of the present disclosure. The functional safety test method can be applied to the above-mentioned functional safety test circuit to implement a functional safety test on the integrated circuit to be tested. Figure 7 As shown, the functional safety testing method may include the following steps 701 to 704 .

[0127] Step 701: Generate configuration information for testing the integrated circuit to be tested by a configurator.

[0128] Step 702: Generate first test data corresponding to each of the multiple test data generators based on the configuration information by using the multiple test data generators.

[0129] Step 703: Process the plurality of first test data by the integrated circuit to be tested to obtain a plurality of second test data.

[0130] Step 704: Compare the consistency of the plurality of second test data by a first comparator to obtain a first test result of the integrated circuit to be tested.

[0131] In some embodiments, the first test data includes random test data or preset test data. Taking the first test data including random test data as an example, step 702 specifically includes: generating random test data by a test data generator in response to first sub-configuration information corresponding to a random data test. Taking the first test data including preset test data as an example, step 702 specifically includes: generating preset test data by a test data generator in response to second sub-configuration information corresponding to a preset data test.

[0132] In some embodiments, the integrated circuit under test includes a plurality of first data conversion circuits, arithmetic logic circuits, and second data conversion circuits. Figure 8 As shown in the above Figure 7 Based on the illustrated embodiment, step 703 may include the following steps 7031 to 7033.

[0133] Step 7031: Perform first data conversion on a plurality of first test data by using a plurality of first data conversion circuits to obtain and output a plurality of first conversion data.

[0134] Step 7032: Perform arithmetic operation on the plurality of first conversion data through an arithmetic logic circuit to obtain and output a plurality of arithmetic operation data.

[0135] Step 7033, performing a second data conversion on the plurality of arithmetic operation data by a second data conversion circuit, and obtaining and outputting a plurality of second test data.

[0136] In some embodiments, the arithmetic logic circuit includes a first logic operation circuit and a second logic operation circuit. Fig. 9 As shown in the above Figure 8 Based on the illustrated embodiment, step 7032 includes the following steps 801 and 802 .

[0137] Step 801: Perform a first logic operation on a plurality of first conversion data by a first logic operation circuit to obtain a plurality of first operation data.

[0138] Step 802: Perform a second logic operation on the plurality of first operation data by a second logic operation circuit to obtain a plurality of arithmetic operation data.

[0139] In some embodiments, the functional safety test circuit further includes a second comparator. Fig.10 As shown in the above Fig. 9 Based on the illustrated embodiment, the functional safety testing method may further include the following step 803 .

[0140] Step 803: Compare the consistency of the plurality of first operation data by a second comparator to obtain a second test result of the integrated circuit to be tested.

[0141] In some embodiments, step 803 specifically includes: responding to the first test data being preset test data by a second comparator, determining expected data corresponding to the preset test data, comparing the consistency of the first operation data and the expected data, and obtaining a second test result; or, responding to the first test data being random detection data by a second comparator, comparing the consistency of multiple first operation data, and obtaining a second test result.

[0142] In some examples, the integrated circuit under test also includes a beater. Fig.10 As shown in the above Figure 8 Based on the illustrated embodiment, step 7033 specifically includes: temporarily storing multiple arithmetic operation data through a beater, and outputting the multiple arithmetic operation data after temporary storage; performing second data conversion processing on the multiple arithmetic operation data after temporary storage through a second data conversion circuit to obtain multiple second test data, and outputting the multiple second test data to the first comparator.

[0143] Regarding a functional safety testing method for an integrated circuit in the above-mentioned embodiment, the specific methods and corresponding beneficial effects of each execution step have been described in detail in the corresponding embodiment part of the functional safety testing circuit part mentioned above. Please refer to the corresponding execution operation methods and beneficial technical effects of the above-mentioned exemplary circuit part, and no further details will be given here.

[0144] In some embodiments of the present disclosure, if the neural network processor of the on-chip SOC includes multiple tensor computing cores, the neural network processor includes corresponding multiple functional safety test circuits.

[0145] Fig.11 FIG. 1 is a schematic diagram of a neural network processor provided by an exemplary embodiment of the present disclosure. Fig.11As shown, the neural network processor 110 includes at least one Figure 1 Functional safety test circuit shown.

[0146] Exemplary Electronic Devices

[0147] Fig.12 is a schematic diagram of a structure of an electronic device provided by an exemplary embodiment of the present disclosure, such as Fig.12 As shown, the electronic device 120 includes one or more processors 1201 and a memory 1202 .

[0148] The processor 1201 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 120 to perform desired functions.

[0149] The memory 1202 may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1201 may execute the program instructions to implement the functional safety test method of the integrated circuit of each embodiment of the present disclosure above and / or other desired functions.

[0150] In one example, the electronic device 120 may further include: an input device 1203 and an output device 1204 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0151] Of course, to simplify, Fig.12 Only some of the components related to the present disclosure in the electronic device 120 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 120 may also include any other appropriate components.

[0152] Exemplary computer program products and computer-readable storage media

[0153] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the functional safety testing method of an integrated circuit according to various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section of this specification.

[0154] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0155] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes the steps of the functional safety testing method of an integrated circuit according to various embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0156] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (Random Access Memory, RAM), a read-only memory (Read Only Memory, ROM), an erasable programmable read-only memory (Erasable Programmable Read Only Memory, EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0157] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0158] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A functional safety test circuit, comprising: A configurator, used to generate configuration information for testing the integrated circuit under test, and output the configuration information; A plurality of test data generators, coupled to the configurator, for generating and outputting first test data corresponding to each of the plurality of test data generators based on the configuration information; The integrated circuit under test is coupled to the plurality of test data generators, and is used to process the plurality of the first test data to obtain and output a plurality of second test data; The first comparator is coupled to the integrated circuit under test and is used to compare the consistency of a plurality of the second test data to obtain a first test result of the integrated circuit under test.

2. The circuit according to claim 1, wherein The test data generator is used to: In response to the configuration information including first sub-configuration information corresponding to the random data test, generating random test data; In response to the configuration information including second sub-configuration information corresponding to the preset data test, generating preset test data; Wherein, the first test data includes the random test data or the preset test data.

3. The circuit according to claim 1, wherein: The integrated circuit to be tested comprises: A plurality of first data conversion circuits, used for performing first data conversion on the plurality of first test data to obtain and output a plurality of first conversion data; an arithmetic logic circuit, coupled to the plurality of first data conversion circuits, for performing arithmetic operations on the plurality of first conversion data to obtain and output a plurality of arithmetic operation data; The second data conversion circuit is coupled to the arithmetic logic circuit and is used to perform a second data conversion on the plurality of arithmetic operation data to obtain and output the plurality of second test data.

4. The circuit according to claim 3, wherein: The arithmetic logic circuit comprises: A first logic operation circuit is used to perform a first logic operation on the plurality of first conversion data to obtain a plurality of first operation data; The second logic operation circuit is used to perform a second logic operation on the plurality of first operation data to obtain the plurality of arithmetic operation data.

5. The circuit according to claim 4, wherein the functional safety test circuit further comprises: The second comparator is coupled to the first logic operation circuit and is used to compare the consistency of the plurality of first operation data to obtain a second test result of the integrated circuit to be tested.

6. The circuit according to claim 5, wherein: The second comparator is used for: In response to the first test data being preset test data, determining expected data corresponding to the preset test data, comparing the first operation data with the expected data for consistency, and obtaining the second test result; or, In response to the first test data being random detection data, the consistency of the plurality of first operation data is compared to obtain the second test result.

7. The circuit according to claim 3, wherein: The integrated circuit to be tested also includes: a beater, coupled to the arithmetic logic circuit and the second data conversion circuit respectively, for temporarily storing the plurality of arithmetic operation data and outputting the plurality of arithmetic operation data after the temporary storage; The second data conversion circuit is used to perform second data conversion processing on the multiple arithmetic operation data after the temporary storage processing to obtain and output the multiple second test data.

8. A functional safety testing method for an integrated circuit, the method comprising: generating, by a configurator, configuration information for testing the integrated circuit under test; Generate, by multiple test data generators based on the configuration information, first test data corresponding to each of the multiple test data generators; Processing the first test data by the integrated circuit to be tested to obtain a plurality of second test data; The consistency of the plurality of second test data is compared by a first comparator to obtain a first test result of the integrated circuit to be tested.

9. A neural network processor, comprising at least one functional safety test circuit according to any one of claims 1 to 7.

10. An electronic device, comprising: A memory for storing processor executable instructions; The processor is used to read the executable instructions from the memory and execute the executable instructions to implement the functional safety testing method for the integrated circuit described in claim 8 above.

11. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the functional safety testing method for an integrated circuit according to claim 8.

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