Signal processing method of photoelectric realization matrix multiplication system based on ZYNQ

Abstract

The invention relates to the technical field of photoelectric signals, and discloses a ZYNQ-based signal processing method for a photoelectric matrix multiplication system, which is characterized in that analog level output and optical power signal measurement are carried out through a PL end of a ZYNQ, and calculation of a proportionality coefficient, confirmation of delay time and synchronous calibration are completed by using a PS end. And conversion and accumulation from the optical power signal to a standard result are completed. And the flexibility of the PS end is combined with the parallel processing capability and the real-time capability of the PL end, so that the signal processing efficiency can be effectively improved. According to the invention, the multiplication operation of data is converted into optical domain operation, and the acceleration of large-scale matrix multiplication is realized.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic signal technology, and in particular to a signal processing method of an optoelectronic matrix multiplication system based on ZYNQ. Background Art

[0002] There are many problems in the field of scientific computing that need to be solved using matrix multiplication. For example, machine learning, software simulation, digital signal processing, etc. In existing technologies, such as GPU and FPGA, the parallelism of computing units is usually used to accelerate matrix operations. However, low-cost devices can only support a limited degree of parallelism, which is not conducive to large-scale matrix operations; while devices that can support large-scale parallelism for large-scale matrix operations are expensive.

[0003] The prior art discloses a sparse matrix multiplication acceleration method, FPGA, computing system and storage medium. The method is used to calculate the product of sparse matrix A and matrix B. Sparse matrix A is stored in an off-chip memory in sparse blocks. The method includes: configuring the parallelism parameter of the computing unit according to the available computing resources on the FPGA chip and the sparse block size of the sparse matrix A; determining the storage structure of the off-chip memory and the storage form of the data in the on-chip buffer according to the parallelism parameter and the data bit width of the off-chip memory; transferring the data in the on-chip memory to the on-chip buffer, and the sparse core computing unit on the FPGA chip calculates the data stored in the on-chip buffer to obtain the product of the sparse matrix A and the matrix B. The patent uses the parallelism of the computing unit to accelerate matrix operations. However, low-cost equipment can only support a limited degree of parallelism, which is not conducive to large-scale matrix operations; and equipment that can support large-scale parallelism for large-scale matrix operations is expensive. Summary of the invention

[0004] The purpose of the present invention is to provide a signal processing method for an optoelectronic matrix multiplication system based on ZYNQ, which can effectively improve the signal processing efficiency and realize the acceleration of large-scale matrix multiplication.

[0005] In order to achieve the above object, the present invention provides a signal processing method of a photoelectric matrix multiplication system based on ZYNQ, including ZYNQ and MZM intensity modulators, wherein the ZYNQ includes a PS end and a PL end, and includes the following steps:

[0006] S1. The PS end configures an analog level signal with a preset waveform and sends multiple packets of data to the PL end in units of a single maximum transmission length;

[0007] S2, PL end receives the data sent by PS end, and outputs the data to MZM intensity modulator in the form of analog level, and at the same time receives the optical power signal modulated by MZM intensity modulator;

[0008] S3, PS reads the optical power signal received by PL, and confirms the synchronization and proportionality coefficient;

[0009] S4, the PS end is configured with an analog level signal for matrix multiplication operation, and sends a single row of vector multiplication data to the PL end;

[0010] S5, the PL end receives the data sent by the PS end and outputs the data in the form of analog level to the MZM intensity modulator, the MZM intensity modulator performs a vector multiplication operation to obtain a multiplication result, and the MZM intensity modulator outputs the multiplication result in the form of an optical power signal to the PL end;

[0011] S6, the PS side reads the multiplication result from the PL side, performs proportional conversion and accumulation operations, and calculates the matrix multiplication result;

[0012] S7. Execute steps S4 to S6 in a loop until every element in the matrix multiplication is calculated and the result is sent to the host computer.

[0013] As a preferred solution, it also includes DDR, ADC chip and DAC chip, the PS end is connected to DDR, the PL end includes AXIDMA module, ADC control module and DAC control module, the PL end communicates with the PS end through the AXIDMA module, the ADC control module is connected to the ADC chip, and the DAC control module is connected to the DAC chip, and step S1 includes:

[0014] S101, the PS end initializes the AXIDMA module, opens the MM2S and S2MM channels, and opens the receive interrupt and the send interrupt;

[0015] S102, the PS terminal sets the value of the parameter register;

[0016] S103, the PS terminal reads the 16-bit level data of the single maximum transmission length from the DDR, and sets the header address and transmission length of the transmission data;

[0017] S104, the PS end executes the transmission command and waits for the transmission completion interrupt;

[0018] S105, after receiving the transmission completion interrupt command, read the next packet of data in units of the single maximum transmission length, and repeat this cycle.

[0019] As a preferred solution, in step S102, the value parameters of the parameter register set include: ADC zero level parameter V zero And the maximum length of a single transmission is LEN.

[0020] As a preferred solution, step S2 includes:

[0021] S201, the PL side receives data from the PS side in packets and stores it into FIFO_0;

[0022] S202, after receiving all the data, the PL terminal sends an enable signal to the DAC control module and the ADC control module;

[0023] S203, after receiving the enable signal, the DAC control module takes out the data in FIFO_0, outputs the 14-bit data to the MZM intensity modulator through its IO port, and modulates the MZM intensity modulator to generate an optical power signal;

[0024] S204, after receiving the enable signal, the ADC control module at the PL end enables the data valid signal of the ADC control module, reads 12-bit digital level data from the IO port of the ADC control module, and inputs the data into FIFO_2 in the form of data stream;

[0025] S205 . After receiving the data with a length of LEN, enable the S2MM data transmission channel, read the FIFO_2 data in units of a single maximum transmission length, and transmit the data to the AXIDMA module.

[0026] As a preferred solution, in step S203, the level signal modulates the MZM intensity modulator to generate an optical power signal as follows: the MZM intensity modulator is set to operate at the bias point V π , when the MZM intensity modulator operates at the bias point V π When the level V is applied, the optical power is P=P0(1+kV), where k is a priori value.

[0027] As a preferred solution, step S3 includes:

[0028] The PS side compares the received data with the sent data and calculates the number of clock cycles between sending and receiving. π The level at the bias point is converted to a standard value between 0 and 2; the proportional coefficient of the level signal and the optical power conversion is calculated;

[0029] The standard value between 0 and 2 is: P / P0 = (1 + kV), the ratio of the modulated optical power to the bias point optical power. For the MZM intensity modulator, the maximum optical power is V π Twice the bias point power, P / P0 is a positive real value not greater than 2.

[0030] As a preferred solution, step S4 includes:

[0031] S401, the PS end reads vector A and vector B whose elements are stored in 16-bit form from the DDR, and after encoding the same code element twice with +V and -V, for a single element to be transmitted that is a 32-bit array, the lower 16 bits store vector A data, and the upper 16 bits store vector B data;

[0032] S402, setting the head address and transmission length of the transmission data through the host computer; the PS end executes the transmission command and waits for the transmission completion interrupt;

[0033] S403, after receiving the transmission completion interrupt command, read the next packet of data in units of the single maximum transmission length, and repeat this cycle until the two column vectors are transmitted.

[0034] As a preferred solution, step S5 includes:

[0035] S501, the PL receives data from the PS in packets, and stores them into FIFO_0 and FIFO_1 respectively according to the high 16 bits as vector A and the low 16 bits as vector B;

[0036] S502, after receiving all the data, the PL terminal sends an enable signal to the DAC control module and the ADC control module;

[0037] S503, after receiving the enable signal, the DAC control module takes out the data in FIFO_0 and FIFO_1, and outputs the data from the dual channels ch1 and ch2 to the IO port to the MZM intensity modulator in the form of 14-bit data; the cascaded MZM intensity modulator completes the vector multiplication operation; after receiving the enable signal, the ADC control module at the PL end enables the data valid signal of the ADC control module, reads the 12-bit digital level data from the IO port of the ADC control module, and inputs it into FIFO_2 in the form of data stream;

[0038] S504, after receiving the data with a length of LEN, enable the S2MM data transmission channel, read the FIFO_2 data in units of a single maximum transmission length, and transmit the multiplication result data in the form of an optical power signal to the DMA direct memory reading module.

[0039] As a preferred solution, in step 503, the vector multiplication operation performed by the cascaded MZM intensity modulators is: when the analog levels of V1 and V2 are applied to the cascaded MZM intensity modulators respectively, the optical power thereof is P=P0(1+kV1)(1+kV2).

[0040] As a preferred solution, step S6 includes:

[0041] S601, determining an interval of valid data in the received data according to the delay time period and the proportionality coefficient calculated in step S2;

[0042] S602, according to the size of the matrix, the received data is divided and spliced, and the corresponding rows and columns are used as units for sorting; V is calculated π is the level size at the bias point, and converts the data into a standard value between 0 and 2, and converts the standard value into the result of the dot product of vector A and vector B according to the proportional coefficient calculated in step S2; wherein, the method for converting the standard value into the result of the dot product of vector A and vector B is: according to the method mentioned in step S4 for encoding the same code element twice with +V and -V, for the multiplication result of the optical powers of V1 and V2, there will be P1=P0(1+kV1)(1+kV2) and P2=P0(1-kV1)(1-kV2), and P1+P2=2P0(1+k 2 V1V2), and V1V2=[(P1 / P0+P2 / P0) / 2-1] / (k 2 ), where k is the proportionality coefficient obtained in step S3, and P1 / P0 and P2 / P0 are standard values ​​obtained respectively;

[0043] S603 , sum the results of the dot product of vector A and vector B to obtain the values ​​of the corresponding rows and columns in the result matrix.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] The present invention outputs analog levels and measures optical power signals through the PL end of ZYNQ, uses the PS end to complete the calculation of the proportional coefficient, the confirmation of the delay time and the synchronous calibration, and completes the conversion and accumulation of the optical power signal to the standard result. Combining the flexibility of the PS end with the parallel processing capability and real-time capability of the PL end can effectively improve the signal processing efficiency. The present invention converts the data multiplication operation into the optical domain, realizing the acceleration of large-scale matrix multiplication. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a flow chart of a signal processing method of a ZYNQ-based optoelectronic matrix multiplication system according to an embodiment of the present invention.

[0047] Figure 2 It is a schematic diagram of the control flow of the PS end of an embodiment of the present invention.

[0048] Figure 3 Schematic diagram of the system structure of an embodiment of the present invention.

[0049] Figure 4 It is a schematic diagram of functional modules of an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0051] ZYNQ is divided into two parts: PS (Processing System) and PL (Progarmmable Logic, also known as FPGA). PS is ARM (Advanced RISC Machine) and PL is FPGA (Field Programmable Gate Array). When using ZYNQ, it is inevitable that the PS and PL need to communicate. In most cases, the PS is the master and the PL is the slave, and the PS-PL communication is realized through the AXI bus.

[0052] The MZI intensity modulator is a "MZM Mach-Zehnder Modulator".

[0053] Embodiment 1

[0054] like Figures 1 to 4 As shown, a signal processing method of a photoelectric matrix multiplication system based on ZYNQ in a preferred embodiment of the present invention includes ZYNQ and MZM intensity modulators, and ZYNQ includes a PS end and a PL end, including the following steps:

[0055] S1. The PS end configures an analog level signal with a preset waveform and sends multiple packets of data to the PL end in units of a single maximum transmission length;

[0056] S2, PL end receives the data sent by PS end, and outputs the data to MZM intensity modulator in the form of analog level, and at the same time receives the optical power signal modulated by MZM intensity modulator;

[0057] S3, PS reads the optical power signal received by PL, and confirms the synchronization and proportionality coefficient;

[0058] S4, the PS end is configured with an analog level signal for matrix multiplication operation, and sends a single row of vector multiplication data to the PL end;

[0059] S5, the PL end receives the data sent by the PS end and outputs the data in the form of analog level to the MZM intensity modulator, the MZM intensity modulator performs a vector multiplication operation to obtain a multiplication result, and the MZM intensity modulator outputs the multiplication result in the form of an optical power signal to the PL end;

[0060] S6, the PS side reads the multiplication result from the PL side, performs proportional conversion and accumulation operations, and calculates the matrix multiplication result;

[0061] S7. Execute steps S4 to S6 in a loop until every element in the matrix multiplication is calculated and the result is sent to the host computer.

[0062] This embodiment uses the PL end of ZYNQ to output analog levels and measure optical power signals, and uses the PS end to complete the calculation of proportional coefficients, confirmation of delay time and synchronous calibration, and complete the conversion and accumulation of optical power signals to standard results. Combining the flexibility of the PS end with the parallel processing capability and real-time capability of the PL end can effectively improve signal processing efficiency. And the data multiplication operation is converted to the optical domain, realizing the acceleration of large-scale matrix multiplication.

[0063] In this embodiment, the MZM intensity modulator includes a plurality of MZM structures, and the plurality of MZM structures are cascaded. The MZM cascade can improve the sensitivity and accuracy of sensing.

[0064] Furthermore, ZYNQ in this embodiment selects XC7Z020CLG400-2. The first addresses of the send data area and the receive data area are 0x01200000 and 0x01400000 respectively.

[0065] Embodiment 2

[0066] The difference between this embodiment and the first embodiment is that, based on the first embodiment, this embodiment provides a detailed description of steps S1 to S3.

[0067] A signal processing method of an optoelectronic matrix multiplication system based on ZYNQ in this embodiment includes ZYNQ, an MZM intensity modulator, DDR, an ADC chip and a DAC chip. The ZYNQ includes a PS end and a PL end. The PS end is connected to the DDR. The PL end includes an AXIDMA module, an ADC control module and a DAC control module. The PL end communicates with the PS end through the AXIDMA module. The ADC control module is connected to the ADC chip. The DAC control module is connected to the DAC chip. In addition, the PS end of this embodiment is connected to a host computer through a USB to serial port chip.

[0068] Specifically:

[0069] ADC chip: outputs the preset waveform or the vector to be multiplied to the IO port in the form of analog level, modulates the MZM intensity modulator for proportional calibration or vector multiplication;

[0070] DAC chip: receives modulated optical power signals or vector multiplied optical power signals, and transmits data to AXIDMA to wait for the PS end to initiate reception;

[0071] PL-side AXIDMA module: initiates data read commands to the PL side, or stores data from the PS side to the PL-side storage unit;

[0072] ADC control module at the PL end: responds to the data read command initiated by the PS end and outputs analog level from the IO port;

[0073] DAC control module at the PL end: responds to the data receiving command initiated by the PS end and receives the analog level from the external IO port;

[0074] PS side: initialize AXI control module and interrupt control module; initialize parameter registers; initiate send and receive commands to PL side; respond to AXI receive interrupt and send interrupt; and transmit matrix results to the host computer through USB to serial port chip;

[0075] DDR memory: stores preset waveforms and matrix data.

[0076] The method comprises the following steps:

[0077] S1, the PS end configures an analog level signal of a preset waveform, and sends multiple packets of data to the PL end in units of a single maximum transmission length; specifically, step S1 includes:

[0078] S101, the PS end initializes the AXIDMA module, opens the MM2S and S2MM channels, and opens the receive interrupt and the send interrupt;

[0079] S102, the PS terminal sets the value of the parameter register; wherein, in step S102, the value of the parameter register set includes: ADC zero level parameter V zero and the maximum length LEN of a single transmission; ZYNQ also includes parameter registers, which are used to store and transmit data. Through the parameter registers, data exchange and communication can be carried out between the PS and PL ends to achieve collaborative work.

[0080] S103, the PS terminal reads the 16-bit level data of the single maximum transmission length from the DDR, and sets the header address and transmission length of the transmission data;

[0081] S104, the PS end executes the transmission command and waits for the transmission completion interrupt;

[0082] S105, after receiving the transmission completion interrupt command, read the next packet of data in units of the single maximum transmission length, and repeat this cycle.

[0083] S2, the PL end receives the data sent by the PS end, and outputs the data to the MZM intensity modulator in the form of analog level, and receives the optical power signal modulated by the MZM intensity modulator at the same time; this embodiment receives the data through the DMA direct memory access module, and outputs the data in the form of analog level through the DAC. Specifically, step S2 includes:

[0084] S201, the PL side receives data from the PS side in packets and stores it into FIFO_0;

[0085] S202, after receiving all the data, the PL terminal sends an enable signal to the DAC control module and the ADC control module;

[0086] S203, after receiving the enable signal, the DAC control module takes out the data in FIFO_0, outputs the 14-bit data to the MZM intensity modulator through its IO port, and modulates the MZM intensity modulator to generate an optical power signal;

[0087] In step S203, the level signal modulates the MZM intensity modulator to generate an optical power signal: the MZM intensity modulator is set to operate at the bias point V π , when the MZM intensity modulator operates at the bias point V π When the level V is applied, the optical power is P = P0 (1 + kV), where k is a priori value;

[0088] S204, after receiving the enable signal, the ADC control module at the PL end enables the data valid signal of the ADC control module, reads 12-bit digital level data from the IO port of the ADC control module, and inputs the data into FIFO_2 in the form of data stream;

[0089] S205 . After receiving the data with a length of LEN, enable the S2MM data transmission channel, read the FIFO_2 data in units of a single maximum transmission length, and transmit the data to the AXIDMA module.

[0090] S3, the PS end reads the optical power signal received by the PL end, performs synchronization and confirms the proportional coefficient; specifically, step S3 includes:

[0091] The PS side compares the received data with the sent data and calculates the number of clock cycles between sending and receiving. π The level at the bias point is converted to a standard value between 0 and 2; the proportional coefficient of the level signal and the optical power conversion is calculated;

[0092] The standard value between 0 and 2 is: P / P0 = (1 + kV), the ratio of the modulated optical power to the bias point optical power. For the MZM intensity modulator, the maximum optical power is Vπ Twice the bias point power, P / P0 is a positive real value not greater than 2.

[0093] S4. The PS end is configured with an analog level signal for matrix multiplication operation and sends a single row of vector multiplication data to the PL end.

[0094] S5. The PL end receives the data sent by the PS end and outputs the data in the form of analog level to the MZM intensity modulator. The MZM intensity modulator performs a vector multiplication operation to obtain the multiplication result. The MZM intensity modulator outputs the multiplication result to the PL end in the form of an optical power signal.

[0095] S6. The PS side reads the multiplication result from the PL side, performs proportional conversion and accumulation operations, and calculates the matrix multiplication result.

[0096] S7. Execute steps S4 to S6 in a loop until every element in the matrix multiplication is calculated and the result is sent to the host computer.

[0097] Embodiment 3

[0098] The difference between this embodiment and the second embodiment is that, based on the second embodiment, this embodiment further illustrates steps S4 to S6.

[0099] A signal processing method of an optoelectronic matrix multiplication system based on ZYNQ in this embodiment includes ZYNQ, an MZM intensity modulator, DDR, an ADC chip and a DAC chip. The ZYNQ includes a PS end and a PL end. The PS end is connected to the DDR. The PL end includes an AXIDMA module, an ADC control module and a DAC control module. The PL end communicates with the PS end through the AXIDMA module. The ADC control module is connected to the ADC chip. The DAC control module is connected to the DAC chip. The method includes the following steps:

[0100] S1. The PS end configures an analog level signal with a preset waveform and sends multiple packets of data to the PL end in units of a single maximum transmission length.

[0101] S2 and PL receive the data sent by the PS end, and output the data to the MZM intensity modulator in the form of analog level, and at the same time receive the optical power signal modulated by the MZM intensity modulator.

[0102] S3. The PS end reads the optical power signal received by the PL end and performs synchronization and proportional coefficient confirmation.

[0103] S4, the PS end configures an analog level signal for performing matrix multiplication operation, and sends a single row of vector multiplication data to the PL end; specifically, step S4 includes:

[0104] S401, the PS end reads vector A and vector B whose elements are stored in 16-bit form from the DDR, and after encoding the same code element twice with +V and -V, for a single element to be transmitted that is a 32-bit array, the lower 16 bits store vector A data, and the upper 16 bits store vector B data;

[0105] S402, setting the head address and transmission length of the transmission data through the host computer; the PS end executes the transmission command and waits for the transmission completion interrupt;

[0106] S403, after receiving the transmission completion interrupt command, read the next packet of data in units of the single maximum transmission length, and repeat this cycle until the two column vectors are transmitted.

[0107] S5, the PL end receives the data sent by the PS end and outputs the data in the form of analog level to the MZM intensity modulator, the MZM intensity modulator performs a vector multiplication operation to obtain a multiplication result, and the MZM intensity modulator outputs the multiplication result in the form of an optical power signal to the PL end; specifically, step S5 includes:

[0108] S501, the PL receives data from the PS in packets, and stores them into FIFO_0 and FIFO_1 respectively according to the high 16 bits as vector A and the low 16 bits as vector B;

[0109] S502, after receiving all the data, the PL terminal sends an enable signal to the DAC control module and the ADC control module;

[0110] S503, after receiving the enable signal, the DAC control module takes out the data in FIFO_0 and FIFO_1, and outputs the data from the dual channels ch1 and ch2 to the IO port to the MZM intensity modulator in the form of 14-bit data; the cascaded MZM intensity modulator completes the vector multiplication operation; after receiving the enable signal, the ADC control module at the PL end enables the data valid signal of the ADC control module, reads the 12-bit digital level data from the IO port of the ADC control module, and inputs it into FIFO_2 in the form of data stream;

[0111] In step 503, the operation of vector multiplication performed by the cascaded MZM intensity modulators is: when the analog levels of V1 and V2 are applied to the cascaded MZM intensity modulators respectively, the optical power thereof is P=P0(1+kV1)(1+kV2);

[0112] S504, after receiving the data with a length of LEN, enable the S2MM data transmission channel, read the FIFO_2 data in units of a single maximum transmission length, and transmit the multiplication result data in the form of an optical power signal to the DMA direct memory reading module.

[0113] S6, the PS end reads the multiplication result from the PL end, performs proportional conversion and accumulation operations, and calculates to obtain the matrix multiplication result; specifically, step S6 includes:

[0114] S601, determining an interval of valid data in the received data according to the delay time period and the proportionality coefficient calculated in step S2;

[0115] S602, according to the size of the matrix, the received data is divided and spliced, and the corresponding rows and columns are used as units for sorting; V is calculated π is the level size at the bias point, and converts the data into a standard value between 0 and 2, and converts the standard value into the result of the dot product of vector A and vector B according to the proportional coefficient calculated in step S2; wherein, the method for converting the standard value into the result of the dot product of vector A and vector B is: according to the method mentioned in step S4 for encoding the same code element twice with +V and -V, for the multiplication result of the optical powers of V1 and V2, there will be P1=P0(1+kV1)(1+kV2) and P2=P0(1-kV1)(1-kV2), and P1+P2=2P0(1+k 2 V1V2), and V1V2=[(P1 / P0+P2 / P0) / 2-1] / (k 2 ), where k is the proportionality coefficient obtained in step S3, and P1 / P0 and P2 / P0 are standard values ​​obtained respectively;

[0116] S603 , sum the results of the dot product of vector A and vector B to obtain the values ​​of the corresponding rows and columns in the result matrix.

[0117] S7, loop through the steps of S4 to S6 until each element in the matrix multiplication is calculated, and the result is sent to the host computer. In this embodiment, the method of transmitting to the host computer in step S7 is serial communication, and the UART (Universal Serial Asynchronous Receiver Transmitter) interface protocol is used to transmit the matrix data.

[0118] In summary, the embodiment of the present invention provides a signal processing method for an optoelectronic matrix multiplication system based on ZYNQ, which outputs analog levels and measures optical power signals through the PL end of ZYNQ, uses the PS end to complete the calculation of the proportional coefficient, the confirmation of the delay time and the synchronous calibration, and completes the conversion and accumulation of the optical power signal to the standard result. Combining the flexibility of the PS end with the parallel processing capability and real-time capability of the PL end can effectively improve the signal processing efficiency. And the data multiplication operation is converted into the optical domain, realizing the acceleration of large-scale matrix multiplication.

[0119] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and substitutions can be made without departing from the technical principles of the present invention. These improvements and substitutions should also be regarded as the scope of protection of the present invention.

Claims

1. A signal processing method for an optoelectronic matrix multiplication system based on ZYNQ, characterized in that: The invention comprises a ZYNQ and an MZM intensity modulator, wherein the ZYNQ comprises a PS end and a PL end, and comprises the following steps: S1. The PS end configures an analog level signal with a preset waveform and sends multiple packets of data to the PL end in units of a single maximum transmission length; S2, PL end receives the data sent by PS end, and outputs the data to MZM intensity modulator in the form of analog level, and at the same time receives the optical power signal modulated by MZM intensity modulator; S3, PS reads the optical power signal received by PL, and confirms the synchronization and proportionality coefficient; S4, the PS end is configured with an analog level signal for matrix multiplication operation, and sends a single row of vector multiplication data to the PL end; S5, the PL end receives the data sent by the PS end and outputs the data in the form of analog level to the MZM intensity modulator, the MZM intensity modulator performs a vector multiplication operation to obtain a multiplication result, and the MZM intensity modulator outputs the multiplication result in the form of an optical power signal to the PL end; S6, the PS side reads the multiplication result from the PL side, performs proportional conversion and accumulation operations, and calculates the matrix multiplication result; S7. Execute steps S4 to S6 in a loop until every element in the matrix multiplication is calculated and the result is sent to the host computer.

2. The signal processing method of the optoelectronic matrix multiplication system based on ZYNQ according to claim 1, characterized in that: It also includes DDR, ADC chip and DAC chip, the PS end is connected to DDR, the PL end includes AXIDMA module, ADC control module and DAC control module, the PL end communicates with the PS end through the AXIDMA module, the ADC control module is connected to the ADC chip, and the DAC control module is connected to the DAC chip, and step S1 includes: S101, PS end initializes AXIDMA module, opens MM2S and S2MM channels, opens receive interrupt and send interrupt; S102, the PS terminal sets the value of the parameter register; S103, the PS terminal reads the 16-bit level data of the single maximum transmission length from the DDR, and sets the header address and transmission length of the transmission data; S104, the PS end executes the transmission command and waits for the transmission completion interrupt; S105, after receiving the transmission completion interrupt command, read the next packet of data in units of the single maximum transmission length, and repeat this cycle.

3. The signal processing method of the optoelectronic matrix multiplication system based on ZYNQ according to claim 2, characterized in that: In step S102, the value parameters of the parameter registers set include: ADC zero level parameter V zero And the maximum length of a single transmission is LEN.

4. The signal processing method of the optoelectronic matrix multiplication system based on ZYNQ according to claim 3, characterized in that: Step S2 includes: S201, the PL side receives data from the PS side in packets and stores it into FIFO_0; S202, after receiving all the data, the PL terminal sends an enable signal to the DAC control module and the ADC control module; S203, after receiving the enable signal, the DAC control module takes out the data in FIFO_0, outputs the 14-bit data to the MZM intensity modulator through its IO port, and modulates the MZM intensity modulator to generate an optical power signal; S204, after receiving the enable signal, the ADC control module at the PL end enables the data valid signal of the ADC control module, reads 12-bit digital level data from the IO port of the ADC control module, and inputs the data into FIFO_2 in the form of data stream; S205 . After receiving the data with a length of LEN, enable the S2MM data transmission channel, read the FIFO_2 data in units of a single maximum transmission length, and transmit the data to the AXIDMA module.

5. The signal processing method of the optoelectronic matrix multiplication system based on ZYNQ according to claim 4, characterized in that: In step S203, the level signal modulates the MZM intensity modulator to generate an optical power signal: the MZM intensity modulator is set to operate at the bias point V π , when the MZM intensity modulator operates at the bias point V π When the level V is applied, the optical power is P=P0(1+kV), where k is a priori value.

6. The signal processing method of the optoelectronic matrix multiplication system based on ZYNQ according to claim 5, characterized in that: Step S3 includes: The PS side compares the received data with the sent data and calculates the number of clock cycles between sending and receiving. π The level at the bias point is converted to a standard value between 0 and 2; the proportional coefficient of the level signal and the optical power conversion is calculated; The standard value between 0 and 2 is: P / P0 = (1 + kV), the ratio of the modulated optical power to the bias point optical power. For the MZM intensity modulator, the maximum optical power is V π Twice the bias point power, P / P0 is a positive real value not greater than 2.

7. The signal processing method of the optoelectronic matrix multiplication system based on ZYNQ according to claim 6, characterized in that: Step S4 includes: S401, the PS end reads vector A and vector B whose elements are stored in 16-bit form from the DDR, and after encoding the same code element twice with +V and -V, for a single element to be transmitted that is a 32-bit array, the lower 16 bits store vector A data, and the upper 16 bits store vector B data; S402, setting the head address and transmission length of the transmission data through the host computer; the PS end executes the transmission command and waits for the transmission completion interrupt; S403, after receiving the transmission completion interrupt command, read the next packet of data in units of the single maximum transmission length, and repeat this cycle until the two column vectors are transmitted.

8. The signal processing method of the optoelectronic matrix multiplication system based on ZYNQ according to claim 7, characterized in that: Step S5 includes: S501, the PL receives data from the PS in packets, and stores them into FIFO_0 and FIFO_1 respectively according to the high 16 bits as vector A and the low 16 bits as vector B; S502, after receiving all the data, the PL terminal sends an enable signal to the DAC control module and the ADC control module; S503, after receiving the enable signal, the DAC control module takes out the data in FIFO_0 and FIFO_1, and outputs the data from the dual channels ch1 and ch2 to the IO port to the MZM intensity modulator in the form of 14-bit data; the cascaded MZM intensity modulator completes the vector multiplication operation; after receiving the enable signal, the ADC control module at the PL end enables the data valid signal of the ADC control module, reads the 12-bit digital level data from the IO port of the ADC control module, and inputs it into FIFO_2 in the form of data stream; S504, after receiving the data with a length of LEN, enable the S2MM data transmission channel, read the FIFO_2 data in units of a single maximum transmission length, and transmit the multiplication result data in the form of an optical power signal to the DMA direct memory reading module.

9. The signal processing method of the optoelectronic matrix multiplication system based on ZYNQ according to claim 8, characterized in that: In step 503, the vector multiplication operation performed by the cascaded MZM intensity modulators is: when the analog levels of V1 and V2 are applied to the cascaded MZM intensity modulators respectively, the optical power thereof is P=P0(1+kV1)(1+kV2).

10. The signal processing method of the optoelectronic matrix multiplication system based on ZYNQ according to claim 9, characterized in that: Step S6 includes: S601, determining an interval of valid data in the received data according to the delay time period and the proportionality coefficient calculated in step S2; S602, according to the size of the matrix, the received data is divided and spliced, and the corresponding rows and columns are used as units for sorting; V is calculated π is the level size at the bias point, and converts the data into a standard value between 0 and 2, and converts the standard value into the result of the dot product of vector A and vector B according to the proportional coefficient calculated in step S2; wherein, the method for converting the standard value into the result of the dot product of vector A and vector B is: according to the method mentioned in step S4 for encoding the same code element twice with +V and -V, for the multiplication result of the optical powers of V1 and V2, there will be P1=P0(1+kV1)(1+kV2) and P2=P0(1-kV1)(1-kV2), and P1+P2=2P0(1+k 2 V1V2), and V1V2=[(P1 / P0+P2 / P0) / 2-1] / (k 2 ), where k is the proportionality coefficient obtained in step S3, and P1 / P0 and P2 / P0 are standard values ​​obtained respectively; S603 , sum the results of the dot product of vector A and vector B to obtain the values ​​of the corresponding rows and columns in the result matrix.

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