Mixed domain multiply-accumulate calculation circuit based on bit rotation input

Abstract

The invention discloses a mixed domain multiply-accumulate calculation circuit based on bit rotation input, which is used for supporting the design of a calculation macro cell and an accelerator in a digital and analog mixed domain memory, and belongs to the technical field of special integrated circuit design. On the basis of an input mode of bit rotation, a digital and analog mixed domain in-memory computing architecture is designed, and two computing modes of an unsigned number and a signed number are supported. Compared with a traditional bit parallel and bit serial input mixed domain in-memory calculation structure, the bit rotation input technology is adopted, the same calculation precision of a bit parallel mode is achieved with the same hardware overhead of a bit serial mode, low hardware overhead and high calculation precision are both considered, and the comprehensive performance of a calculation framework and a circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a mixed-domain multiplication-accumulation calculation circuit based on bit rotation input. Background Art

[0002] Under the requirements of high efficiency and high computing density, computing in memory (CIM) technology has gradually become an important direction of processor design. By integrating multiply and accumulate (MAC) operations directly into the storage array, CIM significantly reduces the energy consumption caused by repeated data transmission between the processor and the memory, and solves the bottleneck problem of the "storage wall" in the von Neumann architecture. In edge artificial intelligence applications, the CIM architecture has attracted widespread attention due to its high energy efficiency. However, in the traditional CIM structure, the calculation method used usually has high hardware overhead and limited calculation accuracy. In the application of neural networks, the amount of data is large and the degree of parallelism is high. Therefore, a low-power and high-efficiency calculation method is needed to improve the overall performance of in-memory computing. Currently, in-memory computing mostly uses bit-parallel or bit-serial input methods. Although basic MAC operations are implemented, the hardware overhead is high or the accuracy is insufficient, which makes it difficult to meet complex computing requirements. Summary of the invention

[0003] The present invention provides a mixed domain multiplication-accumulation calculation circuit based on bit rotation input to solve the technical problem that the existing single-precision floating-point quantization method is not compatible with the accelerator (macro unit) design of the floating-point in-memory calculation unit.

[0004] An embodiment of the present invention provides a mixed domain multiplication-accumulation calculation circuit based on bit rotation input, comprising: a collection buffer area, a rotation shift input unit and a digital-analog mixed in-memory calculation SRAM array embedded with sign bit processing; the collection buffer area collects serial input data through multiple internal triggers, and passes the data to the rotation shift input unit in the form of parallel output, and compresses multiple multiplication results into a single multiplication-accumulation result by rotating and shifting the input data, and performs multiplication-accumulation calculation in combination with the digital-analog mixed in-memory calculation array embedded with sign bit processing.

[0005] Optionally, in one embodiment of the present invention, the data mapping input method of the mixed domain multiplication and accumulation calculation circuit is: in each cycle, the data is passed bit by bit to adjacent triggers in sequence through rotation and shift operations, so that the input data bits and weight bits are aligned one by one, and partial results of the multiplication and accumulation are updated in each cycle.

[0006] Optionally, in one embodiment of the present invention, each rotation shift input unit includes two 2-to-1 multiplexers and one D flip-flop, supporting two modes selected by the 2-to-1 multiplexers: extraction mode and rotation mode; in the extraction mode, the rotation shift input unit obtains data from the collection buffer area, and in the rotation mode, each rotation shift input unit transfers the data to the adjacent D flip-flop by bit rotation shift cycle by cycle.

[0007] Optionally, in one embodiment of the present invention, a complete rotate-shift-multiply-accumulate operation includes one extraction cycle and seven rotation cycles, during which characteristic data will be transferred between adjacent D flip-flops on the same side of multiple rotate-shift input units: the D flip-flop on the left transfers data to the adjacent left flip-flop, the D flip-flop on the right transfers data to the adjacent right flip-flop, and the left D flip-flop of the last rotate-shift input unit transfers data to the right D flip-flop of the first rotate-shift input unit when transferring data.

[0008] Optionally, in one embodiment of the present invention, the digital-analog hybrid in-memory computing SRAM array includes a sign bit multiplication-addition unit and a digital-analog hybrid multiplication-addition unit;

[0009] The sign bit multiplication and addition unit includes 16 6T-SRAM units, a sign bit extension unit and a selective inversion digital multiplier. In each cycle, a 1-bit weight is read from the 16 6T-SRAMs and multiplied with the input 2-bit feature data. The sign bit extension unit is used to store the sign bit product result in a register and reuse the accumulation in multi-cycle calculation through an adder. The selective inversion digital multiplier is used to select and output the original multiplication result or the inversion result according to the input sign bit.

[0010] The digital-analog mixed multiplication and addition unit includes 16 6T-SRAM units, a selective inversion digital multiplier and an analog multiplier. The selective inversion digital multiplier outputs the result of the digital part, and the analog multiplier outputs the result of the analog part, thereby realizing digital-analog mixed calculation.

[0011] Optionally, in one embodiment of the present invention, the mixed domain multiplication-accumulation calculation circuit supports a signed calculation mode and an unsigned calculation mode; wherein, in the signed mode, the sign bit extension unit stores the sign bit product result of the previous cycle in a register, and is multiplexed and accumulated by the adder, and cooperates with the result of the mixed digital-analog multiplication-addition unit to correctly handle the sign information in the multi-cycle calculation; in the unsigned mode, the original multiplication result is directly output, and the sign bit extension unit does not perform sign bit extension and directly outputs the original result.

[0012] The mixed domain multiplication and accumulation calculation circuit based on bit rotation input of the embodiment of the present invention is suitable for efficient multiplication and accumulation of mixed analog and digital in-memory computing units. Through the rotation shift input mode and the in-memory computing SRAM array with embedded sign bit processing, the hardware overhead is significantly reduced while ensuring high calculation accuracy. This method realizes efficient utilization of hardware resources by rotating the input data for transmission and mixing accumulation in the analog and digital domains, solving the problems of high hardware cost and limited accuracy in traditional computing structures, and is suitable for application in low-power, high-efficiency edge AI accelerator design.

[0013] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0015] Figure 1 A schematic diagram of the overall structure of a mixed-domain multiplication-accumulation calculation circuit based on bit rotation input according to an embodiment of the present invention;

[0016] Figure 2 It is a schematic diagram of the multiplication and accumulation operation flow of the digital part, the analog part and the sign bit part of an embodiment of the present invention;

[0017] Figure 3 It is a schematic diagram of the working structure of the rotation shift input unit in the extraction mode and the rotation mode according to an embodiment of the present invention;

[0018] Figure 4 Schematic diagram of the operation of the SRAM array in the digital-analog hybrid in-memory computing in signed / unsigned mode according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0020] In order to solve the problems of the background technology, the present invention proposes a mixed domain multiplication and accumulation calculation circuit based on bit rotation input, and a multiplication and accumulation calculation method based on rotation shift input. Through a hybrid storage array of rotation input and embedded sign bit processing, a low hardware overhead and high-precision calculation method is realized, which is suitable for edge AI and high-performance neural network applications.

[0021] Figure 1The present invention is a schematic diagram of the overall structure of a mixed-domain multiplication-accumulation calculation circuit based on bit rotation input according to an embodiment of the present invention.

[0022] like Figure 1 As shown, the mixed domain multiplication-accumulation calculation circuit based on bit rotation input includes: a collection buffer area, a rotation shift input unit and a digital-analog mixed in-memory calculation SRAM array embedded with sign bit processing.

[0023] The collection buffer collects serial input data through multiple internal triggers and passes the data to the rotation and shift input unit in the form of parallel output. By rotating and shifting the input data, multiple multiplication results are compressed into a single multiplication-accumulation result, and multiplication and accumulation calculations are performed in combination with a mixed digital-analog in-memory computing array embedded with sign bit processing.

[0024] The invention discloses a multiplication-accumulation calculation method based on rotation shift input of a mixed domain multiplication-accumulation calculation circuit based on bit rotation input, which is used to support efficient multiplication-accumulation calculation. In this structure, multiple multiplication results are compressed into a single multiplication-accumulation result by rotating and shifting the input data, and combined with a mixed digital-analog in-memory calculation array embedded with a sign bit processing unit, low hardware overhead and high-precision multiplication-accumulation calculation are achieved.

[0025] The collection buffer is used to collect serial input data and pass the data to the rotation input unit through parallel output. In each collection buffer, there are 8 triggers responsible for collecting serial input data and passing the data to 8 rotation input units in parallel.

[0026] The mixed domain multiplication-accumulation computing architecture based on bit-rotated input is used to support the design of digital and analog mixed domain in-memory computing macro units and accelerators. This circuit proposes a bit-rotated data mapping input method, and based on this, a digital and analog mixed domain in-memory computing architecture is designed, which supports both unsigned and signed computing modes.

[0027] The bit-rotated data mapping input method is as follows: in each cycle, the data is passed bit by bit to the adjacent flip-flops through the rotation shift operation, so that the input data bits are aligned with the weight bits one by one, and the partial results of the multiplication and accumulation are updated in each cycle.

[0028] Specifically, Figure 2 As shown in the figure, the bit-rotated data mapping input method is a method to achieve efficient data alignment by rotating and shifting cycle by cycle. In each calculation cycle, the input data is transmitted by bit rotation so that the input data bits are aligned with the weight bits one by one, which is used to update the partial results of multiplication and accumulation in each cycle. This data mapping method relies on the D flip-flop chain structure of the rotation input unit.

[0029] In one embodiment of the present invention, Figure 3 As shown, each rotation shift input unit consists of two 2-to-1 multiplexers and a D flip-flop, and the two modes selected by the 2-to-1 multiplexer are "extraction mode" and "rotation mode". In the extraction mode, the rotation shift input unit obtains data from the collection buffer, and the 8-bit feature data enters the left D flip-flop of each rotation shift input unit, and 8 zeros enter the right D flip-flop to prepare for the rotation operation. In the rotation mode, the rotation shift input unit transfers the data to the adjacent D flip-flop by bit rotation shift cycle by cycle.

[0030] Furthermore, a complete rotate-shift-multiply-accumulate operation includes one extraction cycle and seven rotation cycles, such as Figure 2 As shown. In the rotation cycle, the characteristic data will be transferred between the adjacent D flip-flops on the same side of the 8 rotation shift input units: the D flip-flop on the left transfers the data to the adjacent left flip-flop, and the D flip-flop on the right transfers the data to the adjacent right flip-flop. When the left D flip-flop of the last rotation shift input unit transfers the data, it transfers the data to the right D flip-flop of the first rotation shift input unit. This design ensures that only one characteristic data bit is transferred in each rotation cycle, achieving efficient data flow transfer.

[0031] In one embodiment of the present invention, the mixed digital-analog in-memory computing SRAM array includes a sign bit multiplication-addition unit and a mixed digital-analog multiplication-addition unit.

[0032] Sign bit multiplication and addition unit: It consists of 16 6T-SRAM units, a selective inversion digital multiplier, and a sign bit extension unit. In each cycle, a 1-bit weight is read from the 16 6T-SRAMs and multiplied with the input 2-bit feature data. The selective inversion digital multiplier is used for multiplication calculations in the digital part, and outputs the original multiplication result or the inversion result according to the input sign bit. The sign bit extension unit is responsible for storing the sign bit product result in a register, and reuses the accumulation in multi-cycle calculations through the adder to ensure the correct processing of the sign information.

[0033] Digital-analog hybrid multiplication and addition unit: It consists of 16 6T-SRAM units, a selective inversion digital multiplier and an analog multiplier. The selective inversion digital multiplier outputs the result of the digital part, and the analog multiplier outputs the result of the analog part, realizing digital-analog hybrid calculation, supporting both signed and unsigned operation modes.

[0034] In one embodiment of the present invention, Figure 4As shown, the mixed digital-analog in-memory computing SRAM array supports signed computing mode and unsigned computing mode; wherein, in the signed mode, the sign bit extension unit stores the sign bit product result of the previous cycle in a register, and is multiplexed and accumulated by the adder, and cooperates with the result of the mixed digital-analog multiplication and addition unit to correctly handle the sign information in multi-cycle calculations; in the unsigned mode, the original multiplication result is directly output, and the sign bit extension unit does not perform sign bit extension and directly outputs the original result.

[0035] The digital-analog hybrid in-memory computing SRAM array of the present invention supports two computing modes: signed mode and unsigned mode:

[0036] In signed mode, the sign bit processing is divided into two parts: (1) Selective inversion: The selective inversion digital multiplier will choose to output the original multiplication result or the inverted result according to the sign bit of the multiplier (for example, F[7]); (2) Sign bit extension: The sign bit extension unit stores the sign bit product result of the previous cycle (for example, p07, p17, etc.) in a register and multiplexes it through the adder to ensure the correct propagation of sign information in multi-cycle calculations.

[0037] In the unsigned mode, the selective inversion digital multiplier directly outputs the original multiplication result. At this time, the sign bit extension unit does not perform sign bit extension and directly accumulates the unsigned product result.

[0038] In one embodiment of the present invention, the post-processing unit accumulates the calculation results of the analog part and the digital part respectively in each cycle. Figure 2 As shown, finally, the sign bit product result is accumulated to the final multiplication-addition result through the sign bit extension unit, and the complete multiplication-addition result is obtained in the 7th cycle, ensuring the correctness of the calculation result.

[0039] According to the mixed domain multiplication and accumulation calculation circuit based on bit rotation input proposed in the embodiment of the present invention, a digital and analog mixed domain in-memory calculation architecture is designed based on the bit rotation input mode, supporting two calculation modes of unsigned numbers and signed numbers. Compared with the traditional bit parallel and bit serial input mixed domain in-memory calculation structure, the present invention adopts bit rotation input technology, and achieves the same calculation accuracy of the bit parallel mode with the same hardware overhead of the bit serial mode, taking into account low hardware overhead and high calculation accuracy, and improving the comprehensive performance of the calculation architecture and circuit.

[0040] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. A mixed domain multiplication-accumulation calculation circuit based on bit rotation input, characterized in that: include: Collect buffers, rotate and shift input units, and a hybrid in-memory computation SRAM array for embedded sign bit processing; The collection buffer area collects serial input data through multiple internal triggers and passes the data to the rotation and shift input unit in the form of parallel output. By rotating and shifting the input data, multiple multiplication results are compressed into a single multiplication-accumulation result, and multiplication and accumulation calculations are performed in combination with a mixed digital-analog in-memory calculation array embedded with sign bit processing.

2. The mixed domain multiplication-accumulation calculation circuit based on bit rotation input according to claim 1, characterized in that: The data mapping input method of the mixed domain multiplication and accumulation calculation circuit is as follows: in each cycle, the data is transferred bit by bit to the adjacent triggers through rotation and shift operations, so that the input data bits are aligned with the weight bits one by one, and the partial results of the multiplication and accumulation are updated in each cycle.

3. The mixed domain multiplication-accumulation calculation circuit based on bit rotation input according to claim 1, characterized in that: Each rotation shift input unit includes two 2-to-1 multiplexers and a D flip-flop, supporting two modes selected by the 2-to-1 multiplexer: extraction mode and rotation mode; in the extraction mode, the rotation shift input unit obtains data from the collection buffer area, and in the rotation mode, each rotation shift input unit transfers the data to the adjacent D flip-flop by bit rotation shift cycle by cycle.

4. The mixed domain multiplication-accumulation calculation circuit based on bit rotation input according to claim 3, characterized in that: A complete rotate-shift-multiply-accumulate operation includes one extraction cycle and seven rotation cycles. During the rotation cycle, the feature data will be transferred between adjacent D flip-flops on the same side of multiple rotate-shift input units: the D flip-flop on the left transfers data to the adjacent left flip-flop, the D flip-flop on the right transfers data to the adjacent right flip-flop, and the left D flip-flop of the last rotate-shift input unit transfers data to the right D flip-flop of the first rotate-shift input unit when transferring data.

5. The mixed domain multiplication-accumulation calculation circuit based on bit rotation input according to claim 1, characterized in that: The digital-analog hybrid in-memory calculation SRAM array includes a sign bit multiplication-addition unit and a digital-analog hybrid multiplication-addition unit; The sign bit multiplication and addition unit includes 16 6T-SRAM units, a sign bit extension unit and a selective inversion digital multiplier. In each cycle, a 1-bit weight is read from the 16 6T-SRAMs and multiplied with the input 2-bit feature data. The sign bit extension unit is used to store the sign bit product result in a register and reuse the accumulation in multi-cycle calculation through an adder. The selective inversion digital multiplier is used to select and output the original multiplication result or the inversion result according to the input sign bit. The digital-analog mixed multiplication and addition unit includes 16 6T-SRAM units, a selective inversion digital multiplier and an analog multiplier. The selective inversion digital multiplier outputs the result of the digital part, and the analog multiplier outputs the result of the analog part, thereby realizing digital-analog mixed calculation.

6. The mixed domain multiplication-accumulation calculation circuit based on bit rotation input according to claim 5, characterized in that: The mixed domain multiplication and accumulation calculation circuit supports signed calculation mode and unsigned calculation mode; in the signed mode, the sign bit extension unit stores the sign bit product result of the previous cycle in the register, and the adder reuses the accumulation, and cooperates with the result of the mixed digital-analog multiplication and addition unit to correctly handle the sign information in multi-cycle calculation; in the unsigned mode, the original multiplication result is directly output, and the sign bit extension unit directly outputs the original result without performing sign bit extension.

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