Method for processing surface of large-size cadmium zinc telluride substrate

Abstract

The invention discloses a large-size tellurium-zinc-cadmium substrate surface processing method which comprises the following steps: obtaining a cut tellurium-zinc-cadmium wafer, and polishing a first surface of the tellurium-zinc-cadmium wafer until cutting fluctuation on the surface of the first surface is removed to obtain a first wafer; carrying out thinning treatment on the second surface of the tellurium-zinc-cadmium wafer, and then carrying out mechanical polishing on the second surface of the tellurium-zinc-cadmium wafer to obtain a second wafer; taking down the second wafer from the thinned slide, carrying out an X-ray diffraction appearance test to obtain an X-ray diffraction morphology graph corresponding to the second wafer, selecting an area with uniform contrast on the X-ray diffraction morphology graph, and marking the corresponding position of the second wafer; cutting the second wafer into a cadmium zinc telluride substrate in a regular shape according to the mark at the corresponding position of the second wafer; and placing the tellurium-zinc-cadmium substrate on the polishing slide glass for substrate polishing treatment, performing gluing protection on the polished tellurium-zinc-cadmium substrate, taking down the tellurium-zinc-cadmium substrate from the polishing slide glass, and cleaning the tellurium-zinc-cadmium substrate to obtain the processed tellurium-zinc-cadmium substrate.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor material processing, and in particular to a surface processing method for a large-size cadmium zinc telluride substrate. Background Art

[0002] CdZnTe single crystal material is the best substrate material for preparing high-performance HgCdTe infrared focal plane detectors. Large-size CdZnTe substrates are not only required for the development of high-resolution, large-array HgCdTe infrared detectors, but also one of the most effective means to improve the efficiency of HgCdTe epitaxy and device front-end tape-out. By improving the processing technology of large-size CdZnTe substrates, it can support the development and production of larger quantities of second-generation and third-generation HgCdTe infrared detectors.

[0003] Generally, the processing of CdZnTe wafers involves chamfering, grinding, polishing, cleaning and other steps. As the diameter of CdZnTe crystals increases, when the wafer size after slicing reaches 50mm×50mm or more, in order to obtain a better surface shape and surface state and lay the foundation for subsequent polishing, it is necessary to remove the surface undulations and damaged layers of the substrate through a grinding process. However, whether in the chamfering process or the grinding process before grinding, the risk of fragmentation of large-sized CdZnTe wafers is relatively high, resulting in a low yield of large-sized wafers and a waste of materials. In addition, the surface flatness of the wafer after processing is also difficult to control, which in turn affects the subsequent epitaxial process and device interconnection process.

[0004] In view of this, how to provide a surface processing method for large-size CdZnTe substrates with high efficiency, low fragmentation rate and good flatness to avoid damage or cracks to the cut crystals during the cutting process and reduce substrate losses has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The embodiment of the present application provides a large-size cadmium zinc telluride substrate surface processing method, which is used to solve the problem of damage or cracks to the cut crystal during the current cutting process, resulting in substrate loss.

[0006] In a first aspect of an embodiment of the present application, a large-size cadmium zinc telluride substrate surface processing method is provided, comprising:

[0007] Obtaining a cadmium zinc telluride wafer that has been cut, placing the cadmium zinc telluride wafer on a polishing carrier with the first surface facing upward, and performing a polishing process on the first surface until the cutting undulations on the surface of the first surface are removed, thereby obtaining a first wafer;

[0008] With the second surface facing upward, the first wafer is removed from the polishing carrier, placed on a thinning carrier, the second surface is thinned, and the second surface of the cadmium zinc telluride wafer is mechanically polished to obtain a second wafer, wherein the thickness of the second wafer meets a preset thickness condition, and the flatness of the second wafer meets a preset flatness;

[0009] The second wafer is removed from the thinned carrier, and an X-ray diffraction profile test is performed to obtain an X-ray diffraction profile image corresponding to the second wafer, and an area with uniform contrast on the X-ray diffraction profile image is selected and marked at a corresponding position of the second wafer;

[0010] According to the marks at corresponding positions of the second wafer, the second wafer is cut into cadmium zinc telluride substrates of regular shapes;

[0011] The CdZnTe substrate is placed on a polishing carrier to perform substrate polishing treatment, the CdZnTe substrate after polishing is coated with glue for protection, and after being removed from the polishing carrier, the CdZnTe substrate is cleaned to obtain a processed CdZnTe substrate.

[0012] In an optional embodiment, placing the cadmium zinc telluride wafer on a polishing carrier and polishing the first surface until the cutting undulations on the surface of the first surface are removed to obtain a first wafer comprises:

[0013] The cadmium zinc telluride wafer is attached to a polishing carrier using adhesive wax, and the first surface is polished using a first polishing liquid until the cutting undulations on the surface of the first surface are removed to obtain a first wafer, wherein the first polishing liquid is a diamond polishing liquid with a particle size range within a first particle size threshold range.

[0014] In an optional embodiment, the thinning process is performed on the second surface, and then the second surface of the cadmium zinc telluride wafer is mechanically polished to obtain the second wafer, including:

[0015] The second surface is thinned by using a grinding wheel thinning machine, and the second surface of the cadmium zinc telluride wafer is mechanically polished by using a first polishing liquid to obtain a second wafer, wherein the first polishing liquid is a diamond polishing liquid having a particle size range within a first particle size threshold range.

[0016] In an optional embodiment, placing the cadmium zinc telluride substrate on a polishing carrier to perform substrate polishing treatment includes:

[0017] Placing the cadmium zinc telluride substrate on a polishing carrier, and performing mechanical polishing using a second polishing liquid to obtain a first cadmium zinc telluride substrate, wherein the second polishing liquid is a diamond polishing liquid having a particle size range within a second particle size threshold range;

[0018] The first cadmium zinc telluride substrate is chemically mechanically polished using a third polishing liquid to obtain a second cadmium zinc telluride substrate, wherein the third polishing liquid is a silica sol polishing liquid with a particle size range within a third particle size threshold range, and an oxidant and a dispersant are added, the pH value is adjusted to a target pH threshold range, and the polishing pressure is within a preset polishing pressure threshold range.

[0019] In an optional embodiment, after being removed from the polishing carrier, the cadmium zinc telluride substrate is cleaned to obtain a processed cadmium zinc telluride substrate, comprising:

[0020] After being removed from the polishing carrier, the first surface of the CdZnTe substrate is cleaned with petroleum ether, the second surface of the CdZnTe substrate is cleaned with petroleum ether, acetone and anhydrous ethanol in sequence, and the substrate surface is dried with dry nitrogen to obtain a processed CdZnTe substrate.

[0021] The present application provides a large-size CdZnTe substrate surface processing method, comprising: first, obtaining a cut CdZnTe wafer, placing the CdZnTe wafer on a polishing carrier with a first surface facing upward, and polishing the first surface until the cutting undulations on the surface of the first surface are removed to obtain a first wafer; then, removing the first wafer from the polishing carrier with a second surface facing upward, placing the first wafer on a thinning carrier, thinning the second surface, and then mechanically polishing the second surface of the CdZnTe wafer to obtain a second wafer, wherein the thickness of the second wafer meets a preset thickness condition, and the flatness of the second wafer meets a preset flatness; The method comprises the following steps: first, removing the second wafer from the thinned carrier, performing an X-ray diffraction morphology test, obtaining an X-ray diffraction morphology image corresponding to the second wafer, selecting an area with uniform contrast on the X-ray diffraction morphology image, and marking the corresponding position of the second wafer; secondly, cutting the second wafer into cadmium zinc telluride substrates of regular shapes according to the marks at the corresponding positions of the second wafer; finally, placing the cadmium zinc telluride substrate on a polishing carrier for substrate polishing, coating the cadmium zinc telluride substrate after polishing with glue for protection, removing the cadmium zinc telluride substrate from the polishing carrier, and cleaning the cadmium zinc telluride substrate to obtain a processed cadmium zinc telluride substrate.

[0022] The large-size CdZnTe substrate surface processing method provided in the embodiment of the present application has the following beneficial effects: (1) It is suitable for processing large-size wafers and substrates with high processing efficiency; (2) It is suitable for processing irregular-shaped wafers; (3) After processing, the substrate has good surface flatness while maintaining the original roughness and original surface quality; (4) The processing debris rate is low.

[0023] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, which can be implemented in accordance with the contents of the specification, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0025] Figure 1 A schematic flow chart of a large-size cadmium zinc telluride substrate surface processing method provided in an embodiment of the present application;

[0026] Figure 2 A block diagram of a large-size CdZnTe substrate surface processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0028] During the high-speed cutting process of CdZnTe crystals, the cut wafers will be damaged or cracked. The main purpose of subsequent processing is to remove these damages and cracks. However, as the size of the substrate increases, the processing of large-sized CdZnTe substrates takes a long time. In addition, during the processing, due to the increase in grinding pressure, large abrasive particles are prone to cause cracks and cleavage in some areas of the wafer surface under high pressure, resulting in substrate loss.

[0029] In addition, if the cutting damage is removed only by polishing with a smaller abrasive, not only will the processing time be very long, but the wear of the polishing pad will also increase. Because the polishing pad for double-sided polishing is a soft polishing pad, the deformation of the polishing pad during polishing is not friendly to the surface flatness of the wafer after polishing, and after double-sided grinding, the amount of removal required in the double-sided polishing step is large (generally greater than 30μm), which further deteriorates the surface flatness of the wafer and cannot meet subsequent use requirements.

[0030] In order to overcome the above problems, the embodiments of the present application provide a large-size CdZnTe substrate processing method with high efficiency, low fragmentation rate and good flatness when processing substrates with a substrate size of 50 mm×50 mm or more.

[0031] See also Figure 1 , Figure 1 A schematic diagram of a process for processing a large-size CdZnTe substrate surface provided in an embodiment of the present application. Figure 1 As shown, the specific steps include the following steps.

[0032] Step S102: obtaining a CdZnTe wafer that has been cut, placing the CdZnTe wafer on a polishing carrier with the first surface facing upward, and performing polishing on the first surface until the cutting undulations on the surface of the first surface are removed, thereby obtaining a first wafer.

[0033] Step S104: With the second surface facing upward, the first wafer is removed from the polishing carrier, and placed on a thinning carrier, the second surface is thinned, and the second surface of the cadmium zinc telluride wafer is mechanically polished to obtain a second wafer, wherein the thickness of the second wafer meets a preset thickness condition, and the flatness of the second wafer meets a preset flatness condition.

[0034] Step S106: remove the second wafer from the thinned carrier, perform an X-ray diffraction profile test, obtain an X-ray diffraction topography image corresponding to the second wafer, select an area with uniform contrast on the X-ray diffraction topography image, and mark the corresponding position of the second wafer.

[0035] Step S108: according to the marks at corresponding positions of the second wafer, the second wafer is cut into CdZnTe substrates of regular shapes.

[0036] Step S110: placing the CdZnTe substrate on a polishing carrier to perform substrate polishing treatment, coating the polished CdZnTe substrate with glue for protection, and after removing the CdZnTe substrate from the polishing carrier, cleaning the CdZnTe substrate to obtain a processed CdZnTe substrate.

[0037] In the embodiment of the present application, the step of placing the cadmium zinc telluride wafer on a polishing carrier and polishing the first surface until the cutting undulations on the surface of the first surface are removed to obtain a first wafer includes:

[0038] The cadmium zinc telluride wafer is attached to a polishing carrier using adhesive wax, and the first surface is polished using a first polishing liquid until the cutting undulations on the surface of the first surface are removed to obtain a first wafer, wherein the first polishing liquid is a diamond polishing liquid with a particle size range within a first particle size threshold range.

[0039] In the embodiment of the present application, the second surface is thinned, and the second surface of the cadmium zinc telluride wafer is mechanically polished to obtain the second wafer, including:

[0040] The second surface is thinned by using a grinding wheel thinning machine, and the second surface of the cadmium zinc telluride wafer is mechanically polished by using a first polishing liquid to obtain a second wafer, wherein the first polishing liquid is a diamond polishing liquid having a particle size range within a first particle size threshold range.

[0041] In an embodiment of the present application, placing the cadmium zinc telluride substrate on a polishing carrier for substrate polishing includes:

[0042] Placing the cadmium zinc telluride substrate on a polishing carrier, and performing mechanical polishing using a second polishing liquid to obtain a first cadmium zinc telluride substrate, wherein the second polishing liquid is a diamond polishing liquid having a particle size range within a second particle size threshold range;

[0043] The first cadmium zinc telluride substrate is chemically mechanically polished using a third polishing liquid to obtain a second cadmium zinc telluride substrate, wherein the third polishing liquid is a silica sol polishing liquid with a particle size range within a third particle size threshold range, and an oxidant and a dispersant are added, the pH value is adjusted to a target pH threshold range, and the polishing pressure is within a preset polishing pressure threshold range.

[0044] In an embodiment of the present application, after being removed from the polishing carrier, the cadmium zinc telluride substrate is cleaned to obtain a processed cadmium zinc telluride substrate, comprising:

[0045] After being removed from the polishing carrier, the first surface of the CdZnTe substrate is cleaned with petroleum ether, the second surface of the CdZnTe substrate is cleaned with petroleum ether, acetone and anhydrous ethanol in sequence, and the substrate surface is dried with dry nitrogen to obtain a processed CdZnTe substrate.

[0046] The present application embodiment proposes a processing method for a large-size CdZnTe substrate, including A-side polishing, B-side thinning, X-ray diffraction morphology testing, slicing, substrate polishing, slicing and cleaning, see Figure 2 , Figure 2 A block diagram of a large-size CdZnTe substrate surface processing method provided in an embodiment of the present application.

[0047] Compared with the conventional method of double-sided grinding - double-sided polishing - X-ray diffraction morphology test - slicing - substrate polishing - chip removal - cleaning, the embodiment of the present application abandons the steps of double-sided grinding and double-sided polishing, and uses grinding wheel thinning and single-sided polishing instead. Grinding wheel thinning is a method of using fixed abrasives to achieve material removal. Compared with grinding with free abrasives, it can avoid the problem of a sharp increase in pressure in the local area of ​​the wafer due to abrasive agglomeration, which leads to cracks or even splits in the wafer; due to the growth of cadmium zinc telluride crystals, the single wafer formed is an irregular wafer. During double-sided grinding and double-sided polishing, the wafer will collide with the edge of the cruise ship hole many times, which is very easy to cause edge collapse. When the stress is too large, it can directly cause wafer cleavage. The use of grinding wheel thinning and single-sided polishing processes can avoid the above problems when the wafer is removed from the surface. In addition, due to the increase in wafer size, the number of wafers processed in a single double-sided grinding and double-sided polishing is reduced, and the processing efficiency of the grinding wheel thinning processing method is comparable to that of the single-sided polishing method. Finally, the use of these two processes can avoid the degradation of wafer surface flatness caused by double-sided polishing.

[0048] Specifically, in the embodiment of the present application, the implementation of polishing the A surface includes: taking <111> or <211> The CdZnTe wafer that has been cut in the crystal direction is pasted on the polishing carrier with wafer sticking wax on its A surface for A surface polishing. The polishing liquid uses a diamond polishing liquid with a particle size of (0.25-5) μm. The polishing is carried out until the cutting undulations are completely removed to obtain a flat and bright surface.

[0049] The B-side thinning is achieved by removing the wafer with the A-side polished from the polishing carrier, bonding the B-side to the thinning carrier with wafer adhesive wax, and thinning the B-side of the wafer with a grinding wheel thinner to a target thickness of 40 to 80 μm higher than the target thickness of the final substrate. The flatness of the thinned carrier must be better than 5 μm.

[0050] If cracking occurs during the thinning process, the cracking phenomenon can be improved by increasing the thickness of the carrier.

[0051] After the grinding wheel thinning is completed, mechanical polishing is performed. The polishing liquid uses a diamond polishing liquid with a particle size of (0.25-5) μm. The target thickness after thinning is 30-70 μm higher than the target thickness of the final substrate, and polishing is performed until a flat and bright surface is obtained.

[0052] The implementation of the X-ray diffraction morphology test includes: removing the CdZnTe wafer that has completed B-side thinning from the thinning carrier, performing an X-ray diffraction morphology test, obtaining an X-ray diffraction morphology image of the entire wafer, selecting an area with uniform contrast and marking the corresponding position on the wafer.

[0053] The implementation of scribing includes: scribing the CdZnTe wafer into CdZnTe substrates of regular shapes according to the marks on the wafer.

[0054] The realization of substrate polishing includes: sticking the diced CdZnTe substrate on the polishing carrier with wax, first mechanical polishing, using diamond polishing liquid with a particle size of no more than 3μm, and the polishing thickness target is 10μm higher than the target thickness of the final substrate. Then chemical mechanical polishing is performed, with the thickness target of the final substrate as the polishing thickness target, the polishing liquid is prepared with silica sol polishing liquid with a particle size of 50-120nm, adding oxidant and dispersant and adjusting the pH value to 4-5, and the polishing pressure is 70g / cm 2 ~130g / cm 2 set up.

[0055] The process of taking out and cleaning the substrate includes: applying glue to protect the polished substrate, removing the substrate from the polishing carrier, cleaning the A side of the substrate with petroleum ether, cleaning the B side of the substrate with petroleum ether, acetone and anhydrous ethanol, and blowing the substrate surface dry with dry nitrogen.

[0056] Compared with the conventional method of chamfering - double-sided grinding - double-sided polishing - X-ray diffraction morphology test - slicing - substrate polishing - wafer removal and cleaning, the results of processing five 80mm×80mm substrates are compared, as shown in the following table:

[0057] Table 1 Related test results after two processing methods

[0058] Conventional methods Method of the present invention Fragmentation rate 40％ 0％ Processing efficiency 1 tablet / day About 1.3 tablets / day Average roughness 0.33nm~0.56nm 0.31nm~0.51nm Surface flatness 3.58μm~6.24μm 1.96μm~3.87μm Double crystal diffraction half peak width 12~18arcsec 10~17arcsec

[0059] The method of the present invention has a significantly lower fragmentation rate than conventional methods when the substrate surface quality is equivalent (that is, the average roughness of the substrate surface and the half-peak width of the double crystal diffraction are equivalent), and the processing efficiency and the flatness of the substrate surface after processing are greatly improved.

[0060] In addition, the present application also provides two embodiments.

[0061] Embodiment 1: Take <111> The cadmium zinc telluride wafer that has been cut in a crystal orientation direction can be cut into an 80mm×80mm cadmium zinc telluride substrate with a thickness of 1500μm to 1650μm, and the final processing target thickness is 900μm to 1250μm. The processing is carried out according to the above steps (1) to (6). The large-size substrate processed by this method has good surface flatness and roughness. The surface flatness of the substrate tested by an optical profilometer is 1.9μm. Three points on the substrate surface are randomly selected for roughness testing using a white light interferometer, and the results are 0.33nm, 0.38nm, and 0.38nm respectively.

[0062] Embodiment 2: Take <211> The cadmium zinc telluride wafer that has been cut in a crystal orientation direction can be cut into a 60mm×60mm cadmium zinc telluride substrate with a thickness of 1300μm to 1400μm, and the final target thickness is 800μm to 1050μm. The processing is carried out according to the above steps (1) to (6). The large-sized substrate processed by this method has good surface flatness and roughness. The surface flatness of the substrate tested by an optical profilometer is 1.8μm. The roughness test was performed on three points randomly selected on the substrate surface by an optical profilometer, and the results were 0.51nm, 0.49nm, and 0.53nm respectively.

[0063] The substrates processed in the above two embodiments can both be used as epitaxial substrates. Therefore, the embodiments of the present application can be used as a method for processing large-size wafers.

[0064] The application of the embodiments of the present application can produce the following beneficial effects: (1) It is suitable for processing large-size wafers and substrates with high processing efficiency; (2) It is suitable for processing irregular-shaped wafers; (3) After processing, the substrate has good surface flatness while maintaining the original roughness and original surface quality; (4) The processing debris rate is low.

[0065] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the large-size CdZnTe substrate surface processing device, since it is basically similar to the large-size CdZnTe substrate surface processing method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the large-size CdZnTe substrate surface processing method embodiment.

[0066] It should be noted that the above is a description of a specific embodiment of the present specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the embodiments of the present specification.

[0067] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0068] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The optional embodiments do not describe all the details in detail, nor do they limit the invention to only the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of the embodiments of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of this specification, so that technicians in the relevant technical field can well understand and use this specification. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. A large-size cadmium zinc telluride substrate surface processing method, characterized in that: include: Obtaining a cadmium zinc telluride wafer that has been cut, placing the cadmium zinc telluride wafer on a polishing carrier with the first surface facing upward, and performing a polishing process on the first surface until the cutting undulations on the surface of the first surface are removed, thereby obtaining a first wafer; With the second surface facing upward, the first wafer is removed from the polishing carrier, placed on a thinning carrier, the second surface is thinned, and the second surface of the cadmium zinc telluride wafer is mechanically polished to obtain a second wafer, wherein the thickness of the second wafer meets a preset thickness condition, and the flatness of the second wafer meets a preset flatness; The second wafer is removed from the thinned carrier, and an X-ray diffraction profile test is performed to obtain an X-ray diffraction profile image corresponding to the second wafer, and an area with uniform contrast on the X-ray diffraction profile image is selected and marked at a corresponding position of the second wafer; According to the marks at corresponding positions of the second wafer, the second wafer is cut into cadmium zinc telluride substrates of regular shapes; The CdZnTe substrate is placed on a polishing carrier to perform substrate polishing treatment, the CdZnTe substrate after polishing is coated with glue for protection, and after being removed from the polishing carrier, the CdZnTe substrate is cleaned to obtain a processed CdZnTe substrate.

2. The method according to claim 1, characterized in that Placing the cadmium zinc telluride wafer on a polishing carrier and polishing the first surface until the cutting undulations on the surface of the first surface are removed to obtain a first wafer, comprising: The cadmium zinc telluride wafer is attached to a polishing carrier using adhesive wax, and the first surface is polished using a first polishing liquid until the cutting undulations on the surface of the first surface are removed to obtain a first wafer, wherein the first polishing liquid is a diamond polishing liquid with a particle size range within a first particle size threshold range.

3. The method according to claim 1, characterized in that The second surface is thinned, and the second surface of the cadmium zinc telluride wafer is mechanically polished to obtain a second wafer, comprising: The second surface is thinned by using a grinding wheel thinning machine, and the second surface of the cadmium zinc telluride wafer is mechanically polished by using a first polishing liquid to obtain a second wafer, wherein the first polishing liquid is a diamond polishing liquid having a particle size range within a first particle size threshold range.

4. The method according to claim 1, characterized in that Placing the cadmium zinc telluride substrate on a polishing carrier to perform substrate polishing treatment comprises: Placing the cadmium zinc telluride substrate on a polishing carrier, and performing mechanical polishing using a second polishing liquid to obtain a first cadmium zinc telluride substrate, wherein the second polishing liquid is a diamond polishing liquid having a particle size range within a second particle size threshold range; The first cadmium zinc telluride substrate is chemically mechanically polished using a third polishing liquid to obtain a second cadmium zinc telluride substrate, wherein the third polishing liquid is a silica sol polishing liquid with a particle size range within a third particle size threshold range, and an oxidant and a dispersant are added, the pH value is adjusted to a target pH threshold range, and the polishing pressure is within a preset polishing pressure threshold range.

5. The method according to claim 1, characterized in that After being removed from the polishing carrier, the cadmium zinc telluride substrate is cleaned to obtain a processed cadmium zinc telluride substrate, comprising: After being removed from the polishing carrier, the first surface of the CdZnTe substrate is cleaned with petroleum ether, the second surface of the CdZnTe substrate is cleaned with petroleum ether, acetone and anhydrous ethanol in sequence, and the substrate surface is dried with dry nitrogen to obtain a processed CdZnTe substrate.

Images