Chip packaging structure and electronic equipment

Abstract

The invention discloses a chip packaging structure and electronic equipment, and belongs to the technical field of semiconductors, and the chip packaging structure comprises a packaging substrate, an adapter plate and a plurality of chips. The adapter plate includes a base layer, a plurality of capacitors embedded in the base layer, and a plurality of differential signal lines. According to the technical scheme of the invention, the capacitors are directly formed on the adapter plate, and each of the pair of differential signal lines between the two chips is connected in series with one capacitor, so that the two chips can bypass the limitation of a DDR or UCIE interface to realize interconnection communication. According to the chip packaging structure and the manufacturing method thereof, a surface-mounted capacitor can be prevented from being additionally arranged in the chip packaging structure, the area of a packaging substrate can be saved, the problem that the surface-mounted technology of the surface-mounted capacitor is incompatible with the surface-mounted technology of the chip packaging structure is solved, the cost is reduced, the higher integration degree is achieved, and the yield can be improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a chip packaging structure and an electronic device. Background Art

[0002] With the development of artificial intelligence and high-performance computing, the requirements for chip computing power are getting higher and higher, and the functions of chips are becoming more and more complex. At present, the main mass production chip packaging solution in the field of AI high-computing power chips is 2.5D packaging technology. This packaging solution ensures the integration of the system, can use high-computing power chips with advanced process nodes, and solves the problem of reduced yield caused by larger chip size. Under this packaging structure, most of the communication interfaces between chips are high-density parallel signal interfaces such as DDR or UCIE.

[0003] However, due to the limitation of domestic process production capacity, the application of DDR interface is restricted, and there is no mature UCIE interface standard protocol in China. How to solve the communication interface connection problem between chips has become an urgent problem to be solved in this field. Summary of the invention

[0004] The present application proposes a chip packaging structure, including a packaging substrate, an adapter board and a plurality of chips. The adapter board is arranged on the packaging substrate and electrically connected to the packaging substrate. The plurality of chips are arranged on a side of the adapter board away from the packaging substrate. In addition, the adapter board includes a base layer, a plurality of capacitors and a plurality of differential signal lines, the base layer includes a first surface away from a side of the packaging substrate, a plurality of capacitors are embedded in the first surface, and the plurality of capacitors include a first capacitor and a second capacitor. The plurality of differential signal lines are arranged on a side of the base layer away from the packaging substrate, the plurality of differential signal lines include a first differential signal line, a second differential signal line, a third differential signal line and a fourth differential signal line, the first differential signal line is electrically connected to one electrode of the first capacitor, and the second differential signal line is electrically connected to another electrode of the first capacitor. The third differential signal line is electrically connected to one electrode of the second capacitor, and the fourth differential signal line is electrically connected to another electrode of the second capacitor. The multiple chips include a first chip and a second chip, the first chip has a first interface, the second chip has a second interface, the first interface is electrically connected to the first differential signal line and the third differential signal line, and the second interface is electrically connected to the second differential signal line and the fourth differential signal line.

[0005] In some embodiments, the first chip and the second chip are arranged at intervals along a first direction, the first direction is parallel to the first surface, and in the first direction, at least part of the first capacitor is located between the first chip and the second chip, and at least part of the second capacitor is located between the first chip and the second chip.

[0006] In some embodiments, the adapter board further includes an insulating layer and a plurality of conductive structures, the insulating layer is disposed between the base layer and the plurality of differential signal lines, and the plurality of conductive structures penetrate the insulating layer. The plurality of conductive structures include a first conductive structure, a second conductive structure, a third conductive structure, and a fourth conductive structure, the first differential signal line is electrically connected to one electrode of the first capacitor through the first conductive structure, the second differential signal line is electrically connected to another electrode of the first capacitor through the second conductive structure. The third differential signal line is electrically connected to one electrode of the second capacitor through the third conductive structure, and the fourth differential signal line is electrically connected to another electrode of the second capacitor through the fourth conductive structure.

[0007] In some embodiments, the plurality of capacitors further include a third capacitor and a fourth capacitor, and the plurality of differential signal lines further include a fifth differential signal line, a sixth differential signal line, a seventh differential signal line, and an eighth differential signal line. The fifth differential signal line is electrically connected to one electrode of the third capacitor, and the sixth differential signal line is electrically connected to another electrode of the third capacitor. The seventh differential signal line is electrically connected to one electrode of the fourth capacitor, and the eighth differential signal line is electrically connected to another electrode of the fourth capacitor. The second chip further has a third interface, the plurality of chips include a third chip, the third chip has a fourth interface, the third interface is electrically connected to the fifth differential signal line and the seventh differential signal line, and the fourth interface is electrically connected to the sixth differential signal line and the eighth differential signal line.

[0008] In some embodiments, the second chip and the third chip are arranged at intervals along a first direction, the first direction is parallel to the first surface, and in the first direction, at least part of the third capacitor is located between the second chip and the third chip, and at least part of the fourth capacitor is located between the second chip and the third chip.

[0009] In some embodiments, a first surface of the base layer is provided with a plurality of grooves, and the plurality of grooves extend from the first surface into the base layer. Each capacitor includes a first electrode, a dielectric layer, and a second electrode, and the first electrode and the second electrode extend from the first surface into the plurality of grooves, respectively, and the dielectric layer is provided between the first electrode and the second electrode.

[0010] In some embodiments, the first interface and the second interface are both PCIE interfaces.

[0011] On the other hand, the present application also provides an electronic device, comprising the chip packaging structure and a circuit board in any one of the above embodiments, wherein the chip packaging structure is electrically connected to the circuit board.

[0012] In the embodiment provided in the present application, the communication channel between the first chip and the second chip of the chip packaging structure includes a pair of differential signal lines, wherein one differential signal line includes a first differential signal line and a second differential signal line, and the other differential signal line includes a third differential signal line and a fourth differential signal line. In addition, the adapter board of the chip packaging structure also includes a plurality of capacitors embedded in the adapter board, the first differential signal line is electrically connected to one electrode of the first capacitor, the second differential signal line is electrically connected to another electrode of the first capacitor, the third differential signal line is electrically connected to one electrode of the second capacitor, and the fourth differential signal line is electrically connected to another electrode of the second capacitor, thereby realizing that each differential signal line in a pair of differential signal lines is connected in series with a capacitor. Based on this, the first interface of the first chip and the second interface of the second chip can bypass the limitations of the DDR or UCIE interface, for example, a PCIE interface can be used to achieve interconnection communication between the two chips, and the capacitors connected to a pair of differential signal lines between the two chips are capacitors directly formed in the adapter board, avoiding the additional configuration of surface mount capacitors in the chip packaging structure, which is beneficial to saving the area of ​​the packaging substrate, and also avoiding the problem of incompatibility between the mounting process of the surface mount capacitor and the mounting process of the chip packaging structure, reducing costs and achieving higher integration, which is beneficial to improving the yield rate.

[0013] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0015] Figure 1 A schematic cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0016] Figure 2 for Figure 1 A top view of a chip packaging structure provided by the illustrated embodiment;

[0017] Figure 3 for Figure 1 A partial enlarged view of the chip packaging structure provided by the embodiment shown at position A;

[0018] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0020] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0021] In the description of the present application, “plurality” means two or more.

[0022] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0023] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0024] At present, chip-on-wafer-on-substrate (CoWoS) technology is a more common 2.5D packaging solution for high-computing power chips in the world. Under this packaging structure, most of the communication interfaces between chips are high-density parallel signal interfaces such as DDR or UCIE.

[0025] However, due to the limitation of domestic process production capacity, the application of DDR interface is subject to certain restrictions, and there is no mature UCIE interface standard protocol in China, and the commercial UCIE interface is not mature. If these two types of interfaces are bypassed and other interfaces are used, there are other corresponding problems. For example, taking the PCIE interface as an example, according to the PCIE interconnection protocol, it is necessary to connect a DC blocking capacitor of a certain capacitance to each of the two differential signal lines of a pair of differential signal lines. However, since the current mounting process of surface mount capacitors is incompatible with the mounting process of chip packaging structure, surface mount capacitors cannot be connected and integrated on the chip packaging structure.

[0026] Based on this, the present application provides a chip packaging structure, such as Figure 1 to Figure 3 As shown, Figure 1 A schematic cross-sectional view of a chip packaging structure provided in an embodiment of the present application. Figure 2 for Figure 1 The top view of the chip packaging structure provided by the embodiment shown, Figure 3 for Figure 1 The illustrated embodiment is a partial enlarged view of the chip packaging structure at point A.

[0027] like Figure 1 As shown, the chip packaging structure 100 includes a packaging substrate 1, an adapter board 2, and a plurality of chips 3. The adapter board 2 is disposed on the packaging substrate 1 and is electrically connected to the packaging substrate 10 through C4 solder bumps. The plurality of chips 3 are disposed on a side of the adapter board 2 away from the packaging substrate 1.

[0028] like Figure 2 and Figure 3 As shown, the adapter board 2 includes a base layer 20, a plurality of capacitors 21 and a plurality of differential signal lines 22. The base layer 20 includes a first surface P1 away from the package substrate 1. The plurality of capacitors 21 are embedded in the first surface P1. The plurality of capacitors 21 include a first capacitor 211 and a second capacitor 212. The plurality of differential signal lines 22 are arranged on the side of the base layer 20 away from the package substrate 1. The plurality of differential signal lines 22 include a first differential signal line 221, a second differential signal line 222, a third differential signal line 223 and a fourth differential signal line 224. The first differential signal line 221 is electrically connected to one electrode of the first capacitor 211, and the second differential signal line 222 is electrically connected to the other electrode of the first capacitor 211. The third differential signal line 223 is electrically connected to one electrode of the second capacitor 212, and the fourth differential signal line 224 is electrically connected to the other electrode of the second capacitor 212.

[0029] like Figure 1 and 2As shown, the multiple chips 3 include a first chip 31 and a second chip 32, the first chip 31 has a first interface 311, the second chip 32 has a second interface 321, the first interface 311 is electrically connected to the first differential signal line 221 and the third differential signal line 223, and the second interface 321 is electrically connected to the second differential signal line 222 and the fourth differential signal line 224.

[0030] In an embodiment of the present application, a plurality of capacitors 21 are directly formed on the adapter board 2, that is, the type of the plurality of capacitors 21 is a deep groove capacitor. Between the two chips of the chip packaging structure 100, taking the first chip 31 and the second chip 32 as an example, the communication channel between the two chips includes a pair of differential signal lines, which can be recorded as a differential signal line L1 and a differential signal line L2. One of the differential signal lines L1 includes a first differential signal line 221 and a second differential signal line 222, which are respectively electrically connected to the two electrodes of the first capacitor 211, thereby connecting the first capacitor 211 in series to the differential signal line L1. Another differential signal line L2 includes a third differential signal line 223 and a fourth differential signal line 224, which are respectively electrically connected to the two electrodes of the second capacitor 212, thereby connecting the second capacitor 212 in series to the differential signal line L2.

[0031] Based on this, a capacitor is connected in series to each differential signal line of a pair of differential signal lines between the first chip 31 and the second chip 32 to block DC signals. Accordingly, the first interface 311 and the second interface 321 can bypass the limitations of the DDR or UCIE interface. For example, the first interface 311 and the second interface 321 can adopt a PCIE interface and use the PCIE communication protocol to achieve communication interconnection between the two chips.

[0032] Furthermore, since the capacitors 21 connected in series on a pair of differential signal lines between the two chips are deep-groove capacitors formed directly on the adapter board 2, it is avoided to configure additional surface-mount capacitors (such as multilayer ceramic capacitors) in the chip packaging structure 100, which is beneficial to saving the area of ​​the packaging substrate 1 and avoiding the problem of incompatibility between the mounting process of the surface-mount capacitors and the mounting process of the chip packaging structure 100, thereby reducing costs and achieving higher integration, which is beneficial to improving the yield rate.

[0033] Since the capacitor 21 is directly formed on the adapter board 2 , the capacitance value of the capacitor 21 can be precisely designed according to needs, thus avoiding the limitation of the fixed capacitance value of the surface mounted capacitor.

[0034] In addition, in the embodiment of the present application, the capacitor 21 is directly formed on the adapter board 2, and the parasitic resistance and parasitic inductance of the capacitor 21 are lower. Combined with the relevant provisions of the communication protocol, the capacitor 21 in the embodiment of the present application can achieve the communication effect specified by the protocol with a lower capacitance value, and thus can further reduce the occupied area of ​​the capacitor 21 on the adapter board 2, which is conducive to further reducing the size of the chip packaging structure 100 and further improving the integration.

[0035] In some embodiments, Figure 3 As shown, the first chip 31 and the second chip 32 are arranged at intervals along a first direction (X-axis direction), and the first direction (X-axis direction) is parallel to the first surface P1. In the first direction, at least a portion of the first capacitor 211 is located between the first chip 31 and the second chip 32, and at least a portion of the second capacitor 212 is located between the first chip 31 and the second chip 32.

[0036] Compared with the connection scheme using surface-mounted capacitors in the related art, the capacitor 21 in the embodiment of the present application is directly formed on the adapter board 2. Based on this, the distribution position of the capacitor 21 is more flexible. By locating at least part of the first capacitor 211 between the first chip 31 and the second chip 32, it is more conducive to the connection of the differential signal line 22, which is conducive to reducing the length of the differential signal line 22 and reducing the signal transmission time. In addition, since the distribution position of the capacitor 21 is more flexible, the area of ​​the adapter board 2 can be fully utilized, which is conducive to optimizing the size of the adapter board 2.

[0037] In some embodiments, Figure 3 As shown, the adapter board 2 also includes an insulating layer 23 and a plurality of conductive structures 24, the insulating layer 23 is disposed between the base layer 20 and the plurality of differential signal lines 22, and the plurality of conductive structures 24 penetrate the insulating layer 23. The plurality of conductive structures 24 include a first conductive structure 241, a second conductive structure 242, a third conductive structure 243, and a fourth conductive structure 244, the first differential signal 221 line is electrically connected to one electrode of the first capacitor 211 through the first conductive structure 241, and the second differential signal line 222 is electrically connected to the other electrode of the first capacitor 211 through the second conductive structure 242. Similarly, the third differential signal 223 line is electrically connected to one electrode of the second capacitor 212 through the third conductive structure 243, and the fourth differential signal 224 line is electrically connected to the other electrode of the second capacitor 212 through the fourth conductive structure 244.

[0038] The above-mentioned multiple conductive structures 24 are used to realize the electrical connection between multiple differential signal lines 22 and corresponding capacitors 21, and when the capacitor 21 is embedded in the adapter board 2, it is beneficial to the layered arrangement of the electrodes of the capacitor 21 and the differential signal lines 22 on the adapter board 2, and it is beneficial to optimize the routing design of the multiple differential signal lines 22 on the adapter board 2, which is beneficial to reduce the area of ​​the adapter board 2 and improve the packaging integration.

[0039] In some embodiments, Figure 2 As shown, the plurality of capacitors 21 further include a third capacitor 213 and a fourth capacitor 214, and the plurality of differential signal lines 22 further include a fifth differential signal line 225, a sixth differential signal line 226, a seventh differential signal line 227, and an eighth differential signal line 228. The fifth differential signal line 225 is electrically connected to one electrode of the third capacitor 213, and the sixth differential signal line 226 is electrically connected to the other electrode of the third capacitor 213. The seventh differential signal line 227 is electrically connected to one electrode of the fourth capacitor 214, and the eighth differential signal line 228 is electrically connected to the other electrode of the fourth capacitor 214. The second chip 32 further has a third interface 322, and the plurality of chips 3 include a third chip 33, and the third chip 33 has a fourth interface 331, and the third interface 322 is electrically connected to the fifth differential signal line 225 and the seventh differential signal line 227, and the fourth interface 331 is electrically connected to the sixth differential signal line 226 and the eighth differential signal line 228.

[0040] In the embodiment of the present application, each chip may include multiple interfaces, for example, the second chip 32 includes a second interface 321 and a third interface 322. Similar to the communication interconnection between the first interface 311 of the first chip 31 and the second interface 321 of the second chip 32, the communication channel between the third interface 322 and the fourth interface 331 also includes a pair of differential signal lines, which can be recorded as differential signal lines L3 and differential signal lines L4. The differential signal line L3 includes a fifth differential signal line 225 and a sixth differential signal line 226, which are respectively electrically connected to the two electrodes of the third capacitor 213, so that the third capacitor 213 is connected in series to the differential signal line L3. Another differential signal line L4 includes a seventh differential signal line 227 and an eighth differential signal line 228, which are respectively electrically connected to the two electrodes of the fourth capacitor 214, so that the fourth capacitor 214 is connected in series to the differential signal line L4.

[0041] Based on this, a capacitor is connected to each differential signal line of a pair of differential signal lines between the second chip 32 and the third chip 33 to block DC signals. The corresponding third interface 322 and fourth interface 331 can also bypass the limitations of the DDR or UCIE interface, for example, using the PCIE interface and the PCIE communication protocol to achieve communication interconnection between the two chips.

[0042] In some embodiments, Figure 2 As shown, the second chip 32 and the third chip 33 are arranged in a spaced relationship along a first direction, where the first direction may be as follows: Figure 2 The X-axis direction shown may also be the Y-axis direction, or other directions parallel to the XY plane, and may be reasonably designed according to the chip packaging requirements. In the first direction, at least a portion of the third capacitor 213 is located between the second chip 32 and the third chip 33, and at least a portion of the fourth capacitor 214 is located between the second chip 32 and the third chip 33.

[0043] By properly arranging the positions of the third capacitor 213 and the fourth capacitor 214 , it is more advantageous to connect the differential signal line 22 , reduce the length of the differential signal line 22 , reduce the signal transmission time, and optimize the size of the adapter board 2 .

[0044] In some embodiments, Figure 3 As shown, a first surface P1 of the base layer 20 is provided with a plurality of grooves T1, and the plurality of grooves T1 extend from the first surface P1 into the base layer 20. Each capacitor 21 includes a first electrode D1, a dielectric layer D3 and a second electrode D2. The first electrode D1 and the second electrode D2 extend from the first surface P1 into the plurality of grooves T1, respectively, and the dielectric layer D3 is provided between the first electrode D1 and the second electrode D2.

[0045] For example, Figure 3 As shown, taking the first capacitor 211 as an example, each capacitor includes a plurality of grooves, and in each groove, the first electrode D1, the dielectric layer D3 and the second electrode D2 can form an interlaced multilayer structure, based on which, it is beneficial to realize the design of different capacitance values, meet the communication requirements between chips, and is beneficial to reduce the area occupied by the capacitor 21 on the adapter board 2, thereby reducing the size of the chip packaging structure 100, reducing costs and improving integration.

[0046] In some embodiments, the first interface 311 and the second interface 321 are both PCIE interfaces. Since the adapter board 2 is integrated with a deep groove capacitor, the solution of connecting the capacitor 21 in series to the differential signal line is relatively simple to operate. Based on this, it is possible to use the PCIE communication protocol to achieve communication interconnection between two chips. In addition, the PCIE interface technology is relatively mature, which is conducive to breaking technical limitations and improving the interconnection performance between chips.

[0047] In a second aspect, the present application also provides an electronic device 200, such as Figure 4 As shown, Figure 4 An electronic device provided in an embodiment of the present application includes the electronic device 200 including the chip packaging structure 100 mentioned above and a circuit board 201 , wherein the chip packaging structure 200 is electrically connected to the circuit board 201 .

[0048] In the chip packaging structure 100 in the electronic device 200, the capacitor 21 is connected in series to the differential signal line. Based on this, the interconnection communication between the two chips can bypass the limitations of the DDR or UCIE interface, for example, it can be implemented using a PCIE interface, etc., and the capacitor connected to a pair of differential signal lines between the two chips is a deep groove capacitor embedded in the adapter board, which avoids the additional configuration of surface mount capacitors in the chip packaging structure 100, is beneficial to saving the area of ​​the packaging substrate 1, and also avoids the problem of incompatibility between the mounting process of the surface mount capacitor and the mounting process of the chip packaging structure, reduces costs and achieves a higher degree of integration, which is beneficial to improving the yield rate.

[0049] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that: include: Package substrate; An adapter plate, disposed on the packaging substrate and electrically connected to the packaging substrate; A plurality of chips are arranged on a side of the adapter board away from the packaging substrate; The adapter board includes a base layer, a plurality of capacitors and a plurality of differential signal lines, the base layer includes a first surface away from a side of the packaging substrate, the plurality of capacitors are embedded in the first surface, and the plurality of capacitors include a first capacitor and a second capacitor; The plurality of differential signal lines are arranged on a side of the base layer away from the packaging substrate, the plurality of differential signal lines include a first differential signal line, a second differential signal line, a third differential signal line and a fourth differential signal line, the first differential signal line is electrically connected to one electrode of the first capacitor, the second differential signal line is electrically connected to the other electrode of the first capacitor; the third differential signal line is electrically connected to one electrode of the second capacitor, and the fourth differential signal line is electrically connected to the other electrode of the second capacitor; The multiple chips include a first chip and a second chip, the first chip has a first interface, and the second chip has a second interface; the first interface is electrically connected to the first differential signal line and the third differential signal line, and the second interface is electrically connected to the second differential signal line and the fourth differential signal line.

2. The chip packaging structure according to claim 1, characterized in that: The first chip and the second chip are arranged at intervals along a first direction, and the first direction is parallel to the first surface; In the first direction, at least a portion of the first capacitor is located between the first chip and the second chip, and at least a portion of the second capacitor is located between the first chip and the second chip.

3. The chip packaging structure according to claim 1, characterized in that: The adapter board further includes an insulating layer and a plurality of conductive structures, wherein the insulating layer is disposed between the base layer and the plurality of differential signal lines, and the plurality of conductive structures penetrate the insulating layer; The plurality of conductive structures include a first conductive structure, a second conductive structure, a third conductive structure, and a fourth conductive structure, the first differential signal line is electrically connected to one electrode of the first capacitor through the first conductive structure, and the second differential signal line is electrically connected to the other electrode of the first capacitor through the second conductive structure; The third differential signal line is electrically connected to one electrode of the second capacitor through the third conductive structure, and the fourth differential signal line is electrically connected to the other electrode of the second capacitor through the fourth conductive structure.

4. The chip packaging structure according to claim 1, characterized in that: The plurality of capacitors further includes a third capacitor and a fourth capacitor; The plurality of differential signal lines further include a fifth differential signal line, a sixth differential signal line, a seventh differential signal line and an eighth differential signal line, the fifth differential signal line is electrically connected to one electrode of the third capacitor, the sixth differential signal line is electrically connected to the other electrode of the third capacitor; the seventh differential signal line is electrically connected to one electrode of the fourth capacitor, and the eighth differential signal line is electrically connected to the other electrode of the fourth capacitor; The second chip also has a third interface, the multiple chips include a third chip, and the third chip has a fourth interface; the third interface is electrically connected to the fifth differential signal line and the seventh differential signal line, and the fourth interface is electrically connected to the sixth differential signal line and the eighth differential signal line.

5. The chip packaging structure according to claim 4, characterized in that: The second chip and the third chip are arranged at intervals along a first direction, and the first direction is parallel to the first surface; In the first direction, at least a portion of the third capacitor is located between the second chip and the third chip, and at least a portion of the fourth capacitor is located between the second chip and the third chip.

6. The chip packaging structure according to claim 1, characterized in that: A first surface of the base layer is provided with a plurality of grooves, and the plurality of grooves extend from the first surface into the base layer; Each of the capacitors includes a first electrode, a dielectric layer, and a second electrode. The first electrode and the second electrode extend from the first surface to the plurality of grooves respectively, and the dielectric layer is disposed between the first electrode and the second electrode.

7. The chip packaging structure according to claim 1, characterized in that: The first interface and the second interface are both PCIE interfaces.

8. An electronic device, characterized in that: include: The chip packaging structure according to any one of claims 1 to 7; A circuit board, the chip packaging structure is electrically connected to the circuit board.

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