Chip packaging structure and electronic equipment
By setting the first chip on the front of the adapter plate and the second chip on the back of the adapter plate in the chip package structure, making full use of the space of the adapter plate, the system risks and low yields caused by the increase in the size of the package structure are solved, and a higher system unit area integration and better welding reliability are achieved.
Patent Information
- Application Number
- CN202411656895.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-03-11
AI Technical Summary
As computing power requirements increase, the core particle size increases, and the packaging structure size also increases, resulting in increased system risks, serious problems with warping and welding reliability, and low yield rate.
A chip packaging structure is proposed. By setting the first chip on the front side of the adapter board and the second chip on the back side of the adapter board, the space of the adapter board is fully utilized, and the area of the adapter board is reduced, thereby reducing the size of the chip packaging structure and improving the integration of the unit area of the system.
It effectively reduces the area of the adapter plate, improves the integration of the system per unit area, improves the warping and welding reliability issues, and improves the yield rate.
Smart Images
Figure CN119601544A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a chip packaging structure. Background Art
[0002] At present, the development of integrated circuit technology is facing key challenges such as performance improvement bottlenecks and power consumption management. As Moore's Law slows down, it is difficult for a single complex chip to continuously improve performance. At the same time, the demand for heterogeneous system integration is increasing, and traditional integration methods are difficult to meet. Against this background, chiplet technology came into being and became an important direction for the next generation of integrated circuit technology. Chiplet technology splits a single complex chip into multiple functional modules and integrates these modules together using advanced 2.5D / 3D packaging technology.
[0003] However, as computing power requirements become higher and higher, the size of the core particles becomes larger and larger, and the number increases, the size of the packaging structure also increases. This will increase system risks, cause warping problems in the packaging structure, and cause problems with welding reliability, resulting in a low yield rate.
[0004] Based on this, how to improve system integration and increase yield rate has become an urgent problem to be solved in this field. Summary of the invention
[0005] The present application proposes a chip packaging structure, including a packaging substrate, an adapter board and a plurality of chips. The adapter board is arranged on the packaging substrate and electrically connected to the packaging substrate, and the plurality of chips include at least one first chip and at least one second chip. The first chip is arranged on a side of the adapter board away from the packaging substrate, and the first chip is electrically connected to the adapter board, and the second chip is arranged between the adapter board and the packaging substrate, and the second chip is electrically connected to the adapter board.
[0006] In some embodiments, an orthographic projection of at least one first chip on the packaging substrate overlaps with an orthographic projection of at least one second chip on the packaging substrate.
[0007] In some embodiments, an area of an orthographic projection of the at least one second chip on the packaging substrate is smaller than an area of an orthographic projection of the at least one first chip on the packaging substrate.
[0008] In some embodiments, at least one first chip is a computing chip, and the multiple chips include multiple second chips. Among the multiple second chips, at least one second chip is a control chip, and at least one second chip is a storage chip.
[0009] In some embodiments, the area of the orthographic projection of the adapter plate on the package substrate is 2160 mm 2 , where the number of computing chips is four, the number of control chips is one, and the number of storage chips is eight.
[0010] In some embodiments, the above-mentioned multiple chips include multiple first chips, among which at least one first chip is a computing chip, at least one first chip is a storage chip, and at least one second chip is a control chip.
[0011] In some embodiments, the area of the orthographic projection of the adapter plate on the package substrate is 2916 mm 2 , where the number of computing chips is four, the number of control chips is one, and the number of storage chips is twelve.
[0012] In some embodiments, the adapter plate includes one of a silicon adapter plate, an organic adapter plate, and a glass adapter plate.
[0013] On the other hand, the present application also provides an electronic device, comprising the chip packaging structure and a circuit board in any one of the above embodiments, wherein the chip packaging structure is electrically connected to the circuit board.
[0014] In the chip packaging structure provided in the present application, at least one first chip is arranged on a side of the adapter board away from the packaging substrate, and at least one second chip is arranged between the adapter board and the packaging substrate. In other words, the first chip is arranged on the front of the adapter board, and the second chip is arranged on the back of the adapter board. Compared with the related art, under the same integration level (that is, the number of integrated chips in the chip packaging structure is the same), the embodiment of the present application can make full use of the space on the front and back of the adapter board, which is conducive to reducing the area of the adapter board, thereby reducing the size of the chip packaging structure, improving the integration level per unit area of the system, improving the warping problem and the welding reliability problem, and improving the yield rate. Similarly, compared with the related art, under the condition that the size of the chip packaging structure is the same, the chip packaging structure provided in the embodiment of the present application can make full use of the back of the adapter board, set more chips, and thus improve the integration level per unit area of the system.
[0015] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0017] Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;
[0018] Figure 2 for Figure 1 A top view of the chip packaging structure in the illustrated embodiment;
[0019] Figure 3 for Figure 1 A bottom view of the chip packaging structure in the illustrated embodiment;
[0020] Figure 4 A schematic diagram of a chip packaging structure in a comparative embodiment;
[0021] Figure 5 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;
[0022] Figure 6 for Figure 5 A top view of the chip packaging structure in the illustrated embodiment;
[0023] Figure 7 for Figure 5 A bottom view of the chip packaging structure in the illustrated embodiment;
[0024] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0025] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0026] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.
[0027] In the description of the present application, “plurality” means two or more.
[0028] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0029] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.
[0030] At present, 2.5D packaging technology is a more common packaging technology for high-computing power chips. As the computing power requirements become higher and higher, the size of the core particles becomes larger and larger, and the size of the chip packaging structure also increases. In the chip packaging structure, the increase in the size of the adapter board will increase the system risk and cause a series of yield problems, such as the warping problem of the adapter board and the welding reliability problem. Among them, the warping problem of the adapter board refers to the fact that the larger the area of the adapter board, the more difficult it is to control the flatness, and it is easy to generate large internal stress under the high and low temperature of the process flow, resulting in the failure of the adapter board. The welding reliability problem (or the corner failure problem of the solder bump) refers to the fact that due to the mismatch of the thermal expansion coefficients of the adapter board and the packaging substrate, the corner solder joints are prone to cold soldering during the welding process, and there may also be welding reliability problems caused by the accumulation of corner stress. In addition, the process steps of large-size adapter boards are more complicated and more difficult.
[0031] In order to avoid the above problems, the present application provides a chip packaging structure, which aims to improve the system integration per unit area, reduce the area of the adapter board, and improve the yield rate of the chip packaging structure.
[0032] like Figure 1 to Figure 3 As shown, Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application is shown in FIG. Figure 2 for Figure 1 A top view of the chip packaging structure in the embodiment shown, Figure 3 for Figure 1Bottom view of the chip packaging structure in the illustrated embodiment. The chip packaging structure 100 includes a packaging substrate 10, an adapter board 11, and a plurality of chips 12. Along the Z-axis direction, the adapter board 11 is disposed on the packaging substrate 10, and the adapter board 11 and the packaging substrate 10 are electrically connected through C4 solder bumps 13. The plurality of chips 12 include at least one first chip 121 and at least one second chip 122. The first chip 121 is disposed on a side of the adapter board 11 away from the packaging substrate 10, that is, disposed on the front side P1 of the adapter board 11, and the first chip 121 and the adapter board 11 are electrically connected through micro bumps 14. The second chip 122 is disposed between the adapter board 11 and the packaging substrate 10, that is, the second chip is disposed on the back side P2 of the adapter board 11, and is electrically connected to the adapter board 11 through micro bumps 14. The chip packaging structure 100 further includes a solder ball 15 located on a side of the packaging substrate 10 away from the adapter board 11 . The solder ball 15 is used to achieve electrical connection between the chip packaging structure 100 and an external PCB board.
[0033] In the embodiment of the present application, the first chip 121 of the plurality of chips 12 is arranged above the adapter board 11, and the second chip 122 is arranged below the adapter board 11. This arrangement makes full use of the area on the upper and lower sides of the adapter board 11. A part of the metal routing on the front side P1 of the adapter board 11 is used to realize the interconnection communication between the plurality of first chips 121, a part of it is used to realize the interconnection communication between the first chip 121 and the second chip 122, and a part of it is used to realize the interconnection communication between the plurality of chips 12 and the external circuit, such as connecting the chip 12 to an external signal loop or power loop. A part of the metal routing on the back side P2 of the adapter board 11 is used to realize the interconnection communication between the plurality of second chips 122, a part of it is used to realize the interconnection communication between the first chip 121 and the second chip 122, and a part of it is used to realize the interconnection communication between the plurality of chips 12 and the external circuit, such as connecting the chip 12 to an external signal loop or power loop.
[0034] By respectively arranging multiple chips 12 on the front side P1 and the back side P2 of the adapter board 11, the area of the adapter board 11 is fully utilized. Under the same integration level, that is, when the number of integrated chips 12 in the chip packaging structure 100 is the same, the area of the adapter board 11 can be effectively reduced.
[0035] For example, Figure 4 Schematic diagram of a chip packaging structure in a comparative embodiment. In this comparative embodiment, a plurality of chips 12 of the chip packaging structure are all arranged on a side of the transfer board 11 away from the packaging substrate 10 .
[0036] The embodiments of the present application Figure 4 The difference between the comparative embodiments shown is that, at the same integration level, Figure 2-3As shown, the embodiment of the present application will Figure 4 The multiple chips 12 in the dotted box area are arranged on the back side P2 of the adapter board 11, thereby achieving the reduction of the size of the adapter board 11 in the X-axis direction. For example, the present application is not limited to the reduction of the size in the X-axis direction, and the size of the adapter board 11 can also be reduced in the Y-axis direction, or the size of the adapter board 11 along the X-axis direction and the Y-axis direction can be reduced at the same time. By reducing the area of the adapter board 11, the system integration per unit area is improved, and the warping problem caused by the large size of the adapter board 11 and the corner failure problem of the solder bump can be effectively avoided, which is conducive to improving the yield rate of the chip packaging structure.
[0037] In some embodiments, Figure 2-3 As shown, the orthographic projection of at least one first chip 121 on the package substrate 10 overlaps with the orthographic projection of at least one second chip 122 on the package substrate 10. The overlap here can be partial overlap or complete overlap. Figure 2-3 As shown, the orthographic projections of a second chip 122 (a) and a first chip 121 on the package substrate 10 are partially overlapped, and the orthographic projections of another second chip 122 (b) and the first chip 121 on the package substrate 10 are completely overlapped. The setting of overlapping orthographic projections is beneficial to improving the utilization rate of the adapter board 11 and further reducing the area of the adapter board 11 on the one hand, and is beneficial to shortening the interconnection distance between the first chip 121 and the second chip 122 on the other hand, and is beneficial to the metal routing design on the adapter board 11, so as to facilitate the interconnection communication between the first chip 121 and the second chip 122.
[0038] In some embodiments, Figure 2-3 As shown, the area of the orthographic projection of at least one second chip 122 on the package substrate 10 is smaller than the area of the orthographic projection of at least one first chip 121 on the package substrate 10. In other words, the chip 12 with a smaller area size among the multiple chips 12 of the chip package structure 100 is arranged on the back side P2 of the adapter board 11. Based on this, on the one hand, stress problems can be avoided and the preparation process can be facilitated, and on the other hand, a certain area space can be reserved on the back side P2 of the adapter board 11 for setting the C4 solder bump 13, which is conducive to realizing the electrical connection between the adapter board 11 and the package substrate 10, and is conducive to realizing the electrical connection between the multiple chips 12 and the external signal circuit or power circuit.
[0039] In some embodiments, Figure 2 As shown, at least one first chip 121 is a computing chip, and the plurality of chips 12 include a plurality of second chips 122. Figure 3As shown, at least one second chip 122 (a) is a control chip, and at least one second chip 122 (b) is a memory chip. There is usually a need for interconnection and communication between the control chip and the computing chip, and between the control chip and the memory chip. Based on this, the control chip is set on the back of the adapter board 11 and is set as centrally as possible, which is beneficial to the metal routing design of the adapter board 11 and shortens the interconnection distance. The setting of the memory chip can be comprehensively considered based on the interconnection requirements with the computing chip and the interconnection requirements with the control chip.
[0040] For example, Figure 2-3 As shown, in some embodiments, the chip packaging structure 100 includes four computing chips, one control chip and eight memory chips. For example, the size of the computing chip along the X-axis direction is 17 mm, the size of the computing chip along the Y-axis direction is 26 mm, the size of the control chip along the X-axis direction is 10 mm, the size of the control chip along the Y-axis direction is 10 mm, the size of the memory chip along the X-axis direction is 4 mm, and the size of the memory chip along the Y-axis direction is 8 mm. According to the packaging structure provided in the embodiment of the present application, the area of the orthographic projection of the adapter plate 11 on the packaging substrate 10 is 2160 mm 2 , its size along the X-axis is 40mm wide and along the Y-axis is 54mm long. At the same integration level, Figure 4 In the comparative embodiment shown, the adapter plate 11 has a width of 54 mm along the X-axis direction and a length of 54 mm along the Y-axis direction. That is, at the same integration level, the embodiment of the present application reduces the area of the adapter plate 11, improves the system integration level per unit area, is conducive to improving the warping problem and welding reliability problem, and is conducive to improving the yield rate.
[0041] In some embodiments, Figure 5 to Figure 7 As shown, Figure 5 A schematic diagram of another chip packaging structure provided in an embodiment of the present application, Figure 6 for Figure 5 A top view of the chip packaging structure in the embodiment shown, Figure 7 for Figure 5 The bottom view of the chip packaging structure in the embodiment shown. The plurality of chips 12 include a plurality of first chips 121, among which at least one first chip 121 (a) is a computing chip, and at least one first chip 121 (b) is a storage chip, and at least one second chip 122 is a control chip.
[0042] For example, Figure 5 to Figure 7 In the embodiment shown, the chip package structure 100 includes four computing chips, one control chip and twelve memory chips. Figure 4 Compared with the comparative embodiment shown in the figure, when the size of the adapter plate 11 is the same, for example Figures 4 to 7The area of the orthographic projection of the adapter plate 11 on the package substrate 10 is 2916 mm 2 , its length along the X-axis direction is 54 mm, and its length along the Y-axis direction is 54 mm. When the size of the adapter plate 11 is the same, Figure 5 to Figure 7 As shown, the chip packaging structure 100 provided in the embodiment of the present application can integrate a larger number of chips, which is conducive to achieving higher computing power.
[0043] The above embodiments are only examples, and the scheme protected by this application does not limit the type and quantity of chips, nor does it limit the relative position relationship between chips. For example, among the multiple first chips 121 included in the chip packaging structure 100, at least one first chip 121(a) can be a computing chip, and at least one first chip 121(b) can be a storage chip. In addition, among the multiple second chips 122 included in the chip packaging structure 100, at least one second chip 122(a) can be a control chip, and at least one second chip 122(b) can be a storage chip.
[0044] The size of the adapter board 11 is comprehensively considered based on the number of different types of chips that need to be integrated. The packaging structure provided in accordance with the embodiment of the present application can minimize the size of the adapter board 11, thereby improving the warping problem, improving the welding reliability problem, and further improving the yield rate.
[0045] In addition, under the premise that the size of the adapter board 11 remains unchanged, the packaging structure provided in accordance with the embodiment of the present application can improve the integration of the system and integrate more chips, including but not limited to storage chips, radio frequency chips, etc., or micro-electromechanical systems, optical elements, etc. can be integrated on the adapter board 11 as needed.
[0046] In some embodiments, the adapter board 11 includes one of a silicon adapter board, an organic adapter board, and a glass adapter board. All types of adapter boards can realize the simultaneous arrangement of the chip 12 on the front side P1 and the back side P2, thereby improving the utilization rate of the adapter board 11, and being conducive to reducing the size of the adapter board 11, improving the system integration, improving the warping problem, improving the welding reliability problem, and thus improving the yield rate.
[0047] In a second aspect, the present application also provides an electronic device 200, such as Figure 8 As shown, Figure 8 An electronic device provided in an embodiment of the present application includes the electronic device 200 including the chip packaging structure 100 mentioned above and a circuit board 201 , wherein the chip packaging structure 200 is electrically connected to the circuit board 201 .
[0048] In the chip packaging structure 100 in the electronic device 200, at least one first chip 121 is arranged on the side of the adapter board 11 away from the packaging substrate 10, and at least one second chip 122 is arranged between the adapter board 11 and the packaging substrate 10. In other words, the first chip 121 is arranged on the front of the adapter board 11, and the second chip 122 is arranged on the back of the adapter board 11. Compared with the related art, under the same integration (that is, the number of integrated chips in the chip packaging structure is the same), the chip packaging structure 100 fully utilizes the space on the front and back of the adapter board, reduces the area of the adapter board 11, and further reduces the size of the chip packaging structure 100, improves the integration per unit area of the system, improves the warping problem and the welding reliability problem, and improves the device yield. In addition, compared with the related art, under the condition that the size of the chip packaging structure 100 is the same, the chip packaging structure 100 fully utilizes the back of the adapter board, arranges more chips, and further improves the integration per unit area of the system.
[0049] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.
Claims
1. A chip packaging structure, characterized in that: include: Package substrate; An adapter plate, disposed on the packaging substrate and electrically connected to the packaging substrate; A plurality of chips include at least one first chip and at least one second chip, wherein the first chip is arranged on a side of the adapter board away from the packaging substrate, and the first chip is electrically connected to the adapter board; the second chip is arranged between the adapter board and the packaging substrate, and the second chip is electrically connected to the adapter board.
2. The chip packaging structure according to claim 1, characterized in that: An orthographic projection of at least one first chip on the packaging substrate overlaps with an orthographic projection of at least one second chip on the packaging substrate.
3. The chip packaging structure according to claim 1, characterized in that: An area of an orthographic projection of at least one second chip on the packaging substrate is smaller than an area of an orthographic projection of at least one first chip on the packaging substrate.
4. The chip packaging structure according to claim 1, characterized in that: At least one first chip is a computing chip; The plurality of chips include a plurality of second chips, among which at least one second chip is a control chip and at least one second chip is a storage chip.
5. The chip packaging structure according to claim 4, characterized in that: The area of the orthographic projection of the adapter plate on the packaging substrate is 2160 mm 2 ; The number of the computing chips is four, the number of the control chip is one, and the number of the storage chips is eight.
6. The chip packaging structure according to claim 1, characterized in that: The multiple chips include multiple first chips, among which at least one first chip is a computing chip and at least one first chip is a storage chip; At least one second chip is a control chip.
7. The chip packaging structure according to claim 6, characterized in that: The area of the orthographic projection of the adapter plate on the packaging substrate is 2916 mm 2 ; The number of the computing chips is four, the number of the control chip is one, and the number of the storage chips is twelve.
8. The chip packaging structure according to claim 1, characterized in that: The adapter plate includes one of a silicon adapter plate, an organic adapter plate, and a glass adapter plate.
9. An electronic device, characterized in that: include: The chip packaging structure according to any one of claims 1 to 8; A circuit board, the chip packaging structure is electrically connected to the circuit board.