SiC MOSFET phase-shifted full-bridge topology circuit and control method

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) phase-shifted full-bridge topology circuit and a control method, belongs to the technical field of phase-shifted full-bridge topology circuits, and provides a SiC MOSFET phase-shifted full-bridge topology of which the secondary side adopts an active absorption circuit. The invention provides a method for solving the problem of mis-turn-off caused by interlayer capacitance interference of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) phase-shifted full-bridge topology under a no-load condition. The invention provides an active absorption circuit for solving the parasitic oscillation problem of a secondary rectifier diode, which can absorb oscillation voltage and feed back energy in an absorption capacitor to a load at the same time, and basically does not generate extra loss.

Description

Technical Field

[0001] The present invention relates to a phase-shifted full-bridge topology circuit, in particular to a SiC MOSFET phase-shifted full-bridge topology circuit and a control method, belonging to the technical field of phase-shifted full-bridge topology circuits. Background Art

[0002] With the rapid development of my country's social economy and the country's strong support for the new energy industry, switching power supplies have been widely used in various fields. High power, high efficiency and small size of switching power supplies have also become its development trend. However, the high efficiency and small size of switching power supplies are contradictory. The most direct and effective way to reduce the size of switching power supplies is to increase the operating frequency of the power supply, thereby reducing the size of frequency-related and large-volume devices such as inductors, capacitors and high-frequency transformers. However, the increase in frequency means an increase in the number of switching times of the power switch tube per unit time, which will directly lead to an increase in its switching loss, and the efficiency of the power supply will decrease accordingly. Soft switching technology can improve the efficiency of the power supply while increasing the switching frequency.

[0003] Among many soft switching topologies, the phase-shifted full-bridge topology has the advantages of simple circuit structure and easy parameter design, and is widely used in medium and high power applications. The phase-shifted full-bridge converter has the advantages of simple topology, constant switching frequency, zero voltage turn-on (ZVS) by using only its own parasitic parameters, low switching loss, high efficiency, etc., and with the emergence of the third-generation wide bandgap material SiC, SiC power devices have good application prospects in high temperature, high voltage, high frequency, and high power occasions. However, due to the high switching speed and parasitic parameters of SiC MOSFET, the phase-shifted full-bridge topology has a voltage oscillation problem caused by the parasitic capacitance of the secondary rectifier bridge after the introduction of SiC MOSFET. For the parasitic oscillation problem of the secondary rectifier diode, the existing technology mostly adopts the addition of RC absorption circuit or RCD absorption circuit to absorb the voltage spike. For the circulating current loss, the existing technical solution adopts a voltage doubling rectification solution, which can reduce the circulating current to the excitation current, thereby reducing the circulating current loss. However, the peak value of the primary current of the topology of this solution is large, and the current stress of the switch tube is large. Therefore, a SiC MOSFET phase-shifted full-bridge topology circuit and control method are designed to solve the above problems. Summary of the invention

[0004] The main purpose of the present invention is to provide a SiC MOSFET phase-shifted full-bridge topology circuit and a control method.

[0005] The purpose of the present invention can be achieved by adopting the following technical solutions:

[0006] A SiC MOSFET phase-shifted full-bridge topology circuit includes a three-phase full-bridge rectifier, wherein the three-phase full-bridge rectifier is respectively coupled with an advanced bridge arm module and a lagging bridge arm module;

[0007] The three-phase full-bridge rectifier is coupled to the high-frequency inverter T through the leading bridge arm module and the lagging bridge arm module, and is coupled to the diode group through the high-frequency inverter T.

[0008] Preferably, the three-phase full-bridge rectifier includes diodes D1 to D6, and the anode of diode D1 is electrically connected to the alternating current U A , the cathode of diode D4;

[0009] The anode of diode D2 is electrically connected to the alternating current U B , the cathode of diode D5;

[0010] The anode of diode D3 is electrically connected to the alternating current U C , the cathode of diode D6;

[0011] The cathodes of diodes D1 to D3 are electrically connected to the leading bridge arm module and the lagging bridge arm module;

[0012] Anodes of diodes D4 to D6 are electrically connected to the leading bridge arm module and the lagging bridge arm module.

[0013] Preferably, the leading bridge arm module includes SiC MOSFET Q1 and SiC MOSFET Q2;

[0014] The drain of SiC MOSFET Q1 is electrically connected to the cathode of diode D1 to diode D3;

[0015] The source of SiC MOSFET Q2 is electrically connected to the anode of diode D4 to diode D6;

[0016] The source of SiC MOSFET Q1 is electrically connected to the drain of SiC MOSFET Q2 and connected to the inductor Lr. The other end of the inductor Lr is electrically connected to the anode of the diode Dc1, the cathode of the diode Dc2 and the Np end of the high-frequency inverter T.

[0017] Preferably, the anode of the diode Dc2 is electrically connected to the source of the SiC MOSFET Q2, and the drain of the SiC MOSFET Q1 is also electrically connected to the cathode of the diode Dc1;

[0018] The lagging bridge arm module includes a drain of SiC MOSFET Q3 electrically connected to the other end of Np of the high-frequency inverter T, a source of SiC MOSFET Q3 electrically connected to the anode of diode Dc2, a drain of SiC MOSFET Q4 electrically connected to the other end of Np of the high-frequency inverter T, and a source of SiC MOSFET Q4 electrically connected to the cathode of diode Dcl.

[0019] Preferably, the diode group includes diodes Dr1 to Dr4;

[0020] The anode of diode Dr1 is electrically connected to the cathode of diode Dr2, the cathode of diode Dr1 is electrically connected to the cathode of diode Dr4, the cathode of diode Dr3 is electrically connected to the anode of diode Dr4, the anode of diode Dr4 is electrically connected to the anode of diode Dr2, the anode of diode Dr1 is electrically connected to one end of Ns of high-frequency transformer T, and the cathode of diode Dr3 is electrically connected to the other end of Ns of high-frequency transformer T.

[0021] Preferably, the cathode of the diode Dr4 is electrically connected to the anode of the diode D7 and one end of the inductor Lf;

[0022] The cathode of the diode D7 is electrically connected to one end of the capacitor Ck and the source of the SiC MOSFET Q5;

[0023] The other end of the capacitor Ck is electrically connected to the anode of the diode Dr3, the drain of the SiC MOSFET Q6, one end of the capacitor Cf and the negative electrode of Rload;

[0024] The anode of Rload is electrically connected to the other end of the inductor Lf, the other end of the inductor Lk, and the other end of the capacitor Cf.

[0025] A SiC MOSFET phase-shifted full-bridge topology circuit control method comprises the following steps:

[0026] Step 1: It is found that when there is no load, the turn-off of SiC MOSFET in the phase-shifted full-bridge topology is zero voltage turn-off, and its turn-on is hard turn-on. The turn-on process of SiC MOSFET at no load is tested at a DC bus voltage of 200V.

[0027] Step 2: It is found that when the drain-source voltage VDS decreases, the input signal voltage Vin of the driver chip will drop. The drop of Vin causes the SiC MOSFET to be mistakenly turned off, and VDS no longer decreases but forms a platform.

[0028] Beneficial technical effects of the present invention:

[0029] The present invention provides a SiC MOSFET phase-shifted full-bridge topology circuit and a control method. The present invention proposes a SiC MOSFET phase-shifted full-bridge topology with an active absorption circuit on the secondary side.

[0030] The present invention proposes a method for solving the problem of false shutdown caused by interlayer capacitance interference in a SiC MOSFET phase-shifted full-bridge topology under no-load conditions.

[0031] The present invention proposes an active absorption circuit for solving the parasitic oscillation problem of a secondary-side rectifier diode, which can feed back the energy in an absorption capacitor to a load while absorbing the oscillation voltage, and basically does not generate additional loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A phase-shifted full-bridge topology principle diagram of a preferred embodiment of a SiC MOSFET phase-shifted full-bridge topology circuit and control method according to the present invention;

[0033] Figure 2 It is a phase-shifted full-bridge power supply efficiency curve diagram according to a preferred embodiment of a SiC MOSFET phase-shifted full-bridge topology circuit and control method of the present invention;

[0034] Figure 3 The waveform diagram of input signal Vin and VDS when SiC MOSFET is turned on under no-load condition according to a preferred embodiment of a SiC MOSFET phase-shifted full-bridge topology circuit and control method of the present invention;

[0035] Figure 4 (a) is a schematic diagram of Cg, and (b) is a coupling equivalent circuit diagram of a preferred embodiment of a SiC MOSFET phase-shifted full-bridge topology circuit and a control method according to the present invention;

[0036] Figure 5 (a) Top Layer PCB layout, (b) Signal Layer 1 PCB layout, (c) Signal Layer 2 PCB layout, (d) Bottom Layer PCB layout diagram of a preferred embodiment of a SiC MOSFET phase-shifted full-bridge topology circuit and control method according to the present invention;

[0037] Figure 6 This is a VDS waveform diagram of a SiC MOSFET turned on under no-load condition with a four-layer board according to a preferred embodiment of a SiC MOSFET phase-shifted full-bridge topology circuit and a control method of the present invention;

[0038] Figure 7 A comparison diagram of transformer secondary voltage waveforms with and without an RCD absorption circuit according to a preferred embodiment of a SiC MOSFET phase-shifted full-bridge topology circuit and control method of the present invention;

[0039] Figure 8 A comparison diagram of the secondary voltage waveforms of the absorption circuit transformer with different resistance absorption resistors according to a preferred embodiment of a SiC MOSFET phase-shifted full-bridge topology circuit and a control method of the present invention;

[0040] (a) Voltage waveform using 2.5kΩ absorption resistor, (b) Voltage waveform using 10kΩ absorption resistor;

[0041] Fig. 9 It is a schematic diagram of an active absorption circuit according to a preferred embodiment of a SiC MOSFET phase-shifted full-bridge topology circuit and a control method of the present invention;

[0042] Fig.10 The figure is a transformer secondary voltage waveform diagram after active absorption according to a preferred embodiment of a SiC MOSFET phase-shifted full-bridge topology circuit and control method of the present invention. DETAILED DESCRIPTION

[0043] In order to make the technical solution of the present invention more clear and specific to those skilled in the art, the present invention is further described in detail below in conjunction with embodiments and drawings, but the implementation manner of the present invention is not limited thereto.

[0044] Figure 1 This is the schematic diagram of the phase-shifted full-bridge topology. In the figure, UA, UB, and UC are three-phase AC power, D1~D6 are six diodes, forming a three-phase full-bridge rectifier, Q1~Q4 are four SiC MOSFETs, Q1 and Q2 are located on the high and low voltage sides of the leading bridge arm, Q4 and Q3 are located on the high and low voltage sides of the lagging bridge arm, respectively; T is a high-frequency transformer, the turns ratio K = Ns / Np, where Np is the number of turns on the primary side and Ns is the number of turns on the secondary side; Lr is the resonant inductor; Cf is the output filter capacitor; Lf is the output filter inductor. ILr is the current flowing through Lr; Ip is the current flowing through the primary side of T; VAB is the voltage between the midpoint A of the leading bridge arm and the midpoint B of the lagging bridge arm; VDC is the bus voltage; Vrect is the voltage on the secondary side of the high-frequency transformer after the rectifier diode. D7 is the absorption circuit diode, Q5 and Q6 are the switch tubes in the Buck circuit, and Lk is the absorption inductor.

[0045] The rated input voltage of the phase-shifted full-bridge topology power supply designed in the present invention is 380V AC, and the rated output power is 8kW. The efficiency of the power supply is tested when the three-phase AC input voltage Vin of the power supply takes the minimum value, the rated value and the maximum value respectively. The efficiency and load curves are shown in FIG. Figure 2 As shown in the figure, within the load range of 20% to 100%, the converter efficiency is greater than 94%, and the maximum efficiency reaches 98.2%. When the load remains unchanged, the efficiency decreases as Vin increases. When Vin is at its maximum, the full load efficiency can reach 97.3%.

[0046] Interference problem of interlayer capacitance on driving circuit

[0047] When a double-layer PCB board is used, due to wiring limitations, the drain trace has to be laid out below the drive circuit in the case of a DC bus stack layout. Two SiC MOSFETs are used in parallel, and the drain traces are connected and located below the drive circuit. The drive loop only contains a SOT-23-6 packaged driver chip and several 0805 packaged resistors and capacitors, and the drive loop area.

[0048] The experiment found that when there is no load, the SiC MOSFET in the phase-shifted full-bridge topology is turned off at zero voltage, and its conduction is hard conduction. The conduction process of the SiC MOSFET at no load is tested at a DC bus voltage of 200V, and the waveform is shown in Figure 3 As shown in the figure, it is found that when the drain-source voltage VDS decreases, the input signal voltage Vin of the driver chip will drop. The drop of Vin causes the SiC MOSFET to be turned off by mistake, and VDS no longer decreases but a platform appears. It can be seen that the change of VDS of SiC MOSFET interferes with the input signal. Figure 3 The reason why the input signal voltage Vin drops is that the drain is located below the input signal line in the PCB layout, and there is an interlayer capacitance Cg between the input signal and the drain. Figure 4 As shown in (a), the drain-source voltage VDS is coupled with Vin. The equivalent circuit is shown in Figure 4 (b) as shown.

[0049] The coupling effect of the power circuit on the drive circuit is related to the coupling capacitance Cg, Riso and Cin. The larger the Cg and Riso, the stronger the coupling effect. In order to reduce the coupling effect of the power circuit on the drive circuit, a four-layer PCB board is used to separate the power circuit and the drive circuit and lay a layer of "ground" under the drive circuit to control the source to reduce the coupling capacitance; the isolation chip with strong current pulling capability and small output resistance can be selected to solve this problem. The four-layer PCB layout diagram is as follows Figure 5 As shown in the figure, the driving circuit part adopts a stacked layout structure, and the power circuit adopts a stacked busbar layout and is laid in the middle of the PCB board without intersection with the driving board.

[0050] Figure 5 In the PCB layout, the phase-shifted full-bridge main power supply topology can be divided into three parts: control circuit, drive circuit and power circuit. The reference grounds of the control circuit are DGND1 and DGND2 respectively. The control circuit and the drive circuit are isolated by an isolation chip. The DC-DC power supply chip has an isolation structure inside, thereby completely separating the control circuit and the drive circuit. The power circuit has no intersection with the drive circuit and the control circuit, and is laid in the middle part of the PCB board. Figure 5The pin color of each chip in the figure indicates that it is connected to the reference plane of the corresponding color. In the drive circuit layout, the drive chip converts the PWM signal from the isolation chip into a drive signal and applies it between the gate and source of the SiC MOSFET. A loop resistor is connected in series with the source pin of the parallel SiC MOSFET to suppress the drive circuit circulation under transient conditions; a capacitor is connected in parallel between the gate and source of the SiC MOSFET to suppress the voltage oscillation of the Miller platform and the crosstalk of the bridge arm. In the power circuit, the DC filter electrolytic capacitors C1-C4 are connected in parallel at the positive and negative DC bus at the input end to reduce DC pulsation and voltage ripple; on the AC output side, due to the high switching speed of the SiC MOSFET, the parasitic parameters in the bridge circuit will generate a shutdown overvoltage and cause voltage oscillation during its shutdown process. Therefore, the absorption capacitors C5 and C6 are connected in parallel between the output AC bus. When C5 and C6 are much larger than the output capacitance of the SiC MOSFET, the parasitic inductance of the DC bus can be decoupled from the power circuit, thereby reducing the shutdown overvoltage and voltage oscillation.

[0051] Figure 5 (a) is the PCB layout of the Top Layer, which is the top layer of the PCB board and all devices are arranged on this layer. The power circuit of this layer is laid with the output AC bus, as shown by the red copper in the figure; the drive circuit of this layer is laid with four independent reference ground planes; the control circuit of this layer is laid with two independent reference ground planes. Figure 5 (b) is the PCB layout of Signal Layer 1. The power circuit of this layer is laid with the output AC bus, as shown by the yellow copper in the figure; the drive circuit of this layer is laid with four independent reference ground planes; and the control circuit of this layer is laid with two independent reference ground planes. Figure 5 (c) is the PCB layout of Signal Layer 2. The power circuit of this layer is laid with the input positive DC bus, as shown by the cyan copper in the figure; the driver circuit of this layer is laid with the 22V DC plane stepped down by LDO and the 5V DC plane output by the DC-DC power supply chip; the control circuit of this layer is laid with two independent reference ground planes. Figure 5 (d) is the Bottom Layer PCB layout. The power circuit of this layer is laid with an input negative DC bus, as shown by the blue copper in the figure; the drive circuit of this layer is laid with four independent reference ground planes; and the control circuit of this layer is laid with two independent reference ground planes. The Top Layer, Signal Layer1, Signal Layer2 PCB layout, and the Bottom Layer are laid with parallel "ground" planes, which can greatly reduce the parasitic capacitance between layers. An isolation chip with strong current pulling capability and small output resistance is used to isolate the drive circuit from the control circuit. The designed four-layer board was used for a no-load experiment. The experimental waveform is shown as follows. Figure 6As shown in the figure, the drain-source voltage VDS of the SiC MOSFET does not show a platform when it is turned on, indicating that the SiC MOSFET is not turned on by mistake. The experimental results show that the four-layer PCB layout solves the problem of interference between the layer capacitance and the drive circuit.

[0052] Secondary side rectifier diode parasitic oscillation suppression

[0053] 3.1 Clamping diode

[0054] When the phase-shifted full-bridge power supply is working, the primary voltage will be clamped by the clamping diode Dc2. When the parasitic capacitance of the secondary rectifier bridge causes voltage oscillation, when the primary voltage is close to exceeding VDC, it will be clamped to VDC by Dc2, and the corresponding secondary voltage will be clamped to KVDC, thereby avoiding voltage oscillation and spikes of the secondary voltage. But in fact, if there is no Dc2, when the secondary voltage rises to KVDC, it will continue to increase, resulting in voltage spikes and voltage oscillations, which is essentially the resonance process of Lr with CDr1 and CDr3. The voltage spikes generated by parasitic oscillations may cause the secondary rectifier diode to be broken down, and the high-frequency voltage oscillation will undoubtedly bring electromagnetic interference.

[0055] 3.2 Absorption circuit

[0056] To solve the parasitic oscillation problem of the secondary rectifier diode, an RC absorption circuit or an RCD absorption circuit is generally used to absorb the voltage spike generated by the parasitic oscillation. The RCD absorption circuit has a better oscillation suppression effect than the RC circuit, but both of the above absorption circuits have absorption resistors, which will cause additional losses. Figure 7 Comparison of transformer secondary voltage waveforms with and without RCD absorption circuit. The RCD absorption circuit has a significant suppressing effect on oscillation.

[0057] Figure 8 The following is a comparison of the voltage waveforms on the secondary side of the transformer using different resistance absorption resistors. The smaller the absorption resistor, the better the absorption effect of the absorption circuit, but the greater the power loss on the absorption resistor. According to the rated 8kW, when using a 10kΩ absorption resistor, the power loss on the absorption resistor is about 13W, and the power loss is 0.1625%; when using a 5kΩ absorption resistor, the power loss on the absorption resistor is about 25W, and the power loss is 0.3125%; when using a 2.5kΩ absorption resistor, the power loss on the absorption resistor is about 50W, and the power loss is 0.625%.

[0058] In view of the power loss in the RCD absorption circuit, this patent proposes an active absorption circuit, which transforms the absorption resistor in the RCD absorption circuit into a Buck step-down circuit. Fig. 9 shown.

[0059] The active absorption circuit controls the conduction of Q5 and Q6 tubes by detecting the voltage on Vrect and the absorption capacitor Ck, realizing the voltage regulation of Ck, making the Ck voltage slightly larger than Vrect, thereby absorbing the spikes caused by the parasitic oscillation of the secondary rectifier diode. The absorption effect is as follows: Fig.10 As shown in the figure, the energy absorbed by the absorption circuit is output to the load. As a result, the parasitic oscillation of the secondary rectifier diode can be effectively suppressed, and the power loss in the absorption circuit can be greatly reduced. Compared with the case of using a 5kΩ absorption resistor, this solution can reduce the power loss by 0.3125%.

[0060] The above description is only a further embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and concepts of the present invention within the scope disclosed by the present invention, which belong to the protection scope of the present invention.

Claims

1. A SiC MOSFET phase-shifted full-bridge topology circuit, characterized in that: It includes a three-phase full-bridge rectifier, and the three-phase full-bridge rectifier is respectively coupled with an advanced bridge arm module and a lagging bridge arm module; The three-phase full-bridge rectifier is coupled to the high-frequency inverter T through the leading bridge arm module and the lagging bridge arm module, and is coupled to the diode group through the high-frequency inverter T.

2. A SiC MOSFET phase-shifted full-bridge topology circuit according to claim 1, characterized in that: The three-phase full-bridge rectifier includes diodes D1 to D6. The anode of the diode D1 is electrically connected to the AC power U A , the cathode of diode D4; The anode of diode D2 is electrically connected to the alternating current U B , the cathode of diode D5; The anode of diode D3 is electrically connected to the alternating current U C , the cathode of diode D6; The cathodes of diodes D1 to D3 are electrically connected to the leading bridge arm module and the lagging bridge arm module; Anodes of diodes D4 to D6 are electrically connected to the leading bridge arm module and the lagging bridge arm module.

3. A SiC MOSFET phase-shifted full-bridge topology circuit according to claim 2, characterized in that: The advanced bridge arm module includes SiC MOSFET Q1 and SiC MOSFET Q2; The drain of SiC MOSFET Q1 is electrically connected to the cathode of diode D1 to diode D3; The source of SiC MOSFET Q2 is electrically connected to the anode of diode D4 to diode D6; The source of SiC MOSFET Q1 is electrically connected to the drain of SiC MOSFET Q2 and connected to the inductor Lr. The other end of the inductor Lr is electrically connected to the anode of the diode Dc1, the cathode of the diode Dc2 and the Np end of the high-frequency inverter T.

4. A SiC MOSFET phase-shifted full-bridge topology circuit according to claim 3, characterized in that: The anode of the diode Dc2 is electrically connected to the source of the SiC MOSFET Q2, and the drain of the SiC MOSFET Q1 is also electrically connected to the cathode of the diode Dc1; The lagging bridge arm module includes a drain of SiC MOSFET Q3 electrically connected to the other end of Np of the high-frequency inverter T, a source of SiC MOSFET Q3 electrically connected to the anode of diode Dc2, a drain of SiC MOSFET Q4 electrically connected to the other end of Np of the high-frequency inverter T, and a source of SiC MOSFET Q4 electrically connected to the cathode of diode Dcl.

5. A SiC MOSFET phase-shifted full-bridge topology circuit according to claim 4, characterized in that: The diode group includes diodes Dr1 to Dr4; The anode of diode Dr1 is electrically connected to the cathode of diode Dr2, the cathode of diode Dr1 is electrically connected to the cathode of diode Dr4, the cathode of diode Dr3 is electrically connected to the anode of diode Dr4, the anode of diode Dr4 is electrically connected to the anode of diode Dr2, the anode of diode Dr1 is electrically connected to one end of Ns of high-frequency transformer T, and the cathode of diode Dr3 is electrically connected to the other end of Ns of high-frequency transformer T.

6. A SiC MOSFET phase-shifted full-bridge topology circuit according to claim 5, characterized in that: The cathode of the diode Dr4 is electrically connected to the anode of the diode D7 and one end of the inductor Lf; The cathode of the diode D7 is electrically connected to one end of the capacitor Ck and the source of the SiC MOSFET Q5; The other end of the capacitor Ck is electrically connected to the anode of the diode Dr3, the drain of the SiC MOSFET Q6, one end of the capacitor Cf and the negative electrode of Rload; The anode of Rload is electrically connected to the other end of the inductor Lf, the other end of the inductor Lk, and the other end of the capacitor Cf.

7. A SiC MOSFET phase-shifted full-bridge topology circuit control method, based on a SiC MOSFET phase-shifted full-bridge topology circuit according to any one of claims 1 to 5, characterized in that: The steps include: Step 1: It is found that when there is no load, the turn-off of SiC MOSFET in the phase-shifted full-bridge topology is zero voltage turn-off, and its turn-on is hard turn-on. The turn-on process of SiC MOSFET at no load is tested at a DC bus voltage of 200V. Step 2: It is found that when the drain-source voltage VDS decreases, the input signal voltage Vin of the driver chip will drop. The drop of Vin causes the SiC MOSFET to be mistakenly turned off, and VDS no longer decreases but forms a platform.

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