Miniaturized ultra-wideband high-pass filter and notch integrated chip based on LTCC (Low Temperature Co-Fired Ceramic) technology

Abstract

The invention discloses a miniaturized ultra-wideband high-pass filter and notch integrated chip based on an LTCC (Low Temperature Co-Fired Ceramic) technology. The chip comprises a base body, an outer electrode, a filter circuit module and a wave trap module, the interior of the chip is formed by stacking 21 circuit layers, and the chip mainly comprises a capacitor plate metal layer and an inductor winding metal layer of an ultra-wideband high-pass filter, a wave trap strip line metal layer, a bottom grounding plate, a top grounding plate and the like. According to the invention, a three-dimensional structure of an LTCC technology is combined for construction, so that the chip is small in size and high in integration level, and adapts to the development trend of integration and miniaturization of new electronic components; a transmission zero point is adjusted through the resonator, in-band impedance matching and out-of-band rejection are adjusted through impedance matching, and the high-pass filter with the ultra-wide frequency band and high out-of-band signal rejection is achieved. Moreover, the system has the advantages of high suppression of clutter interference near a specific frequency, low loss, multiple transmission zero points, steep notch curve, high reliability and the like.

Description

Technical Field

[0001] The invention belongs to the technical field of filters, and in particular relates to a miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology. Background Art

[0002] With the rapid development of wireless communication technology, the demand for high-performance, miniaturized RF components is growing. In the fields of military, aerospace, and civil communications, the trend of miniaturization and multifunctionality of equipment has put forward higher requirements for key components such as filters. As one of the core components in the communication system, the performance of the filter directly affects the communication quality and reliability of the entire system. Traditional filter designs often face problems such as large size, high loss, insufficient selectivity, and limited out-of-band suppression capabilities, which makes it difficult to meet the growing demand for high-performance filters in modern communication systems.

[0003] As an advanced microelectronic packaging technology, low-temperature co-fired ceramic (LTCC) technology has attracted widespread attention due to its ability to achieve high-density integration and three-dimensional structure design. LTCC technology uses low-temperature co-fired ceramic materials as substrates to integrate passive components (such as capacitors and inductors) and active components through multi-layer circuit board technology. This technology can not only significantly reduce the size and weight of electronic components, but also improve the reliability and performance stability of components. In addition, LTCC technology also has excellent thermal stability and mechanical strength, making it an ideal choice for manufacturing high-performance RF components. Summary of the invention

[0004] The object of the present invention is to provide a miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology with the advantages of miniaturization, low loss, multiple transmission zero points, strong suppression of out-of-band signals, steep notch curve, high reliability, etc.

[0005] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is:

[0006] Provided is a miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology, which uses LTCC process technology to achieve three-dimensional integration of the chip, including a substrate, an external electrode, a filter circuit module, and a notch filter module;

[0007] The external electrode includes an input terminal, an output terminal and a ground terminal;

[0008] The filter circuit module and the wave trap module are arranged inside the substrate;

[0009] The filter circuit module includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a first inductor, a second inductor, a third inductor and a fourth inductor. One end of the first capacitor is connected to the input end through a first via hole, and the other end of the first capacitor is connected to one end of the third capacitor through a second via hole. At the same time, both ends of the third capacitor are connected in parallel with both ends of the fifth capacitor through a third via hole and a fourth via hole to form a first equivalent capacitor. One end of the seventh capacitor is connected to one end of the fifth capacitor through a fifth via hole, so that the first capacitor, the first equivalent capacitor and the seventh capacitor are connected in series. The input end is simultaneously connected to one end of the second capacitor through the first via hole, and the other end of the second capacitor is connected to one end of the first inductor through a thirteenth via hole to form a The series resonant structure forms a first zero point, one end of the fourth capacitor is connected to one end of the third capacitor through a sixth via hole, and the other end of the fourth capacitor is connected to one end of the second inductor through a fourteenth via hole to form a series resonant structure to form a second zero point, one end of the sixth capacitor is connected to one end of the fifth capacitor through a seventh via hole, and the other end of the sixth capacitor is connected to one end of the third inductor through a fifteenth via hole to form a series resonant structure to form a third zero point, one end of the eighth capacitor is connected to one end of the seventh capacitor through an eighth via hole, and the other end of the eighth capacitor is connected to one end of the fourth inductor through a sixteenth via hole to form a series resonant structure to form a fourth zero point, and the other ends of the first to fourth inductors are connected to the first ground layer through twenty-fifth to twenty-eighth via holes, respectively, so that the first to fourth inductors are connected in parallel;

[0010] The wave trap module comprises a first coupler, a second coupler and a third coupler, wherein the first coupler, the second coupler and the third coupler are sequentially connected in series;

[0011] The first ground layer is connected to the ground terminal.

[0012] Furthermore, the filter circuit module and the wave trap module are connected via a ground filtering decoupling capacitor to weaken the coupling effect between the filter circuit module and the wave trap module and achieve impedance matching.

[0013] Furthermore, the chip includes a multi-layer LTCC ceramic substrate and a circuit layer correspondingly arranged on the LTCC ceramic substrate.

[0014] Furthermore, the filtering circuit module has eleven layers, the first capacitor, the third capacitor, the fifth capacitor, and the seventh capacitor are arranged on the first, second, and third layers of the chip three-dimensional circuit, the second capacitor, the fourth capacitor, the sixth capacitor, and the eighth capacitor are arranged on the fourth, fifth, sixth, and seventh layers of the chip three-dimensional circuit, the first inductor, the second inductor, the third inductor, and the fourth inductor are arranged on the eighth, ninth, and tenth layers of the chip three-dimensional circuit, and the eleventh layer of the chip three-dimensional circuit is a ground layer.

[0015] Furthermore, the first to eighth capacitors all adopt parallel stacking technology to reduce the volume occupied by the capacitors and achieve chip miniaturization.

[0016] Furthermore, the first to fourth inductors all adopt a stacked structure, and the metal coils on different dielectric layers are connected through vias.

[0017] Furthermore, the trap module has ten layers, the first coupler is arranged on the twelfth and thirteenth layers of the chip three-dimensional circuit, the second coupler is arranged on the fifteenth, sixteenth and seventeenth layers of the chip three-dimensional circuit, the first coupler is arranged on the nineteenth and twentieth layers of the chip three-dimensional circuit, and the fourteenth, eighteenth and twenty-first layers of the chip three-dimensional circuit are ground layers.

[0018] Furthermore, the first to third couplers all adopt parallel coupled stripline structures, wherein the first coupler and the third coupler are both two-segment parallel coupled lines, and the second coupler is three-segment parallel coupled lines.

[0019] Furthermore, the dielectric layers where the first to third couplers are located are all provided with isolation walls, and the isolation walls are connected to the ground terminal to separate the coupling transmission line stages from each other and from other devices to avoid other coupling effects.

[0020] Furthermore, the circuit layer is made of metal, and the LTCC ceramic substrates thereof are LTCC dielectric substrates with a dielectric constant of 7.5 and a dielectric loss tangent of 0.003.

[0021] The beneficial effects of the present invention are as follows: the present invention adopts the LTCC process technology, and each circuit layer is connected through a via hole, thereby realizing a three-dimensional structure of a filter circuit, and fully utilizing the laminated structure, significantly reducing the size and weight of the electronic component, and improving the reliability and performance stability of the component; the chip has the advantages of miniaturization, low loss, multiple transmission zero points, strong suppression of out-of-band signals, steep notch curve, high reliability, etc.; through the resonator to adjust the transmission zero point, impedance matching to adjust the in-band impedance matching and out-of-band suppression, a high-pass filter with an ultra-wide frequency band and strong suppression of out-of-band signals is realized, and strong suppression of clutter interference near a specific frequency is satisfied; the overall chip packaging size is millimeter-level, which adapts to the development trend of integration and miniaturization of modern electronic components. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic diagram of the internal three-dimensional structure of the hidden ground plate of the integrated chip of the filter and notch according to an embodiment of the present invention;

[0023] Figure 2 is a schematic diagram of the internal structure of a filter plus notch integrated chip according to an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of the internal structure of a hidden ground plate of a filter plus notch integrated chip according to an embodiment of the present invention;

[0025] Figure 4 is a schematic front view of the internal structure of a filter plus notch integrated chip according to an embodiment of the present invention;

[0026] Figure 5 It is a schematic front view of the internal structure of the hidden ground plate of the integrated chip of the filter and notch according to an embodiment of the present invention;

[0027] Figure 6 is a top-level structural diagram of a filter plus notch integrated chip according to an embodiment of the present invention;

[0028] Figure 7 1 is a schematic diagram of the first internal circuit layer of a filter plus notch integrated chip according to an embodiment of the present invention;

[0029] Figure 8 1 is a schematic diagram of the internal second layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0030] Fig. 9 1 is a schematic diagram of the internal third layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0031] Fig.10 1 is a schematic diagram of the internal fourth layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0032] Fig.11 1 is a schematic diagram of the internal fifth layer circuit of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0033] Fig.12 1 is a schematic diagram of the sixth internal circuit of the integrated chip of the filter and notch according to an embodiment of the present invention;

[0034] Fig.13 is a schematic diagram of the seventh internal circuit layer of the integrated filter and notch chip according to an embodiment of the present invention;

[0035] Fig.141 is a schematic diagram of the internal eighth layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0036] Fig.15 is a schematic diagram of the inner ninth layer circuit of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0037] Fig.16 1 is a schematic diagram of the internal tenth layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0038] Fig.17 11th layer internal circuit diagram of the integrated chip of filter and notch according to an embodiment of the present invention;

[0039] Fig.18 is a schematic diagram of the internal twelfth layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0040] Fig.19 is a schematic diagram of the internal thirteenth layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0041] Fig. 20 14th layer circuit diagram of the internal chip of the integrated filter and notch according to an embodiment of the present invention;

[0042] Fig.21 is a schematic diagram of the internal fifteenth layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0043] Fig. 22 is a schematic diagram of the internal sixteenth layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0044] Fig.23 is a schematic diagram of the seventeenth internal circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0045] Fig.24 18th layer circuit diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0046] Fig.25 19th layer circuit diagram of the internal chip of the integrated filter and notch according to an embodiment of the present invention;

[0047] Fig.26 is a schematic diagram of the internal twentieth layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0048] Fig. 27 is a schematic diagram of the internal twenty-first layer circuit of the filter plus notch integrated chip according to an embodiment of the present invention;

[0049] Fig.28 is a schematic diagram of the bottom structure of a filter plus notch integrated chip according to an embodiment of the present invention;

[0050] Fig.29 Schematic diagram of the first and third circuit hole layers inside the integrated chip of the filter and notch according to an embodiment of the present invention;

[0051] Fig.30 2 is a schematic diagram of the second circuit hole layer inside the integrated filter and notch filter chip according to an embodiment of the present invention;

[0052] Fig.31 Schematic diagram of the fourth, fifth and sixth circuit hole layers inside the integrated filter and notch filter chip according to an embodiment of the present invention;

[0053] Fig.32 2 is a schematic diagram of the seventh internal circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0054] Fig.33 2 is a schematic diagram of the internal eighth-layer circuit hole layer of the filter plus notch integrated chip according to an embodiment of the present invention;

[0055] Fig.34 2 is a schematic diagram of the inner ninth circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0056] Fig.35 2 is a schematic diagram of the inner tenth circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0057] Fig.36 1 is a schematic diagram of the eleventh internal circuit hole layer of the filter plus notch integrated chip according to an embodiment of the present invention;

[0058] Fig.37 1 is a schematic diagram of the internal twelfth circuit hole layer of the filter plus notch integrated chip according to an embodiment of the present invention;

[0059] Fig.38 3 is a schematic diagram of the internal thirteenth circuit hole layer of the filter plus notch integrated chip according to an embodiment of the present invention;

[0060] Fig.39 14 is a schematic diagram of the internal circuit hole layer of the fourteenth layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0061] Fig.40 1 is a schematic diagram of the inner fifteenth circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0062] Fig.4116th circuit hole layer schematic diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0063] Fig.42 17th circuit hole layer schematic diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0064] Fig.43 1 is a schematic diagram of the internal eighteenth circuit hole layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0065] Fig.44 19th circuit hole layer schematic diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0066] Fig.45 2. It is a schematic diagram of the internal circuit hole layer of the 20th layer of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0067] Fig.46 21st circuit hole layer schematic diagram of the integrated filter and notch filter chip according to an embodiment of the present invention;

[0068] Fig.47 is a top-level perspective schematic diagram of the external structure of a filter plus notch integrated chip according to an embodiment of the present invention;

[0069] Fig.48 is a bottom-level perspective schematic diagram of the external structure of a filter plus notch integrated chip according to an embodiment of the present invention;

[0070] Fig.49 1 is a schematic diagram of the equivalent circuit principle of a filter plus notch integrated chip according to an embodiment of the present invention;

[0071] Fig.50 4 is an S parameter electrical performance curve of a filter plus notch integrated chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0072] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0073] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0074] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0075] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0076] The embodiment of the present invention provides a miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology.

[0077] like Figure 1-5 , Figures 47-49 As shown, the miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology includes a substrate 100, an external electrode 200 arranged on the surface of the substrate 100, and a filter circuit module 300 and a notch filter module 400 arranged inside the substrate 100. The substrate 100 is a low-temperature co-fired ceramic medium, which is realized by LTCC (Low Temperature Co-fired Ceramic, low-temperature co-fired ceramic) process, which is formed by printing electronic components on the surface of a multi-layer LTCC ceramic substrate and sintering, and is used to achieve high slope, high suppression effect, high Q value and miniaturization of ultra-wideband filters and notch filters.

[0078] In this embodiment, the chip includes a multi-layer LTCC ceramic substrate, each layer of the LTCC ceramic substrate is provided with a corresponding circuit layer, and each circuit layer is connected through vias, thereby realizing a three-dimensional structure of the filter circuit and making full use of the laminated structure.

[0079] The external electrode 200 includes an input electrode IN, an output electrode OUT and a ground electrode GND. The input electrode IN is used to receive a radio frequency signal, the output electrode OUT is used to output a filtered radio frequency signal, and the ground electrode GND is used to stabilize the voltage of the filter circuit module 300 and enable the filter circuit module 300 to work normally. The shapes and positions of the input electrode IN, the ground electrode GND and the output electrode OUT can be set accordingly according to the requirements, such as Figures 47-48In one embodiment, the input electrode IN and the output electrode OUT are respectively disposed on the left and right side surfaces of the substrate 100 , and the ground electrode GND is disposed on the front and rear plates and the bottom area of ​​the substrate 100 .

[0080] In this embodiment, the filter circuit module 300 and the trap module 400 are arranged inside the substrate 100 and are placed in the upper and lower parts respectively. The two circuit modules are connected through the ground filtering decoupling capacitor C9 to weaken the coupling between the filter circuit module and the trap module and achieve impedance matching, thereby improving the degree of suppression of clutter interference by the trap.

[0081] The filter circuit module 300 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4. Among them, one end of the first capacitor C1 is connected to the input electrode IN through the first via hole 501, and the other end of the first capacitor C1 is connected to one end of the third capacitor C3 through the second via hole 502. At the same time, the two ends of the third capacitor C3 are connected in parallel with the two ends of the fifth capacitor C5 through the third via hole 503 and the fourth via hole 504 to form a first equivalent capacitor, and one end of the seventh capacitor C7 is connected to one end of the fifth capacitor C5 through the fifth via hole, so that the first capacitor C1, the first equivalent capacitor, and the seventh capacitor C7 are connected in series; the input electrode IN is simultaneously connected to one end of the second capacitor C2 through the first via hole 501, and the other end of the second capacitor C2 is connected to one end of the first inductor L1 through the ninth via hole 509 to form a series resonant structure to form a first zero point, one end of the fourth capacitor C4 is connected to one end of the third capacitor C3 through the sixth via hole 506, and the other end of the fourth capacitor C4 is connected to One end of the second inductor L2 is connected to form a series resonant structure to form a second zero point, one end of the sixth capacitor C6 is connected to one end of the fifth capacitor C5 through the seventh via 507, the other end of the sixth capacitor C6 is connected to one end of the third inductor L3 through the eleventh via 511 to form a series resonant structure to form a third zero point, one end of the eighth capacitor C8 is connected to one end of the seventh capacitor C7 through the eighth via 508, the other end of the eighth capacitor C8 is connected to one end of the fourth inductor L4 through the twelfth via 512 to form a series resonant structure to form a fourth zero point, the other ends of the first inductor L1, the second inductor L2, the third inductor L3, and the fourth inductor L4 are connected to the first grounding layer 61 through the twenty-first via 521, the twenty-second via 522, the twenty-third via 523, and the twenty-fourth via 524, respectively, so that the first inductor L1, the second inductor L2, the third inductor L3, and the fourth inductor L4 are connected in parallel;

[0082] In this embodiment, the first to eighth capacitors C1, C2, C3, C4, C5, C6, C7, and C8 all adopt parallel stacking technology to reduce the volume occupied by the capacitors and realize chip miniaturization. Among them, the first capacitor C1, the third capacitor C3, the fifth capacitor C5, and the seventh capacitor C7 are three-layer parallel plate capacitors, which are arranged on the first, second, and third layers of the chip three-dimensional circuit. The second capacitor C2, the fourth capacitor C4, the sixth capacitor C6, and the eighth capacitor C8 are four-layer parallel plate capacitors, which are arranged on the fourth, fifth, sixth, and seventh layers of the chip three-dimensional circuit. The first inductor L1, the second inductor L2, the third inductor L3, and the fourth inductor L4 all adopt a stacking structure. The metal coils on different dielectric layers are connected through vias to form a stacking layer to reduce the volume of the inductor element and improve the integration. Among them, the first inductor L1, the second inductor L2, the third inductor L3, and the fourth inductor L4 are arranged on the eighth, ninth, and tenth layers of the chip three-dimensional circuit.

[0083] Combination Figure 1-17 , Figure 29-36 , the specific structures of the first circuit layer to the eleventh circuit layer are described in detail:

[0084] The first circuit layer includes a first electrode plate 3101 connected to a ninth electrode plate 3109 and an input electrode IN through a first via hole 501; a second electrode plate 3102 connected to a tenth electrode plate 3110 through a sixth via hole 506; a third electrode plate 3103 connected to an eleventh electrode plate 3111 through a seventh via hole 507; and a fourth electrode plate 3104 connected to a twelfth electrode plate 3112 through an eighth via hole 508;

[0085] The second circuit layer includes a fifth electrode plate 3105, the left part of which is connected to the first electrode plate 3101 and the ninth electrode plate 3109 respectively through vertical coupling, and the right part is connected to the tenth electrode plate 3110 through the second via 502; the left part of the sixth electrode plate 3106 is connected to the second electrode plate 3102 and the tenth electrode plate 3110 respectively through vertical coupling, and the right part is connected to the eleventh electrode plate 3111 through the third via 503; the left part of the seventh electrode plate 3107 is connected to the tenth electrode plate 3110 through the fourth via 504, and the right part is connected to the third electrode plate 3103 and the eleventh electrode plate 3111 respectively through vertical coupling; the left part of the eighth electrode plate 3108 is connected to the eleventh electrode plate 3111 through the fifth via 505, and the right part is connected to the fourth electrode plate 3104 and the twelfth electrode plate 3112 respectively through vertical coupling;

[0086] The third circuit layer is completely consistent with the first circuit layer in structure;

[0087] The fourth circuit layer includes a thirteenth electrode plate 3113 connected to a seventeenth electrode plate 3117 through vertical coupling, and connected to a twenty-first electrode plate 3121 through a ninth via 509; a fourteenth electrode plate 3114 connected to an eighteenth electrode plate 3118 through vertical coupling, and connected to a twenty-second electrode plate 3122 through a tenth via 510; a fifteenth electrode plate 3115 connected to a nineteenth electrode plate 3119 through vertical coupling, and connected to a twenty-third electrode plate 3123 through an eleventh via 511; a sixteenth electrode plate 3116 connected to a twentieth electrode plate 3120 through vertical coupling, and connected to a twenty-fourth electrode plate 3124 through a twelfth via 512;

[0088] The fifth circuit layer includes a seventeenth electrode plate 3117 connected to the twenty-fifth electrode plate 3125 and the input electrode IN through the first via hole 501; an eighteenth electrode plate 3118 connected to the tenth electrode plate 3110 and the twenty-sixth electrode plate 3126 through the sixth via hole 506; a nineteenth electrode plate 3119 connected to the eleventh electrode plate 3111 and the twenty-seventh electrode plate 3127 through the seventh via hole 507; and a twentieth electrode plate 3120 connected to the twelfth electrode plate 3112 and the twenty-eighth electrode plate 3128 through the eighth via hole 508;

[0089] The sixth circuit layer includes a twenty-first electrode plate 3121 connected to the twenty-fifth electrode plate 3125 through vertical coupling, and connected to the first metal conductor 3201 through the thirteenth via 513; the twenty-second electrode plate 3122 is connected to the twenty-sixth electrode plate 3126 through vertical coupling, and connected to the second metal conductor 3202 through the fourteenth via 514; the twenty-third electrode plate 3123 is connected to the twenty-seventh electrode plate 3127 through vertical coupling, and connected to the third metal conductor 3203 through the fifteenth via 515; the twenty-fourth electrode plate 3124 is connected to the twenty-eighth electrode plate 3128 through vertical coupling, and connected to the fourth metal conductor 3204 through the sixteenth via 516; wherein the thirteenth via 513 is connected to the ninth via 509, the fourteenth via 514 is connected to the tenth via 510, the fifteenth via 515 is connected to the eleventh via 511, and the sixteenth via 516 is connected to the twelfth via 512.

[0090] The seventh circuit layer is completely consistent with the fifth circuit layer in structure, and the twenty-eighth electrode plate 3128 is connected to the twenty-ninth electrode plate 3129 through the eighth via 508;

[0091] The eighth circuit layer includes a first metal conductive strip 3201 connected to a fifth metal conductive strip 3205 through a seventeenth via hole 517; a second metal conductive strip 3202 connected to a sixth metal conductive strip 3206 through an eighteenth via hole 518; a third metal conductive strip 3203 connected to a seventh metal conductive strip 3207 through a nineteenth via hole 519; and a fourth metal conductive strip 3204 connected to an eighth metal conductive strip 3208 through a twentieth via hole 520.

[0092] The ninth circuit layer includes a fifth metal conductive strip 3205 connected to a ninth metal conductive strip 3209 through a twenty-first via 521; a sixth metal conductive strip 3206 connected to a tenth metal conductive strip 3210 through a twenty-second via 522; a seventh metal conductive strip 3207 connected to an eleventh metal conductive strip 3211 through a twenty-third via 523; an eighth metal conductive strip 3208 connected to a twelfth metal conductive strip 3212 through a twenty-fourth via 524; and a twenty-ninth electrode plate 3129 connected to a second metal stripline 412 through an eighth via 508 and a thirtieth via 530.

[0093] The tenth circuit layer includes a ninth metal conductive strip 3209, a tenth metal conductive strip 3210, an eleventh metal conductive strip 3211, and a twelfth metal conductive strip 3212, which are respectively connected to the first ground layer 61 through a twenty-fifth via hole 525, a twenty-sixth via hole 526, a twenty-seventh via hole 527, and a twenty-eighth via hole 528;

[0094] The eleventh circuit layer includes the first ground layer 61 from which a matrix area having a length and a width of 0.35 mm and passing through the eighth via hole 508 is dug out.

[0095] Among them, the first electrode plate 3101, the fifth electrode plate 3105, and the ninth electrode plate 3109 form a capacitor C1; the second electrode plate 3102, the sixth electrode plate 3106, and the tenth electrode plate 3110 form a capacitor C3; the third electrode plate 3103, the seventh electrode plate 3107, and the eleventh electrode plate 3111 form a capacitor C5; the fourth electrode plate 3104, the eighth electrode plate 3108, and the twelfth electrode plate 3112 form a capacitor C7; the thirteenth electrode plate 3113, the seventeenth electrode plate 3117, the twenty-first electrode plate 3121, and the twenty-fifth electrode plate 3125 form a capacitor C2; the fourteenth electrode plate 3114, the eighteenth electrode plate 3118, the twenty-second electrode plate 3122, and the twenty-sixth electrode plate 3126 form a capacitor C4; the fifteenth electrode plate 3115, the nineteenth electrode plate 3117, the twenty-first electrode plate 3121, and the twenty-fifth electrode plate 3125 form a capacitor C2; Plate 3119, the twenty-third electrode plate 3123, and the twenty-seventh electrode plate 3127 form a capacitor C6; the sixteenth electrode plate 3116, the twentieth electrode plate 3120, the twenty-fourth electrode plate 3124, and the twenty-eighth electrode plate 3128 form a capacitor C8; the twenty-ninth electrode plate 3129 is a ground filtering and decoupling capacitor C9; the first metal conductive strip 3201, the fifth metal conductive strip 3205, and the ninth metal conductive strip 3209 form an inductor L1; the second metal conductive strip 3202, the sixth metal conductive strip 3206, and the tenth metal conductive strip 3210 form an inductor L2; the third metal conductive strip 3203, the seventh metal conductive strip 3207, and the eleventh metal conductive strip 3211 form an inductor L3; the fourth metal conductive strip 3204, the eighth metal conductive strip 3208, and the twelfth metal conductive strip 3212 form an inductor L4.

[0096] The wave trap module 400 includes a first coupler CL1, a second coupler CL2, and a third coupler CL3. The first coupler CL1, the second coupler CL2, and the third coupler CL3 are connected in series in sequence, wherein the other end of the first coupler CL1 is connected to one end of the ground filtering decoupling capacitor C9 through the thirtieth via 530, and the other end of the third coupler CL3 is connected to the output electrode OUT. The first coupler CL1, the second coupler CL2, and the third coupler CL3 all adopt a parallel coupled stripline structure, wherein the first coupler CL1 and the third coupler CL3 are two-segment parallel coupled lines, and the second coupler CL2 is three-segment parallel coupled lines. The first coupler CL1 is arranged on the 12th and 13th layers of the chip three-dimensional circuit, the second coupler CL2 is arranged on the 15th, 16th, and 17th layers of the chip three-dimensional circuit, and the third coupler CL3 is arranged on the 19th and 20th layers of the chip three-dimensional circuit. The fourteenth, eighteenth, and twenty-first layers are ground layers, which are connected to the ground electrode GND.

[0097] Combination Figure 18-27 , Figure 37-46 , the specific structures of the twelfth to twenty-first circuit layers are described in detail:

[0098] The twelfth circuit layer includes a first metal stripline 411 connected to a second metal stripline 412 through vertical coupling, and connected to the first ground layer 61 through a twenty-ninth via 529;

[0099] The thirteenth circuit layer includes the second metal strip line 412 connected to the fourth metal strip line through the thirty-first via 531;

[0100] The fourteenth circuit layer includes the second ground layer 62 where the matrix area having a length and a width of 0.35 mm passing through the thirty-first via hole 531 is dug out;

[0101] The fifteenth circuit layer includes a third metal stripline 413 connected to the fourth metal stripline 414 through vertical coupling, and connected to the second ground layer 62 through a thirty-second via 532;

[0102] The sixteenth circuit layer includes the fourth metal strip line 414 connected to the seventh metal strip line 417 through the thirty-third via 533;

[0103] The seventeenth circuit layer includes a fifth metal stripline 415 connected to the fourth metal stripline 414 through vertical coupling, and connected to the third ground layer 63 through a thirty-fourth via 534;

[0104] The eighteenth circuit layer includes the third ground layer 63 where the matrix area having a length and a width of 0.35 mm is dug out through the thirty-third via hole 533;

[0105] The nineteenth circuit layer includes the sixth metal stripline 416 connected to the seventh metal stripline 417 through vertical coupling, and connected to the third ground layer 63 through the thirty-fifth via 535;

[0106] The twentieth circuit layer includes a seventh metal strip line 417 connected to the output electrode OUT through a thirty-sixth via hole 536;

[0107] The twenty-first circuit layer includes a fourth ground layer 64 .

[0108] The first ground layer 61 , the second ground layer 62 , the third ground layer 63 , and the fourth ground layer 64 are all connected to the ground electrode GND.

[0109] The first metal stripline 411 and the second metal stripline 412 form a first coupler CL1; the third metal stripline 413, the fourth metal stripline 414, and the fifth metal stripline 415 form a second coupler CL2; and the sixth metal stripline 416 and the seventh metal stripline 417 form a third coupler CL3.

[0110] like Figure 18-19 , Figure 21-23As shown, the twelfth, thirteenth, fifteenth, sixteenth and seventeenth circuit layers where the coupler is located are all provided with isolation walls IW, the isolation walls IW are all connected to and grounded to the second grounding layer 62 and the third grounding layer 63, and a grounding layer is provided between each level of the coupled transmission line. This design separates the coupled transmission line levels from each other and from other devices, and at the same time plays the role of lateral isolation and longitudinal isolation to avoid other coupling effects that affect the passband width, and at the same time shields the internal circuit signals and provides strong support.

[0111] In this embodiment, the relative dielectric constant of the LTCC ceramic dielectric substrate used is 7.5, the dielectric loss tangent is 0.003, and the circuit layer material is metal, preferably metal silver.

[0112] In this embodiment, a miniaturized ultra-wideband high-pass filter plus notch integrated chip is constructed by using a three-dimensional structure of the LTCC process, and the overall package size is controlled to be 4.5×3.2×2.5mm. An ultra-wideband high-pass filter module and a notch filter module are integrated internally, and the transmission zero point is adjusted by the resonator, and the impedance matching is adjusted to adjust the in-band impedance matching and out-of-band suppression. Fig.50 , taking fc as the benchmark (fc is a frequency in the S band, and the horizontal axis is expressed as multiples of fc as the benchmark), a high-pass filter with an ultra-wide band of fc to 9*fc and strong out-of-band signal suppression is realized, and it has strong suppression of clutter interference near the 3*fc frequency within the fc to 9*fc band, and the suppression in the nearby frequency range exceeds 25dB. It has the performance characteristics of low loss, multiple transmission zeros, strong suppression of out-of-band signals, steep notch curve, high reliability, etc., meeting the requirements of integration and miniaturization of electronic components.

[0113] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology, characterized by: Use LTCC process technology to achieve three-dimensional integration of chips, including substrate, external electrodes, filter circuit module, and notch filter module; The external electrode includes an input terminal, an output terminal and a ground terminal; The filter circuit module and the wave trap module are arranged inside the substrate; The filter circuit module includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a first inductor, a second inductor, a third inductor and a fourth inductor. One end of the first capacitor is connected to the input end through a first via hole, and the other end of the first capacitor is connected to one end of the third capacitor through a second via hole. At the same time, both ends of the third capacitor are connected in parallel with both ends of the fifth capacitor through a third via hole and a fourth via hole to form a first equivalent capacitor. One end of the seventh capacitor is connected to one end of the fifth capacitor through a fifth via hole, so that the first capacitor, the first equivalent capacitor and the seventh capacitor are connected in series. The input end is simultaneously connected to one end of the second capacitor through the first via hole, and the other end of the second capacitor is connected to one end of the first inductor through a thirteenth via hole to form a The series resonant structure forms a first zero point, one end of the fourth capacitor is connected to one end of the third capacitor through a sixth via hole, and the other end of the fourth capacitor is connected to one end of the second inductor through a fourteenth via hole to form a series resonant structure to form a second zero point, one end of the sixth capacitor is connected to one end of the fifth capacitor through a seventh via hole, and the other end of the sixth capacitor is connected to one end of the third inductor through a fifteenth via hole to form a series resonant structure to form a third zero point, one end of the eighth capacitor is connected to one end of the seventh capacitor through an eighth via hole, and the other end of the eighth capacitor is connected to one end of the fourth inductor through a sixteenth via hole to form a series resonant structure to form a fourth zero point, and the other ends of the first to fourth inductors are connected to the first ground layer through twenty-fifth to twenty-eighth via holes, respectively, so that the first to fourth inductors are connected in parallel; The wave trap module comprises a first coupler, a second coupler and a third coupler, wherein the first coupler, the second coupler and the third coupler are sequentially connected in series; The first ground layer is connected to the ground terminal.

2. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 1, characterized in that: The filter circuit module and the wave trap module are connected via a ground filtering decoupling capacitor to weaken the coupling effect between the filter circuit module and the wave trap module and achieve impedance matching.

3. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 2, characterized in that: The chip includes a multi-layer LTCC ceramic substrate and a circuit layer correspondingly arranged on the LTCC ceramic substrate.

4. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 3, characterized in that: The filtering circuit module has eleven layers, the first capacitor, the third capacitor, the fifth capacitor, and the seventh capacitor are arranged on the first, second, and third layers of the chip three-dimensional circuit, the second capacitor, the fourth capacitor, the sixth capacitor, and the eighth capacitor are arranged on the fourth, fifth, sixth, and seventh layers of the chip three-dimensional circuit, the first inductor, the second inductor, the third inductor, and the fourth inductor are arranged on the eighth, ninth, and tenth layers of the chip three-dimensional circuit, and the eleventh layer of the chip three-dimensional circuit is a ground layer.

5. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 4, characterized in that: The first to eighth capacitors all adopt parallel stacking technology to reduce the volume occupied by the capacitors and realize chip miniaturization.

6. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 4, characterized in that: The first to fourth inductors all adopt a stacked structure, and the metal coils on different dielectric layers are connected through vias.

7. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 3, characterized in that: The trap module has ten layers, the first coupler is arranged on the twelfth and thirteenth layers of the chip three-dimensional circuit, the second coupler is arranged on the fifteenth, sixteenth and seventeenth layers of the chip three-dimensional circuit, the first coupler is arranged on the nineteenth and twentieth layers of the chip three-dimensional circuit, and the fourteenth, eighteenth and twenty-first layers of the chip three-dimensional circuit are ground layers.

8. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 7, characterized in that: The first to third couplers all adopt parallel coupled stripline structures, wherein the first coupler and the third coupler are both two-segment parallel coupled lines, and the second coupler is three-segment parallel coupled lines.

9. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 8, characterized in that: The dielectric layers where the first to third couplers are located are all provided with isolation walls, and the isolation walls are connected to the ground end to separate the coupling transmission line stages from each other and the stages from other devices to avoid other coupling effects.

10. The miniaturized ultra-wideband high-pass filter plus notch integrated chip based on LTCC technology according to claim 3, characterized in that: The circuit layer is made of metal, and the LTCC ceramic substrates are LTCC dielectric substrates with a dielectric constant of 7.5 and a dielectric loss tangent of 0.003.

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