Clock detection circuit and chip
By designing a clock detection circuit including filtering and combining logic modules to detect and calibrate the frequency of the input clock, the circuit abnormality caused by clock deviation in the prior art is solved, and effective detection and calibration of the clock frequency is achieved.
Patent Information
- Application Number
- CN202410889386.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-03
- Publication Date
- 2025-03-11
AI Technical Summary
In the prior art, the clock calibration function cannot be effectively calibrated when the input clock deviation is large, resulting in circuit abnormality.
A clock detection circuit is designed, including a first filter module, a second filter module and a combined logic module, and the frequency of the input clock is detected by filtering and combining logic processing, and only passes through the circuit when the frequency is in a specified passband range, otherwise the output level signal indicates a clock abnormality.
It realizes effective detection and calibration of the input clock, solves the circuit abnormality caused by clock deviation, and ensures that the clock frequency can pass through the detection circuit when it is within the specified range.
Smart Images
Figure CN119602757A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of circuit technology, and in particular to a clock detection circuit and chip. Background Art
[0002] Chips with clocks usually have a clock calibration function, which can calibrate the input clock generated by the clock source circuit, and then control the clock frequency of the input clock. For example, the phase-locked loop module can achieve phase alignment between the input clock and the reference clock by comparing the phases through the phase detector, thereby achieving the purpose of calibrating the input clock. However, the accuracy of clock calibration is limited. When the deviation of the input clock generated by the clock source circuit is large, the clock calibration function cannot effectively calibrate the input clock. Therefore, it is necessary to provide a clock detection circuit to detect the input clock generated by the clock source circuit. Summary of the invention
[0003] In view of the above problems, the present application provides a clock detection circuit and chip to solve the above technical problems.
[0004] In a first aspect, the present application provides a clock detection circuit, comprising:
[0005] A first filtering module, configured to receive a first clock, filter the first clock according to a first reference frequency and output a second signal, wherein when the frequency of the first clock is higher than the first reference frequency, the second signal is at a high level or a low level, otherwise the second signal is the same as the first clock;
[0006] a second filtering module, configured to receive the second signal, filter the second signal according to a second reference frequency and output a third signal, wherein when the frequency of the second signal is lower than the second reference frequency, the third signal is the high level or the low level, otherwise the third signal is the same as the first clock;
[0007] a combinational logic module, configured to receive the second signal and the third signal, perform combinational logic processing on the second signal and the third signal and output a fourth signal, wherein when the second signal and the third signal are the same as the first clock, the fourth signal is the same as the first clock, otherwise the fourth signal is the high level or the low level;
[0008] The first reference frequency is a characteristic frequency of the first filtering module, the second reference frequency is a characteristic frequency of the second filtering module, and the first reference frequency is higher than the second reference frequency.
[0009] In some embodiments, the first filtering module includes an active low-pass filtering unit.
[0010] In some embodiments, the second filtering module includes a first inverting unit, a second inverting unit, a first capacitor, a second capacitor and an XOR logic unit;
[0011] The input end of the first inverting unit is connected to the first filtering module, and the output end is connected to the first capacitor and the second inverting unit;
[0012] The input end of the second inverting unit is connected to the first inverting unit, and the output end is connected to the second capacitor and the XOR logic unit respectively;
[0013] The first input end of the XOR logic unit is connected to the first filtering module, the second input end is connected to the second inverting unit, and the output end is connected to the combinational logic module;
[0014] A first end of the first capacitor is connected to the first inverting unit, and a second end thereof is grounded;
[0015] A first end of the second capacitor is connected to the second inverting unit, and a second end of the second capacitor is grounded.
[0016] In some embodiments, the second filtering module further includes:
[0017] The first buffer module has an input end connected to the second inverting unit and an output end connected to the XOR logic unit, and is used for shaping the output signal of the second inverting unit and outputting it to the XOR logic unit.
[0018] In some embodiments, the combinational logic module includes an AND logic unit, a third inverting unit, a first transistor, a second transistor, a third transistor, and a fourth transistor;
[0019] The first input end of the AND logic unit is connected to the first filter module, and the second input end is connected to the second filter module; the output end is connected to the third inverting unit and the fourth transistor respectively;
[0020] The input end of the third inverting unit is connected to the AND logic unit, and the output end is connected to the third transistor;
[0021] The control end of the first transistor is connected to the control end of the second transistor and is connected to the second filtering module; the first end of the first transistor is connected to the second end of the second transistor to output the fourth signal, the second end of the first transistor is connected to the third transistor, and the first end of the second transistor is connected to the fourth transistor;
[0022] The control end of the third transistor is connected to the third inverting unit, the first end is connected to the first transistor, and the second end is used to connect to a power source;
[0023] The control end of the fourth transistor is connected to the AND logic unit, the first end is grounded, and the second end is connected to the second transistor.
[0024] In some embodiments, the combinational logic module further includes:
[0025] The second buffer module has an input end respectively connected to the first end of the first transistor and the second end of the second transistor to receive the fourth signal, and an output end for shaping and outputting the fourth signal.
[0026] In some embodiments, the clock detection circuit provided by the present application further includes:
[0027] The first frequency dividing module has an input end for receiving the first clock and an output end connected to the first filtering module to divide the first clock into a clock signal with a duty cycle of 50% and output it to the first filtering module.
[0028] In some embodiments, the clock detection circuit provided by the present application further includes:
[0029] The second frequency division module has an input end connected to the first filtering module and an output end connected to the second filtering module and the combinational logic module respectively, and is used to divide the second signal into a clock signal with a duty cycle of 50% and output it to the second filtering module and the combinational logic module.
[0030] In some embodiments, the clock detection circuit provided by the present application further includes:
[0031] The third frequency division module has an input end connected to the second filtering module and an output end connected to the combinational logic module, and is used for dividing the third signal into a clock signal with a duty cycle of 50% and outputting it to the combinational logic module.
[0032] In a second aspect, the present application also provides a chip, comprising the clock detection circuit of the first aspect mentioned above.
[0033] The clock detection circuit and chip provided in the present application are used to detect the frequency of the input clock. Taking the input clock as the first clock as an example, when the frequency of the first clock is not higher than the first reference frequency and not lower than the second reference frequency, the first filter module receives the first clock and outputs the second signal identical to the first clock, the second filter module receives the second signal and outputs the third signal identical to the first clock, the combination logic module receives the second signal and the third signal, and outputs the fourth signal identical to the first clock through combination logic processing, that is, when the frequency of the first clock is between the second reference frequency and the first reference frequency, the first clock can pass through the first filter module, the second filter module and the combination logic module without distortion. When the frequency of the first clock is not between the second reference frequency and the first reference frequency, the first clock will be filtered into a level signal by the first filter module or the second filter module, that is, the second signal and the third signal received by the combination logic module include at least one level signal, and the combination logic module is designed to output a level signal when the input signal has a level signal, indicating that the first clock is not within the passband range specified by the circuit (from the second reference frequency to the first reference frequency). The clock detection circuit provided in the present application can pass the clock detection circuit only when the frequency of the input clock is within the passband range specified by the circuit. Otherwise, the clock detection circuit outputs a level signal indicating that the first clock is abnormal, thereby realizing the detection of the input clock and solving the problem of circuit abnormality caused by large input clock deviation.
[0034] These and other aspects of the present application will become more apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0036] Figure 1 A module schematic diagram of a clock detection circuit provided in an embodiment of the present application is shown.
[0037] Figure 2 A schematic structural diagram of an active low-pass filter unit provided in an embodiment of the present application is shown.
[0038] Figure 3 A schematic diagram of the structure of the second filtering module provided in an embodiment of the present application is shown.
[0039] Figure 4 Another structural schematic diagram of the second filtering module provided in an embodiment of the present application is shown.
[0040] Figure 5 A schematic diagram of the structure of a combinational logic module provided in an embodiment of the present application is shown.
[0041] Figure 6 Another structural schematic diagram of the combinational logic module provided in an embodiment of the present application is shown.
[0042] Figure 7 Another module schematic diagram of the clock detection circuit provided in an embodiment of the present application is shown.
[0043] Figure 8 Another module schematic diagram of the clock detection circuit provided in an embodiment of the present application is shown.
[0044] Fig. 9 Another module schematic diagram of the clock detection circuit provided in an embodiment of the present application is shown.
[0045] Fig.10 A frequency timing diagram of a clock detection circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0046] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.
[0047] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0048] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.
[0049] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.
[0050] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.
[0051] The first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain.
[0052] The embodiment of the present application provides a clock detection circuit. Figure 1 FIG. 4 shows a schematic diagram of a module of a clock detection circuit provided by an embodiment of the present application. Figure 1 As shown, the clock detection circuit includes:
[0053] The first filtering module 100 is used to receive a first clock, filter the first clock according to a first reference frequency and output a second signal. When the frequency of the first clock is higher than the first reference frequency, the second signal is one of a high level or a low level, otherwise the second signal is the same as the first clock.
[0054] The second filtering module 200 is used to receive the second signal, filter the second signal according to the second reference frequency and output a third signal. When the frequency of the second signal is lower than the second reference frequency, the third signal is one of a high level or a low level. Otherwise, the third signal is the same as the first clock.
[0055] The combinational logic module 300 is used to receive the second signal and the third signal, perform combinational logic processing on the second signal and the third signal to output a fourth signal. When the second signal and the third signal are the same as the first clock, the fourth signal is also the same as the first clock. Otherwise, the fourth signal is one of a high level or a low level.
[0056] Among them, the first reference frequency is the characteristic frequency of the first filtering module, the second reference frequency is the characteristic frequency of the second filtering module, and the first reference frequency is higher than the second reference frequency, that is, the second reference frequency to the first reference frequency is the passband range of the clock detection circuit.
[0057] Specifically, the clock detection circuit provided by the embodiment of the present application assumes a first reference frequency F1, a second reference frequency F2, and a frequency of the first clock F0. For F2≤F0≤F1, the first clock is output without distortion through the first filtering module and the second filtering module, that is, the second signal output by the first filtering module is the same as the first clock, and the third signal output by the second filtering module is the same as the first clock. The combination logic module performs a combination logic process on the second signal and the third signal to output a fourth signal that is the same as the first clock. For F0>F1, the first filtering module receives the first clock, filters the first clock into a level signal and outputs it, and the second filtering module receives the level signal and also outputs the level signal, that is, at this time, the second signal and the third signal are both level signals, and the combination logic module performs a combination logic process on the second signal and the third signal and still outputs a level signal. For F0<F2, the first clock is output without distortion through the first filtering module, that is, the second signal is the same as the first clock, and the second filtering module filters the second signal into a level signal, that is, the third signal is a level signal, and the combination logic module performs a combination logic process on the second signal and the third signal to output a level signal.
[0058] The clock detection circuit provided in the embodiment of the present application can pass the clock detection circuit only when the frequency of the input clock is within the passband range (F2-F1) specified by the circuit. Otherwise, the clock detection circuit outputs a level signal to indicate that the input clock is abnormal, thereby realizing the detection of the input clock and solving the problem of circuit abnormality caused by large input clock deviation.
[0059] In one example, the clock detection circuit provided in the embodiment of the present application is applied to a functional module with a clock, and the level signal output by the clock detection circuit is used as an interrupt signal, that is, after the clock detection circuit outputs the level signal, the level signal will cause the functional module to be interrupted. In another example, the level signal output by the clock detection circuit is also used as an alarm signal, that is, after the clock detection circuit outputs the level signal, the level signal will trigger a module that can be used for alarm, such as an indicator light / sound device, on the functional module.
[0060] In some embodiments, the first filtering module 100 provided in the embodiments of the present application includes an active low-pass filtering unit.
[0061] As an implementation manner, the first filtering module may select an active low-pass filter; as another implementation manner, the first filtering module may select an active low-pass filtering circuit composed of a resistor, a capacitor and an operational amplifier.
[0062] In one example, Figure 2 FIG. 4 shows a schematic diagram of the structure of an active low-pass filter unit provided in an embodiment of the present application. Figure 2 As shown, the active low-pass filter unit includes a first resistor R1, a second resistor R2, a third resistor R3, a third capacitor C3, a fourth capacitor C4 and an operational amplifier OPAMP.
[0063] Wherein, the first end of the first resistor and the first end of the third capacitor are both connected to the non-inverting input terminal of the operational amplifier, the second end of the first resistor is connected to the circuit / module that outputs the first clock, and the second end of the third capacitor is grounded. The second resistor and the fourth capacitor are connected in parallel and connected to the inverting input terminal and the output terminal of the operational amplifier. The third resistor and the second resistor are connected in series and grounded. The output terminal of the operational amplifier is used to output the second signal.
[0064] Understandably, Figure 2 Only a schematic diagram of the structure of an active low-pass filter unit is shown, but it does not mean that the structure of the first filter module provided in the embodiment of the present application is limited to the following. Figure 2 The active low-pass filter unit shown.
[0065] In some embodiments, Figure 3 FIG. 4 shows a schematic diagram of the structure of the second filtering module provided in an embodiment of the present application. Figure 3 As shown, the second filtering module 200 includes a first inverting unit 210 , a second inverting unit 220 , a first capacitor C1 , a second capacitor C2 and an XOR logic unit 230 .
[0066] The input end of the first inverting unit is connected to the first filtering module to receive the second signal, and the output end is connected to the first capacitor and the second inverting unit.
[0067] The input end of the second inverting unit is connected to the first inverting unit, and the output end is connected to the second capacitor and the XOR logic unit respectively.
[0068] The first input end of the XOR logic unit is connected to the first filtering module to receive the second signal, the second input end is connected to the second inverting unit to receive the output signal of the second inverting unit, and the output end is connected to the combinational logic module.
[0069] The first end of the first capacitor is connected to the first inverting unit, and the second end is grounded.
[0070] A first end of the second capacitor is connected to the second inverting unit, and a second end thereof is grounded.
[0071] In some embodiments, the clock detection circuit provided in the embodiments of the present application is used to detect a high-speed clock, such as Figure 3As shown, the first inverting unit and the second inverting unit are both current limiting inverters composed of MOS tubes, so as to achieve filtering of high-speed signals. Specifically, the current limiting inverter includes a PMOS tube and an NMOS tube, the gates of the PMOS tube and the NMOS tube are connected as input ends, the drains are connected as output ends, the source of the PMOS tube is connected to the power supply, and the source of the NMOS tube is grounded.
[0072] In some embodiments, the clock detection circuit provided in the embodiments of the present application is used to detect a high-speed clock, and the XOR logic unit is an XOR logic circuit composed of a transmission gate structure, thereby enabling XOR operations on high-speed signals.
[0073] In some embodiments, Figure 4 Another structural schematic diagram of the second filtering module provided in the embodiment of the present application is shown in FIG. Figure 4 As shown, the second filtering module 200 also includes:
[0074] The first buffer module 240 is arranged between the second inverting unit and the XOR logic unit, the input end of the first buffer module is connected to the output end of the second inverting unit, the output end of the first buffer module is connected to the second input end of the XOR logic unit, and the first buffer module is used to shape the output signal of the second inverting unit and then output it to the XOR logic unit.
[0075] In some embodiments, the clock detection circuit provided in the embodiments of the present application is used to detect a high-speed clock, such as Figure 4 As shown, the embodiment of the present application implements the first buffer module by connecting two current-limiting inverters in series, thereby achieving the shaping output of the high-speed signal.
[0076] The clock detection circuit provided in the embodiment of the present application is provided with a first buffer module to shape the signal output by the second inverting unit to remove the burrs on the output signal of the second inverting unit.
[0077] In some embodiments, Figure 5 The schematic diagram of the structure of the combinational logic module provided in the embodiment of the present application is shown as follows: Figure 5 As shown, the combinational logic module 300 includes an AND logic unit 310, a third inverting unit 320, a first transistor Q1, a second transistor Q2, a third transistor Q3 and a fourth transistor Q4.
[0078] The first input end of the AND logic unit is connected to the first filter module to receive the second signal, and the second input end is connected to the second filter module to receive the third signal; the output end is respectively connected to the third inverting unit and the fourth transistor, and is used to perform an AND operation on the second signal and the third signal and output them to the third inverting unit and the fourth transistor.
[0079] The input end of the third inverting unit is connected to the AND logic unit, and the output end is connected to the third transistor, and is used for inverting the output signal of the AND logic unit and outputting it to the third transistor.
[0080] The control end of the first transistor is connected to the control end of the second transistor, and is connected to the second filter module; the first end of the first transistor is connected to the second end of the second transistor to output a fourth signal, the second end of the first transistor is connected to the third transistor, and the first end of the second transistor is connected to the fourth transistor. Specifically, the first transistor and the second transistor form a current limiting inverter, the control ends of the first transistor and the second transistor are connected as the input end of the current limiting inverter, the drain ends are connected as the output end of the current limiting inverter, the source of the first transistor is connected to the power supply (in the embodiment of the present application, connected to the power supply via the third transistor), and the source of the second transistor is grounded (in the embodiment of the present application, grounded via the fourth transistor).
[0081] The control end of the third transistor is connected to the third inverting unit, the first end is connected to the first transistor, and the second end is used to connect to the power supply.
[0082] The control end of the fourth transistor is connected to the AND logic unit, the first end is used for grounding, and the second end is connected to the second transistor.
[0083] Specifically, in the embodiment of the present application, the first transistor, the second transistor, the third transistor and the fourth transistor form a three-state gate structure, and the three-state gate structure and the AND logic unit and the third inverting unit realize a combinational logic operation.
[0084] As an implementation manner, in the embodiment of the present application, the first transistor and the third transistor are PMOS transistors, the second transistor and the fourth transistor are NMOS transistors, the control end of each transistor is the gate of each transistor, the first end of the first transistor and the third transistor is the drain, the second end of the first transistor and the third transistor is the source, the first end of the second transistor and the fourth transistor is the source, and the second end of the second transistor and the fourth transistor is the drain.
[0085] In some embodiments, the clock detection circuit provided in the embodiments of the present application is used to detect a high-speed clock, and the AND logic unit is an AND logic circuit composed of a transmission gate structure, thereby enabling AND operations on high-speed signals.
[0086] In some embodiments, Figure 6 Another structural diagram of the combinational logic module provided in the embodiment of the present application is shown in FIG. Figure 6 As shown, the combinational logic module 300 further includes:
[0087] The second buffer module 330 has its input end connected to the first end of the first transistor and the second end of the second transistor to receive a fourth signal, and its output end is an output port of the combinational logic module. The second buffer module is used to shape and output the fourth signal.
[0088] In some embodiments, the clock detection circuit provided in the embodiments of the present application is used to detect a high-speed clock, such as Figure 6 As shown, the embodiment of the present application implements the first buffer module by connecting two current-limiting inverters in series, thereby achieving the shaping output of the high-speed signal.
[0089] The clock detection circuit provided in the embodiment of the present application is provided with a second buffer module to shape the fourth signal to remove burrs on the fourth signal.
[0090] In some embodiments, Figure 7 Another module schematic diagram of the clock detection circuit provided in the embodiment of the present application is shown, such as Figure 7 As shown, the clock detection circuit provided in the embodiment of the present application also includes:
[0091] The first frequency dividing module 400 has an input end for receiving a first clock, and an output end connected to the first filtering module to divide the first clock into a clock signal with a duty cycle of 50% and output it to the first filtering module.
[0092] Optionally, the clock detection circuit provided in the embodiment of the present application implements the first frequency division module through a D flip-flop. Specifically, the data input terminal (i.e., the D terminal) and the inverting output terminal (i.e., the Q' terminal) of the D flip-flop are connected, and the clock terminal (i.e., the clk terminal) is connected to an external circuit, which is used to provide a first clock to the clock detection circuit. The output terminal (i.e., the Q terminal) is connected to the input terminal of the first filtering module. At this time, the D flip-flop divides the received first clock into a clock signal with a duty cycle of 50% and outputs it to the first filtering module.
[0093] The clock detection circuit provided in the embodiment of the present application sets a first frequency division module to divide the first clock into a clock signal with a duty cycle of 50%, thereby avoiding the problem that the first filtering module cannot completely filter the first clock.
[0094] In some embodiments, Figure 8 Another module schematic diagram of the clock detection circuit provided in the embodiment of the present application is shown. Figure 8 As shown, the clock detection circuit provided in the embodiment of the present application also includes:
[0095] The second frequency division module 500 has an input end connected to the first filter module, and an output end connected to the second filter module and the combinational logic module, respectively, for dividing the second signal into a clock signal with a duty cycle of 50% and outputting it to the second filter module and the combinational logic module. Optionally, when the second signal is a level signal, it is still a level signal after passing through the second frequency division module.
[0096] Optionally, the clock detection circuit provided in the embodiment of the present application implements the second frequency division module through a D flip-flop. Specifically, the data input terminal (i.e., the D terminal) and the inverting output terminal (i.e., the Q' terminal) of the D flip-flop are connected, the clock terminal (i.e., the clk terminal) is connected to the output terminal of the first filtering module to receive the second signal, and the output terminal (i.e., the Q terminal) is connected to an input terminal of the second filtering module and the combinational logic module. At this time, the D flip-flop divides the received second signal into a clock signal with a duty cycle of 50% and outputs it to the second filtering module and the combinational logic module.
[0097] The clock detection circuit provided in the embodiment of the present application is provided with a second frequency division module to divide the second signal into a clock signal with a duty cycle of 50%, thereby avoiding the problem that the second filtering module cannot completely filter the second signal.
[0098] In some embodiments, Fig. 9 Another module schematic diagram of the clock detection circuit provided in the embodiment of the present application is shown. Fig. 9 As shown, the clock detection circuit provided in the embodiment of the present application also includes:
[0099] The third frequency division module 600 has an input end connected to the second filtering module and an output end connected to the combinational logic module, and is used to divide the third signal into a clock signal with a duty cycle of 50% and output it to the combinational logic module. Optionally, when the third signal is a level signal, it is still a level signal after passing through the third frequency division module.
[0100] Optionally, the clock detection circuit provided in the embodiment of the present application implements the third frequency division module through a D flip-flop. Specifically, the data input terminal (i.e., the D terminal) and the inverting output terminal (i.e., the Q' terminal) of the D flip-flop are connected, the clock terminal (i.e., the clk terminal) is connected to the output terminal of the second filtering module to receive the third signal, and the output terminal (i.e., the Q terminal) is connected to another input terminal of the combinational logic module. At this time, the D flip-flop divides the received fourth signal into a clock signal with a duty cycle of 50% and outputs it to the combinational logic module.
[0101] The clock detection circuit provided in the embodiment of the present application sets a second frequency division module to divide the third signal into a clock signal with a duty cycle of 50%, thereby avoiding the problem that the first filtering module cannot completely filter the third signal.
[0102] Fig.10 FIG. 4 shows a frequency timing diagram of a clock detection circuit provided in an embodiment of the present application. Fig.10 As shown, the first reference frequency is F1, the second reference frequency is F2, the first filter module can only pass the clock signal whose frequency does not exceed the first reference frequency F1 (the frequency is higher than the first reference frequency F1 and the output level signal), and the second filter module can only pass the clock signal whose frequency is not less than the second reference frequency F2 (the frequency is lower than the second reference frequency and the output level signal), then the combinational logic module performs combinational logic processing on the outputs of the first filter module and the second filter module, and can only pass the clock signal whose frequency is between the second reference frequency F2 and the first reference frequency F1.
[0103] The clock detection circuit provided in the embodiment of the present application can pass the input clock through the clock detection circuit only when the frequency of the input clock is within the passband range (F2-F1) specified by the circuit. Otherwise, the clock detection circuit will output a level signal to indicate the abnormal state of the input clock, thereby realizing the detection of the input clock and solving the problem of circuit abnormality caused by large input clock deviation.
[0104] The embodiment of the present application also provides a chip, which includes the above-mentioned clock detection circuit. A chip (Integrated Circuit, IC) is also called a chip, and the chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip.
[0105] An embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above disposed in the device body.
[0106] The above contents are further detailed descriptions of the present application in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be regarded as the protection scope of the present application.
Claims
1. A clock detection circuit, characterized in that: include: A first filtering module, configured to receive a first clock, filter the first clock according to a first reference frequency and output a second signal, wherein when the frequency of the first clock is higher than the first reference frequency, the second signal is at a high level or a low level, otherwise the second signal is the same as the first clock; a second filtering module, configured to receive the second signal, filter the second signal according to a second reference frequency and output a third signal, wherein when the frequency of the second signal is lower than the second reference frequency, the third signal is the high level or the low level, otherwise the third signal is the same as the first clock; a combinational logic module, configured to receive the second signal and the third signal, perform combinational logic processing on the second signal and the third signal and output a fourth signal, wherein when the second signal and the third signal are the same as the first clock, the fourth signal is the same as the first clock, otherwise the fourth signal is the high level or the low level; The first reference frequency is a characteristic frequency of the first filtering module, the second reference frequency is a characteristic frequency of the second filtering module, and the first reference frequency is higher than the second reference frequency.
2. The clock detection circuit according to claim 1, characterized in that: The first filtering module includes an active low-pass filtering unit.
3. The clock detection circuit according to claim 1, characterized in that: The second filtering module includes a first inverting unit, a second inverting unit, a first capacitor, a second capacitor and an XOR logic unit; The input end of the first inverting unit is connected to the first filtering module, and the output end is connected to the first capacitor and the second inverting unit; The input end of the second inverting unit is connected to the first inverting unit, and the output end is connected to the second capacitor and the XOR logic unit respectively; The first input end of the XOR logic unit is connected to the first filtering module, the second input end is connected to the second inverting unit, and the output end is connected to the combinational logic module; A first end of the first capacitor is connected to the first inverting unit, and a second end thereof is grounded; A first end of the second capacitor is connected to the second inverting unit, and a second end of the second capacitor is grounded.
4. The clock detection circuit according to claim 3, characterized in that: The second filtering module also includes: The first buffer module has an input end connected to the second inverting unit and an output end connected to the XOR logic unit, and is used for shaping the output signal of the second inverting unit and outputting it to the XOR logic unit.
5. The clock detection circuit according to claim 1, characterized in that: The combinational logic module includes an AND logic unit, a third inverting unit, a first transistor, a second transistor, a third transistor and a fourth transistor; The first input end of the AND logic unit is connected to the first filter module, and the second input end is connected to the second filter module; the output end is connected to the third inverting unit and the fourth transistor respectively; The input end of the third inverting unit is connected to the AND logic unit, and the output end is connected to the third transistor; The control end of the first transistor is connected to the control end of the second transistor and is connected to the second filtering module; the first end of the first transistor is connected to the second end of the second transistor to output the fourth signal, the second end of the first transistor is connected to the third transistor, and the first end of the second transistor is connected to the fourth transistor; The control end of the third transistor is connected to the third inverting unit, the first end is connected to the first transistor, and the second end is used to connect to a power source; The control end of the fourth transistor is connected to the AND logic unit, the first end is grounded, and the second end is connected to the second transistor.
6. The clock detection circuit according to claim 5, characterized in that: The combinational logic module also includes: The second buffer module has an input end respectively connected to the first end of the first transistor and the second end of the second transistor to receive the fourth signal, and an output end for shaping and outputting the fourth signal.
7. The clock detection circuit according to claim 1, characterized in that: Also includes; The first frequency dividing module has an input end for receiving the first clock and an output end connected to the first filtering module to divide the first clock into a clock signal with a duty cycle of 50% and output it to the first filtering module.
8. The clock detection circuit according to claim 1, characterized in that: Also includes: The second frequency division module has an input end connected to the first filtering module and an output end connected to the second filtering module and the combinational logic module respectively, and is used to divide the second signal into a clock signal with a duty cycle of 50% and output it to the second filtering module and the combinational logic module.
9. The clock detection circuit according to claim 1, characterized in that: Also includes: The third frequency division module has an input end connected to the second filtering module and an output end connected to the combinational logic module, and is used for dividing the third signal into a clock signal with a duty cycle of 50% and outputting it to the combinational logic module.
10. A chip, characterized in that: The clock detection circuit comprises any one of claims 1 to 9.