Offset voltage calibration method and circuit and assembly line successive approximation analog-to-digital converter

Abstract

The invention provides an offset voltage calibration method and circuit and an assembly line successive approximation type analog-to-digital converter, and belongs to the field of integrated circuits. The method comprises the following steps: sampling an input signal through a capacitor array to obtain a sampling signal; detecting the size of a residual signal of the input end after the amplifier amplifies the sampling signal, and determining the size and direction of the offset voltage of the amplifier; the magnitude and direction of the offset voltage of the comparator are adjusted according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier; difference comparison is carried out on the offset voltage of the comparator and the offset voltage of the amplifier, so that the offset voltage of the comparator counteracts the offset voltage of the amplifier, and the equivalent offset voltage of the whole stage circuit is zero. The method is easy to implement and high in calibration precision, and calibration of the comparator and the amplifier is achieved at the same time.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to an offset voltage calibration method, an offset voltage calibration circuit, and a pipeline successive approximation analog-to-digital converter. Background Art

[0002] The pipeline ADC reduces the quantization accuracy of each level through multiple quantization. A common circuit structure of a pipeline ADC is as follows: Figure 1 As shown in the figure. The pipeline structure of Pipeline ADC consists of an input sampling and holding stage circuit and multiple stage circuits. The stage circuit consists of a sub-analog-to-digital converter (sub ADC) and a residual gain unit (MDAC). The signal quantization is completed by the sub ADC, and the signal amplification is completed by the MDAC. During the conversion process, the stage circuits work alternately in a pipeline form. The sampling period is usually half a clock cycle. The stage circuit samples the output of the previous stage circuit. Within half a clock cycle, the stage circuit completes the quantization and amplification of the signal. Finally, the quantized data of each stage is aligned through multi-stage registers.

[0003] Compared with the successive approximation analog-to-digital converter (SAR ADC), the Pipeline ADC can achieve faster conversion speeds, but there are amplifiers in each sub-stage circuit. Usually, the amplifier is the module with the highest power consumption in the entire circuit, so the power consumption of the Pipeline ADC is much greater than that of the SAR ADC. For high-performance Pipeline ADC, it is usually hoped that the first-stage resolution is higher, the inter-stage gain is higher, and the noise and nonlinearity of the subsequent stage are greatly attenuated; at the same time, the increase in the resolution of the first stage can reduce the resolution of the subsequent stage, so the number of pipeline stages decreases and the power consumption is reduced. In the pipeline structure, the sub ADC usually adopts the FLASH ADC structure. Due to the limitations of the FLASH ADC structure itself, the quantization accuracy of the stage circuit is difficult to exceed 4 bits.

[0004] The pipeline-SAR ADC combines the characteristics of the pipeline ADC and SAR ADC structures, adopts a pipeline architecture, and uses a SAR ADC as the quantizer. A common two-stage pipeline-SAR ADC structure is shown in Figure 1. Figure 2As shown in the figure. Since the first-stage quantizer (Stage1) adopts the structure of SAR ADC, the quantization accuracy is higher than the FLASH in the Pipeline ADC sub-stage circuit, so the inter-stage gain is high. The comparator noise of the second stage is greatly attenuated, thus solving the problem that the high-precision SAR ADC comparator noise is difficult to reduce. At the same time, the number of pipeline stage circuits decreases, and the overall power consumption also decreases. Since the quantizer adopts SAR ADC, the quantization speed of Pipeline-SAR ADC is slower than that of Pipeline ADC, but it is still faster than SAR ADC. Due to the high inter-stage gain, the input offset voltage of the first-stage comparator and amplifier will cause the output of the amplifier to exceed the design limit.

[0005] The offset sources of the Pipeline-SAR ADC circuit are the offset voltage of the comparator and the offset voltage of the amplifier. In the Pipeline-SAR ADC, the resolution of each circuit is high, and the corresponding inter-stage gain is also high. Therefore, the offset voltage of the comparator and amplifier needs to be calibrated to ensure the normal operation of the circuit. Summary of the invention

[0006] The invention provides an offset voltage calibration method, an offset voltage calibration circuit and a pipeline successive approximation analog-to-digital converter, which realize the offset voltage calibration of a comparator and an amplifier.

[0007] A first aspect of the present invention provides an offset voltage calibration method, which is applied to various stages of an analog-to-digital converter, wherein the previous stage of the circuit is connected to the next stage of the circuit through an amplifier, and each stage of the circuit includes a capacitor array and a comparator, and the output end of the capacitor array is connected to the negative input end of the comparator and the reverse input end of the amplifier. The method includes:

[0008] The input signal is sampled by a capacitor array to obtain a sampling signal;

[0009] Detecting the magnitude of the residual signal at the input end after the amplifier amplifies the sampling signal, and determining the magnitude and direction of the amplifier's offset voltage;

[0010] Adjusting the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier;

[0011] The offset voltage of the comparator is compared with the offset voltage of the amplifier, so that the offset voltage of the comparator cancels the offset voltage of the amplifier, so that the equivalent offset voltage of the entire stage circuit is zero.

[0012] In an embodiment of the present invention, adjusting the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier includes:

[0013] If the amplifier has an offset voltage in the positive direction, and the comparator has an offset voltage in the negative direction at this time, the offset voltage in the negative direction of the comparator is adjusted to the positive direction through the calibration logic until the offset voltage of the comparator is in the positive direction, and the magnitude of the offset voltage in the positive direction of the comparator is equal to the magnitude of the offset voltage in the positive direction of the amplifier;

[0014] If the amplifier has an offset voltage in the positive direction, and the comparator has an offset voltage in the positive direction at this time, the offset voltage in the positive direction of the comparator is adjusted to be equal to the offset voltage in the positive direction of the amplifier through the calibration logic;

[0015] If the amplifier has a positive offset voltage and the comparator does not have an offset voltage at this time, the comparator is made to present a positive offset voltage through calibration logic, and the positive offset voltage of the comparator is adjusted to be equal to the magnitude of the positive offset voltage of the amplifier.

[0016] In the embodiment of the present invention, the in-direction input terminal and the inverting input terminal of the amplifier are connected via a first conversion switch, the output terminal of the amplifier is connected to the next stage circuit via a second conversion switch, and the inverting input terminal of the amplifier is grounded via a reset switch.

[0017] In the embodiment of the present invention, when sampling is finished, the first conversion switch is turned off, the sampled signal is quantized, and the signal chain of the amplifier is established using the quantized sampled signal.

[0018] At the end of quantization, the reset switch is opened to transfer the sampled signal on the capacitor array to the amplifier, thus establishing the amplifier signal chain.

[0019] After the amplifier signal chain is established, the sampling of the rear-stage circuit is completed, the second conversion switch is disconnected, and a calibration pulse signal is sent to the comparator, triggering the comparator to perform a comparison operation.

[0020] A second aspect of the present invention provides an offset voltage calibration circuit, comprising a capacitor array, a comparator and an amplifier, wherein the output end of the capacitor array is connected to the negative input end of the comparator and the reverse input end of the amplifier, and the comparator comprises an offset voltage adjustment circuit;

[0021] The capacitor array samples the input signal to obtain a sampling signal;

[0022] The amplifier uses the quantized sampled signal to establish a signal chain of the amplifier;

[0023] The offset voltage adjustment circuit is used to adjust the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier;

[0024] The comparator performs a comparison operation under the triggering of the calibration pulse signal, and uses the offset voltage of the comparator to offset the offset voltage of the amplifier, so that the overall equivalent offset voltage is zero.

[0025] In the embodiment of the present invention, the non-inverting input terminal and the reverse input terminal of the amplifier are connected via a first conversion switch, the output terminal of the amplifier is connected to the next stage circuit via a second conversion switch, and the reverse input terminal of the amplifier is grounded via a reset switch.

[0026] When the capacitor array sampling is finished, the first conversion switch is disconnected;

[0027] After the reset switch is opened, the amplifier establishes a signal chain;

[0028] After the second conversion switch is turned off, a calibration pulse signal is sent to the comparator to trigger the comparator to perform a comparison operation.

[0029] In an embodiment of the present invention, the offset voltage adjustment circuit includes: a pre-amplifier input tube, a charge pump, and a pair of auxiliary input tubes. The pre-amplifier input tube inputs a differential signal, and the auxiliary input tube is connected to the charge pump.

[0030] In an embodiment of the present invention, the pre-amplification stage input tube includes: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, and a fifth MOS tube, the gate of the first MOS tube, the gate of the fourth MOS tube, and the gate of the fifth MOS tube are connected to a calibration pulse signal, the drain of the first MOS tube is connected to the source of the second MOS tube and the source of the third MOS tube, the gate of the second MOS tube is connected to a differential positive analog input voltage, and the gate of the third MOS tube is connected to a differential negative analog input voltage; the drain of the second MOS tube is connected to the drain of the fourth MOS tube, the drain of the third MOS tube is connected to the drain of the fifth MOS tube, and the source of the fourth MOS tube and the source of the fifth MOS tube are connected to a power supply voltage.

[0031] The auxiliary input tubes include: a sixth MOS tube, a seventh MOS tube, and an eighth MOS tube. The gate of the sixth MOS tube is connected to the common mode voltage through a third conversion switch, the gate of the seventh MOS tube is connected to the charge pump through a fourth conversion switch, the drain of the eighth MOS tube is connected to the source of the sixth MOS tube and the source of the seventh MOS tube, the drain of the sixth MOS tube M6 is connected to the drain of the fourth MOS tube M4, and the drain of the seventh MOS tube M7 is connected to the drain of the fifth MOS tube M5.

[0032] A third aspect of the present invention provides a pipeline successive approximation analog-to-digital converter, comprising a plurality of stage circuits, wherein the previous stage circuit in each stage circuit is connected to the next stage circuit through an amplifier, each stage circuit comprises a capacitor array and a comparator, the output end of the capacitor array is connected to the negative input end of the comparator and the reverse input end of the amplifier, and the comparator comprises an offset voltage adjustment circuit;

[0033] The capacitor array samples the input signal to obtain a sampling signal;

[0034] The amplifier uses the quantized sampled signal to establish a signal chain of the amplifier;

[0035] The offset voltage adjustment circuit is used to adjust the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier;

[0036] The comparator performs a comparison operation under the triggering of the calibration pulse signal, and uses the offset voltage of the comparator to offset the offset voltage of the amplifier, so that the overall equivalent offset voltage is zero.

[0037] In the embodiment of the present invention, the in-direction input terminal and the inverting input terminal of the amplifier are connected via a first conversion switch, the output terminal of the amplifier is connected to the next stage circuit via a second conversion switch, and the inverting input terminal of the amplifier is grounded via a reset switch.

[0038] In an embodiment of the present invention, the offset voltage adjustment circuit includes: a pre-amplifier input tube, a charge pump, and a pair of auxiliary input tubes. The pre-amplifier input tube inputs a differential signal, and the auxiliary input tube is connected to the charge pump.

[0039] The present invention provides an analog domain offset voltage calibration scheme for an amplifier comparator based on a virtual short circuit of an amplifier. A set of timing controls is added on the basis of the original stage circuit, and a pair of auxiliary input tubes are added to the comparator. By detecting the size of the residual signal at the input end after the amplifier amplification is completed, the offset voltage of the amplifier is offset by the offset voltage of the comparator, so that the equivalent offset voltage is zero, thereby achieving offset voltage calibration. The present invention is simple to implement and has high calibration accuracy, and calibration of the comparator and the amplifier is achieved at the same time. The present invention implements calibration in the analog domain, the output voltage of the amplifier is not affected by the offset voltage, the background can track the offset voltage in real time, and the convergence speed is fast. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0041] Figure 1 It is a structural schematic diagram of an existing pipeline analog-to-digital converter (Pipeline ADC);

[0042] Figure 2 It is a structural schematic diagram of an existing pipeline-successive approximation analog-to-digital converter (Pipeline-SAR ADC);

[0043] Figure 3 It is a structural schematic diagram of an existing Pipeline-SAR ADC level circuit with offset voltage;

[0044] Figure 4 yes Figure 3 Working timing diagram of intermediate circuit;

[0045] Figure 5 It is an existing offset calibration circuit based on detection output;

[0046] Figure 6 is a schematic diagram of the structure of an offset voltage calibration circuit provided by an embodiment of the present invention;

[0047] Figure 7 is a working timing diagram of the offset voltage calibration circuit provided by an embodiment of the present invention;

[0048] Figure 8 It is a structural schematic diagram of a pre-amplifier input tube in an offset voltage calibration circuit provided by an embodiment of the present invention;

[0049] Fig. 9 is a structural schematic diagram of an auxiliary input tube in an offset voltage calibration circuit provided by an embodiment of the present invention;

[0050] Fig.10 is a flow chart of an offset voltage calibration method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0052] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0053] In the present invention, unless otherwise clearly specified and limited, the terms such as "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0054] In the process of implementing the present invention, the inventors found that the offset source of the Pipeline-SAR ADC stage circuit is the offset voltage of the comparator and the offset voltage of the amplifier. Figure 3 As shown, V OS,CMP 、V OS,OTA They represent the offset voltage of the comparator CMP and the offset voltage of the operational amplifier OTA respectively. Figure 4 As shown, F1, F1E, and F2 are the working timing of the stage circuit. Using the charge conservation at the negative input of the amplifier, it can be deduced that the magnitude of the amplifier output offset voltage caused by the operational amplifier and comparator input offset voltage is:

[0055] 0=(V OS,OTA -V OS,CMP )C s +(V OS,OTA -V OUT )C F ;

[0056]

[0057] Derivation shows that the equivalent output offset voltage is approximately the product of the difference between the operational amplifier and comparator input offset voltages and the interstage gain.

[0058] In the Pipeline-SAR ADC, the resolution of each stage of the circuit is high, and the corresponding inter-stage gain is also high. Therefore, by calibrating the offset voltage of the comparator and amplifier, the normal operation of the circuit can be guaranteed.

[0059] The existing calibration scheme of the comparator in the SAR ADC circuit includes foreground calibration and background calibration. Foreground calibration includes: injecting compensation current and adjusting the pre-amplification load; background calibration includes: using auxiliary input tube to adjust the offset voltage. Figure 5 As shown, in an existing calibration scheme based on detecting the output signal swing of the rear stage and calibrating the offset of the front stage through feedback, due to the existence of inter-stage redundancy, taking 1-bit inter-stage redundancy as an example, in the absence of offset voltage, the maximum output signal swing of the rear stage is only half of the range. When it is detected that the high bits of the second-stage output are all 1 or all 0, it means that there is a large inter-stage offset at this time. The calibration method is to add a small calibration capacitor array to the sampling capacitor array of the first stage, and at each conversion, an offset voltage is added by injecting the charge into the calibration capacitor array to offset the inter-stage offset. In order to avoid frequently changing the injection mode of the calibration array, the detection circuit will only be started again when all 0 or all 1 occurs twice in a row. This method can realize the calibration of the comparator and the amplifier at the same time by detecting the output of the second stage, but due to the auxiliary work of digital circuits such as counters, the circuit design is relatively complicated.

[0060] In order to solve the defects of the prior art, the present invention proposes an analog domain offset voltage calibration scheme for amplifier comparator based on amplifier virtual short circuit. Since the offset voltage of the Pipeline-SAR ADC stage circuit mainly comes from the offset voltage of the comparator and the offset voltage of the amplifier. The present invention adds a set of timing control on the basis of the original stage circuit, and adds a pair of auxiliary input tubes in the comparator. By detecting the size of the residual signal at the input end after the amplifier amplification is completed, the offset voltage of the amplifier is offset by the offset voltage of the comparator, so that the equivalent offset voltage is zero, thereby realizing offset voltage calibration. The present invention is simple to implement and has high calibration accuracy, and realizes the calibration of the comparator and the amplifier at the same time. The present invention realizes calibration in the analog domain, the output voltage of the amplifier is not affected by the offset voltage, the background can track the offset voltage in real time, and the convergence speed is fast.

[0061] Figure 6 Schematic diagram of the structure of the offset voltage calibration circuit provided by the embodiment of the present invention. Figure 6As shown, this embodiment provides an offset voltage calibration circuit, including a capacitor array CDAC, a comparator COMP and an amplifier AMP, and Backend is a subsequent circuit. The output end of the capacitor array CDAC is connected to the negative input end of the comparator COMP and the reverse input end of the amplifier, and the positive input end of the comparator COMP is grounded; the same-direction input end and the reverse input end of the amplifier AMP are connected through a first conversion switch SA1, and the output end of the amplifier AMP is connected to the subsequent circuit Backend through a second conversion switch SA2, the same-direction input end of the amplifier AMP is grounded, and the reverse input end of the amplifier AMP is grounded through a reset switch RST, and the input end of the amplifier AMP is in a virtual short circuit state (the reverse input end and the same-direction input end voltage are equal).

[0062] In this embodiment, the capacitor array CDAC samples the input signal VIN to obtain a sampling signal. The amplifier AMP uses the quantized sampling signal to establish a signal chain of the amplifier. The comparator includes an offset voltage adjustment circuit, which adjusts the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier. The comparator COMP performs a comparison operation under the triggering of the calibration pulse signal, and uses the offset voltage of the comparator to offset the offset voltage of the amplifier, so that the overall equivalent offset voltage of the stage circuit is zero.

[0063] The present invention is based on the Pipeline-SAR ADC circuit, and adds Figure 7 Refer to the timing control shown in Figure 6 and Figure 7 , the specific process of offset voltage calibration is as follows: the capacitor array CDAC of the first-stage circuit (SAR ADC) samples the input signal; when the sampling is completed, the SA1 switch is disconnected and the SAR ADC starts quantization. For example, the first-stage SAR ADC controls a total of 6 sampling capacitors, and at this stage there are a total of six pulse signals (CLK) triggering the comparator. When the SAR ADC quantization is completed, the RST switch is disconnected, and due to the effect of negative feedback, the charge on the sampling capacitor begins to transfer, and the amplifier begins to establish a signal chain. When the signal chain of the amplifier AMP is basically established, the SA2 switch is disconnected, and the next-stage sampling is completed. When the signal chain of the amplifier AMP is fully established, the input voltage of the amplifier becomes 0, and the input of the amplifier is in a virtual short-circuit state. When the amplifier has an offset voltage, the voltage at the input of the amplifier is the offset voltage. At this time, the SAR ADC calibration logic triggers a calibration pulse signal (CAL) to the comparator COMP, triggering the comparator to perform a comparison operation. When the comparator COMP completes the comparison, the amplifier AMP is reset and the calibration is completed.

[0064] The offset voltage calibration principle of the present invention is: the magnitude and direction of the offset voltage of the comparator are adjusted according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier, and the offset voltage of the comparator is used to offset the offset voltage of the amplifier, so that the equivalent offset voltage of the entire stage circuit is zero. Specifically, if the amplifier has an offset voltage in the positive direction, and the comparator has an offset voltage in the negative direction at this time, the offset voltage in the negative direction of the comparator is adjusted to the positive direction through the calibration logic until the offset voltage of the comparator is in the positive direction, and the magnitude of the offset voltage in the positive direction of the comparator is equal to the magnitude of the offset voltage in the positive direction of the amplifier; if the amplifier has an offset voltage in the positive direction, and the comparator has an offset voltage in the positive direction at this time, the offset voltage in the positive direction of the comparator is adjusted to be equal to the magnitude of the offset voltage in the positive direction of the amplifier through the calibration logic; if the amplifier has an offset voltage in the positive direction, and the comparator does not have an offset voltage at this time, the comparator presents an offset voltage in the positive direction through the calibration logic, and gradually adjusts the offset voltage in the positive direction of the comparator to be equal to the magnitude of the offset voltage in the positive direction of the amplifier. Similarly, when the amplifier has an offset voltage in the negative direction, the offset voltage of the comparator is adjusted in the direction of the offset voltage of the amplifier.

[0065] For example, if the amplifier has a positive input offset voltage, the comparator has no offset voltage. The calibration pulse signal triggers the comparator. Since the comparator input voltage is the negative value of the amplifier offset voltage, the comparator output result is 0 (indicating that the two comparison objects of the comparator have the same size). Through the calibration logic, the comparator presents a positive offset voltage. After the SAR ADC quantization is completed, the residual voltage mean of the top plate of the capacitor converges to the offset voltage of the comparator. The offset voltage of the entire stage circuit is equivalent to the difference between the offset voltages of the comparator and the amplifier, so the offset voltage of the entire stage circuit decreases. After multiple cycles of calibration, the comparator is triggered by multiple calibration pulse signals, and the offset voltage of the stage circuit is basically 0. When calibration overshoot occurs, that is, the offset voltage of the comparator exceeds the offset voltage of the amplifier, when the calibration pulse signal arrives, the comparison result of the comparator is 1 (indicating that the two comparison objects of the comparator are not equal), the offset voltage of the comparator changes in the opposite direction, and the offset voltage of the stage circuit decreases. When the comparator and the amplifier have offset voltages at the same time, the offset voltage of the comparator is still adjusted in the direction of the amplifier offset voltage, and the offset voltage of the stage circuit eventually converges to 0.

[0066] The present invention adds the above-mentioned timing control on the basis of the stage circuit of Pipeline-SAR ADC, and adds a pair of auxiliary input tubes in the comparator. By detecting the size of the residual signal at the input end after the amplifier amplification is completed, the offset voltage of the amplifier is offset by the offset voltage of the comparator, so that the equivalent offset voltage is zero, thereby realizing the offset voltage calibration. The comparator in the offset voltage calibration circuit of the present invention includes a pre-amplifier stage input tube, a charge pump and a pair of auxiliary input tubes. The pre-amplifier stage input tube inputs a differential signal, and the auxiliary input tube is connected to the common mode voltage and the charge pump. The comparator inputs the data obtained from each calibration pulse signal into the charge pump, adjusts the input voltage of the auxiliary input tube, and plays a role in adjusting the offset voltage.

[0067] In a specific embodiment, if Figure 8 As shown, the pre-amplification stage input tube of the comparator in the offset voltage calibration circuit includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, and a fifth MOS tube M5. The gate of the first MOS tube M1, the gate of the fourth MOS tube M4, and the gate of the fifth MOS tube M5 are connected to the calibration pulse signal CLK, the drain of the first MOS tube M1 is connected to the source of the second MOS tube M2 and the source of the third MOS tube M3, the gate of the second MOS tube M2 is connected to the differential positive analog input voltage VIP, and the gate of the third MOS tube M3 is connected to the differential negative analog input voltage VIN; the drain of the second MOS tube M2 is connected to the drain of the fourth MOS tube M4, the drain of the third MOS tube M3 is connected to the drain of the fifth MOS tube M5, the source of the fourth MOS tube M4 and the source of the fifth MOS tube M5 are connected to the power supply voltage VDD, and the source of the first MOS tube M1 is grounded.

[0068] In a specific embodiment, if Fig. 9 As shown, the auxiliary input tubes of the comparator in the offset voltage calibration circuit include: a sixth MOS tube M6, a seventh MOS tube M7, and an eighth MOS tube M8. The gate of the sixth MOS tube M6 is connected to the common mode voltage VCM through the third conversion switch SA3, and the gate of the seventh MOS tube M7 is connected to the charge pump Charge Pump through the fourth conversion switch SA4. The gate of the eighth MOS tube M8 is connected to the reference voltage VB, the source of the eighth MOS tube M8 is grounded, the drain of the eighth MOS tube M8 is connected to the source of the sixth MOS tube M6 and the source of the seventh MOS tube M7, the drain of the sixth MOS tube M6 is connected to the drain (N terminal) of the fourth MOS tube M4, and the drain of the seventh MOS tube M7 is connected to the drain (P terminal) of the fifth MOS tube M5. Figure 8It can be understood that the pre-amplifier input tubes M2 and M3 and the auxiliary input tubes M6 and M7 are connected to M4 and M5 respectively. The point between the gate of the sixth MOS tube M6 and the third conversion switch SA3 is connected to the ground through the capacitor C1, and the point between the seventh MOS tube M7 and the fourth conversion switch SA4 is connected to the ground through the capacitor C2.

[0069] In an optional embodiment, the size ratio of the auxiliary input tube to the pre-amplifier input tube in the comparator is 1:4 to reduce the impact of each calibration on the offset voltage of the comparator. It should be noted that the ratio of the auxiliary input tube to the pre-amplifier input tube can also be set to other ratios, not limited to the ratio of 1:4.

[0070] The embodiment of the present invention further provides an offset voltage calibration method, corresponding to the offset voltage calibration circuit of the above embodiment. Fig.10 As shown, the offset voltage calibration method provided in this embodiment includes the following steps:

[0071] S101, sampling the input signal VIN through the capacitor array CDAC to obtain a sampling signal;

[0072] S102, detecting the magnitude of the residual signal at the input end after the amplifier amplifies the sampling signal, and determining the magnitude and direction of the offset voltage of the amplifier;

[0073] S103, adjusting the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier;

[0074] S104, performing a difference comparison between the offset voltage of the comparator and the offset voltage of the amplifier, so that the offset voltage of the comparator cancels the offset voltage of the amplifier, so that the equivalent offset voltage of the entire stage circuit is zero.

[0075] In the above step S103, the offset voltage of the comparator is adjusted in magnitude and direction according to the offset voltage of the amplifier, specifically: if the amplifier has an offset voltage in the positive direction, and the comparator has an offset voltage in the negative direction at this time, the offset voltage of the negative direction of the comparator is adjusted in the positive direction through the calibration logic until the offset voltage of the comparator is in the positive direction, and the magnitude of the offset voltage of the positive direction of the comparator is equal to the magnitude of the offset voltage of the positive direction of the amplifier; if the amplifier has an offset voltage in the positive direction, and the comparator has an offset voltage in the positive direction at this time, the offset voltage of the positive direction of the comparator is adjusted to be equal to the magnitude of the offset voltage of the positive direction of the amplifier through the calibration logic; if the amplifier has an offset voltage in the positive direction, and the comparator does not have an offset voltage at this time, the comparator is made to present an offset voltage in the positive direction through the calibration logic, and the offset voltage of the positive direction of the comparator is gradually adjusted to be equal to the magnitude of the offset voltage of the positive direction of the amplifier. Similarly, when the amplifier has an offset voltage in the negative direction, the offset voltage of the comparator is adjusted in the direction of the offset voltage of the amplifier.

[0076] In the above steps, at the end of sampling, the first conversion switch SA1 is disconnected, the sampled signal is quantized, and the signal chain of the amplifier is established using the quantized sampled signal. At the end of quantization, the reset switch RST is disconnected, so that the sampled signal on the capacitor array is transferred to the amplifier, and the signal chain of the amplifier AMP is established. After the amplifier signal chain is established, the sampling of the rear-stage circuit is completed, the second conversion switch SA2 is disconnected, and the calibration pulse signal is sent to the comparator COMP, triggering the comparator to perform a comparison operation, thereby realizing the difference comparison between the offset voltage of the comparator and the offset voltage of the amplifier.

[0077] The embodiment of the present invention also provides a pipeline successive approximation analog-to-digital converter (Pipeline-SAR ADC). Figure 2 and Figure 6It is understood that the embodiment of the present invention improves the stage circuit of the existing Pipeline-SAR ADC, adds a set of timing control on the basis of the original stage circuit, and adds a pair of auxiliary input tubes in the comparator, by detecting the size of the residual signal at the input end after the amplifier amplification is completed, and using the offset voltage of the comparator to offset the offset voltage of the amplifier, so that the equivalent offset voltage is zero, thereby realizing offset voltage calibration. In each stage of the Pipeline-SAR ADC, the previous stage circuit is connected to the next stage circuit through the amplifier AMP, and each stage circuit includes a capacitor array CDAC and a comparator COMP, the output end of the capacitor array CDAC is connected to the negative input end of the comparator COMP and the reverse input end of the amplifier, and the positive input end of the comparator COMP is grounded; the same-direction input end and the reverse input end of the amplifier AMP are connected through the first conversion switch SA1, and the output end of the amplifier AMP is connected to the next stage circuit Backend through the second conversion switch SA2, the same-direction input end of the amplifier AMP is grounded, and the reverse input end of the amplifier AMP is grounded through the reset switch RST.

[0078] The capacitor array CDAC samples the input signal VIN to obtain a sampling signal. The amplifier AMP uses the quantized sampling signal to establish the signal chain of the amplifier. The comparator includes an offset voltage adjustment circuit, which adjusts the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier. The comparator COMP performs a comparison operation under the triggering of the calibration pulse signal, and uses the offset voltage of the comparator to offset the offset voltage of the amplifier, so that the overall equivalent offset voltage of the stage circuit is zero.

[0079] The timing control process for offset voltage calibration is as follows: the capacitor array CDAC of the first-stage circuit (SAR ADC) samples the input signal; when sampling is completed, the SA1 switch is disconnected and the SAR ADC starts quantization. For example, the first-stage SAR ADC controls a total of 6 sampling capacitors, and at this stage there are a total of six pulse signals (CLK) triggering the comparator. When the SAR ADC quantization is completed, the RST switch is disconnected, and due to the effect of negative feedback, the charge on the sampling capacitor begins to transfer, and the amplifier begins to establish a signal chain. When the signal chain of the amplifier AMP is basically established, the SA2 switch is disconnected, and the next-stage sampling is completed. When the signal chain of the amplifier AMP is fully established, the input voltage of the amplifier becomes 0, and the input of the amplifier is in a virtual short-circuit state. When the amplifier has an offset voltage, the voltage at the input of the amplifier is the offset voltage. At this time, the SAR ADC calibration logic triggers a calibration pulse signal (CAL) to the comparator COMP, triggering the comparator to perform a comparison operation. When the comparator COMP completes the comparison, the amplifier AMP is reset and the calibration is completed.

[0080] In a specific embodiment, the circuit of the comparator COMP includes a pre-amplifier input tube, a charge pump, and a pair of auxiliary input tubes. The pre-amplifier input tube inputs a differential signal, and the auxiliary input tube is connected to a common mode voltage and a charge pump. The comparator inputs the data obtained from each calibration pulse signal into the charge pump, adjusts the input voltage of the auxiliary input tube, and plays a role in adjusting the offset voltage. The size ratio of the auxiliary input tube to the pre-amplifier input tube in the comparator can be set to 1:4 or other ratios to reduce the impact of each calibration on the offset voltage of the comparator.

[0081] like Figure 8 As shown, the pre-amplifier input tube includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, and a fifth MOS tube M5. The gate of the first MOS tube M1, the gate of the fourth MOS tube M4, and the gate of the fifth MOS tube M5 are connected to the calibration pulse signal CLK, the drain of the first MOS tube M1 is connected to the source of the second MOS tube M2 and the source of the third MOS tube M3, the gate of the second MOS tube M2 is connected to the differential positive analog input voltage VIP, and the gate of the third MOS tube M3 is connected to the differential negative analog input voltage VIN; the drain of the second MOS tube M2 is connected to the drain of the fourth MOS tube M4, the drain of the third MOS tube M3 is connected to the drain of the fifth MOS tube M5, the source of the fourth MOS tube M4 and the source of the fifth MOS tube M5 are connected to the power supply voltage VDD, and the source of the first MOS tube M1 is grounded.

[0082] like Fig. 9As shown, the auxiliary input tubes include: a sixth MOS tube M6, a seventh MOS tube M7, and an eighth MOS tube M8. The gate of the sixth MOS tube M6 is connected to the common mode voltage VCM through the third conversion switch SA3, and the gate of the seventh MOS tube M7 is connected to the charge pump Charge Pump through the fourth conversion switch SA4. The gate of the eighth MOS tube M8 is connected to the reference voltage VB, the source of the eighth MOS tube M8 is grounded, the drain of the eighth MOS tube M8 is connected to the source of the sixth MOS tube M6 and the source of the seventh MOS tube M7, the drain of the sixth MOS tube M6 is connected to the drain (N terminal) of the fourth MOS tube M4, and the drain of the seventh MOS tube M7 is connected to the drain (P terminal) of the fifth MOS tube M5. Figure 8 A point between the gate of the sixth MOS transistor M6 and the third conversion switch SA3 is connected to the ground through the capacitor C1, and a point between the seventh MOS transistor M7 and the fourth conversion switch SA4 is connected to the ground through the capacitor C2.

[0083] The Pipeline-SAR ADC of this embodiment has the following advantages:

[0084] 1. The offset voltage of the comparator and amplifier is calibrated at the same time, with high calibration accuracy;

[0085] 2. The implementation is simple. By adding a set of timing control and a pair of comparator auxiliary input tubes, offset voltage calibration can be achieved;

[0086] 3. Amplifier and comparator calibration is realized in the analog domain, and the output voltage of the amplifier is not affected by the offset voltage;

[0087] 4. The offset voltage can be tracked in real time with fast convergence speed.

[0088] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A method for calibrating an offset voltage, applied to various stages of an analog-to-digital converter, characterized in that: In each level of the circuit, the previous level circuit is connected to the next level circuit through an amplifier, each level circuit includes a capacitor array and a comparator, the output end of the capacitor array is connected to the negative input end of the comparator and the reverse input end of the amplifier, and the method includes: The input signal is sampled by a capacitor array to obtain a sampling signal; Detecting the magnitude of the residual signal at the input end after the amplifier amplifies the sampling signal, and determining the magnitude and direction of the amplifier's offset voltage; Adjusting the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier; The offset voltage of the comparator is compared with the offset voltage of the amplifier, so that the offset voltage of the comparator cancels the offset voltage of the amplifier, so that the equivalent offset voltage of the entire stage circuit is zero.

2. The offset voltage calibration method according to claim 1, characterized in that: The step of adjusting the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier comprises: If the amplifier has an offset voltage in the positive direction and the comparator has an offset voltage in the negative direction, the offset voltage in the negative direction of the comparator is adjusted to the positive direction through the calibration logic until the offset voltage of the comparator is in the positive direction and the magnitude of the offset voltage in the positive direction of the comparator is equal to the magnitude of the offset voltage in the positive direction of the amplifier; If the amplifier has an offset voltage in the positive direction, the comparator has an offset voltage in the positive direction, and the offset voltage in the positive direction of the comparator is adjusted to be equal to the offset voltage in the positive direction of the amplifier through calibration logic; If the amplifier has a positive offset voltage and the comparator does not have an offset voltage, the comparator is made to present a positive offset voltage through calibration logic, and the positive offset voltage of the comparator is adjusted to be equal to the magnitude of the positive offset voltage of the amplifier.

3. The offset voltage calibration method according to claim 1, characterized in that: The same-direction input terminal and the reverse input terminal of the amplifier are connected through a first conversion switch, the output terminal of the amplifier is connected to the next stage circuit through a second conversion switch, and the reverse input terminal of the amplifier is grounded through a reset switch.

4. The offset voltage calibration method according to claim 3, characterized in that: The method further comprises: When sampling is finished, the first conversion switch is turned off, the sampled signal is quantized, and the signal chain of the amplifier is established using the quantized sampled signal.

5. The offset voltage calibration method according to claim 4, characterized in that: The method of establishing a signal chain of an amplifier using the quantized sampled signal comprises: At the end of quantization, the reset switch is opened to transfer the sampled signal on the capacitor array to the amplifier, thus establishing the amplifier signal chain.

6. The offset voltage calibration method according to claim 3, characterized in that: The method further comprises: After the amplifier signal chain is established, the sampling of the rear-stage circuit is completed, the second conversion switch is disconnected, and a calibration pulse signal is sent to the comparator, triggering the comparator to perform a comparison operation.

7. An offset voltage calibration circuit, characterized in that: It includes a capacitor array, a comparator and an amplifier, wherein the output end of the capacitor array is connected to the negative input end of the comparator and the reverse input end of the amplifier, and the comparator includes an offset voltage adjustment circuit; The capacitor array samples the input signal to obtain a sampling signal; The amplifier uses the quantized sampled signal to establish a signal chain of the amplifier; The offset voltage adjustment circuit is used to adjust the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier; The comparator performs a comparison operation under the triggering of the calibration pulse signal, and uses the offset voltage of the comparator to offset the offset voltage of the amplifier, so that the overall equivalent offset voltage is zero.

8. The offset voltage calibration circuit according to claim 7, characterized in that: The same-direction input terminal and the reverse input terminal of the amplifier are connected via a first conversion switch, the output terminal of the amplifier is connected to a subsequent circuit via a second conversion switch, and the reverse input terminal of the amplifier is grounded via a reset switch.

9. The offset voltage calibration circuit according to claim 8, characterized in that: When the capacitor array sampling is finished, the first conversion switch is disconnected; After the reset switch is opened, the amplifier establishes a signal chain; After the second conversion switch is turned off, a calibration pulse signal is sent to the comparator to trigger the comparator to perform a comparison operation.

10. The offset voltage calibration circuit according to claim 7, characterized in that: The offset voltage adjustment circuit comprises: a pre-amplifier input tube, a charge pump and a pair of auxiliary input tubes. The pre-amplifier input tube inputs a differential signal, and the auxiliary input tube is connected to the charge pump.

11. The offset voltage calibration circuit according to claim 10, characterized in that: The pre-amplifier input tube includes: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, and a fifth MOS tube. The gates of the first MOS tube, the fourth MOS tube, and the fifth MOS tube are connected to a calibration pulse signal. The drain of the first MOS tube is connected to the source of the second MOS tube and the source of the third MOS tube. The gate of the second MOS tube is connected to a differential positive analog input voltage, and the gate of the third MOS tube is connected to a differential negative analog input voltage. The drain of the second MOS tube is connected to the drain of the fourth MOS tube, the drain of the third MOS tube is connected to the drain of the fifth MOS tube, and the source of the fourth MOS tube and the source of the fifth MOS tube are connected to a power supply voltage.

12. The offset voltage calibration circuit according to claim 11, characterized in that: The auxiliary input tubes include: a sixth MOS tube, a seventh MOS tube, and an eighth MOS tube. The gate of the sixth MOS tube is connected to the common mode voltage through a third conversion switch, the gate of the seventh MOS tube is connected to the charge pump through a fourth conversion switch, the drain of the eighth MOS tube is connected to the source of the sixth MOS tube and the source of the seventh MOS tube, the drain of the sixth MOS tube M6 is connected to the drain of the fourth MOS tube M4, and the drain of the seventh MOS tube M7 is connected to the drain of the fifth MOS tube M5.

13. A pipelined successive approximation analog-to-digital converter, comprising a plurality of stage circuits, characterized in that: The previous stage circuit in each stage circuit is connected to the next stage circuit through an amplifier, and each stage circuit includes a capacitor array and a comparator, the output end of the capacitor array is connected to the negative input end of the comparator and the reverse input end of the amplifier, and the comparator includes an offset voltage adjustment circuit; The capacitor array samples the input signal to obtain a sampling signal; The amplifier uses the quantized sampled signal to establish a signal chain of the amplifier; The offset voltage adjustment circuit is used to adjust the magnitude and direction of the offset voltage of the comparator according to the magnitude and direction of the offset voltage of the amplifier, so that the magnitude of the offset voltage of the comparator is equal to the magnitude of the offset voltage of the amplifier, and the direction of the offset voltage of the comparator is consistent with the direction of the offset voltage of the amplifier; The comparator performs a comparison operation under the triggering of the calibration pulse signal, and uses the offset voltage of the comparator to offset the offset voltage of the amplifier, so that the overall equivalent offset voltage is zero.

14. The pipelined successive approximation analog-to-digital converter according to claim 13, characterized in that: The same-direction input terminal and the reverse input terminal of the amplifier are connected via a first conversion switch, the output terminal of the amplifier is connected to a subsequent circuit via a second conversion switch, and the reverse input terminal of the amplifier is grounded via a reset switch.

15. The pipelined successive approximation analog-to-digital converter according to claim 13, characterized in that: The offset voltage adjustment circuit comprises: a pre-amplifier input tube, a charge pump and a pair of auxiliary input tubes. The pre-amplifier input tube inputs a differential signal, and the auxiliary input tube is connected to the charge pump.

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