Flow control system and method

Abstract

The invention provides a flow control system and method. The system comprises a switching chip, a plurality of transaction receiving devices and a plurality of transaction sending devices, wherein the transaction receiving devices and the transaction sending devices are connected with the switching chip. Transaction packet transmission between transaction sending equipment and transaction receiving equipment is carried out through an exchange chip, and when a plurality of transaction sending equipment occupy the same transmission link, and the flow distribution conditions of the transaction packet forwarding time requirement and the to-be-returned transaction packet quantity requirement are met at the same time, the transaction packet is transmitted to the transaction receiving equipment. And selecting a target transaction sending device for sending the transaction packet with the minimum data length to distribute flow, so as to transmit the transaction packet sent by the target transaction sending device to a transaction receiving device, therefore, delay of overall data transmission caused by the fact that the length of the to-be-returned transaction data is large and the transaction sending device corresponding to the transaction with the large number of to-be-returned transaction packets occupies too much flow can be avoided, and reliability and efficiency of data routing transmission are effectively improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a flow control system and method. Background Art

[0002] The PCIe switch chip is a high-speed hybrid digital-analog chip used to expand the link topology and complete data routing in the PCIe link to serve the root complex (RC) and the endpoint device (EP). The switch chip is also called Switch, or SW for short. Each port of the SW needs to be able to complete the data packet output and input. These data packets need to pass through the PCIe controller and transaction router of the SW and stay in the data path and memory within the SW for a period of time. For ASIC chips, data paths and memory resources are difficult to reconstruct. Therefore, flow control design is crucial for high-reliability and low-latency data exchange, which is also one of the main difficulties in the development of PCIe switch chips.

[0003] For example, Figure 1 In the flow control system shown, devices B and C initiate requests to device A through the corresponding source ports (i.e., ports B and C). These requests are routed by the switching chip and sent from the target port (i.e., port A), occupying the same link. If the transaction volume required to be returned by the request initiated by device B is much larger than the transaction volume returned by the request of device C, then most of the traffic on the link will be allocated to device B, and the transaction of device C will be in a starvation state for a long time, which may affect the functional operation of device C. At the same time, it cannot be guaranteed that the transaction of device C is processed in time, thereby affecting the reliability and efficiency of the overall data transmission. Therefore, it is necessary to control the traffic allocation of each port to ensure that each device and the corresponding transaction data can be processed in a timely and reliable manner. Summary of the invention

[0004] The main purpose of the present application is to provide a traffic control system and method, which can at least solve the problem of low reliability and large delay of data transmission caused by unreasonable traffic distribution of transmission links in related technologies.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides a traffic control system, which includes: a switching chip, multiple transaction receiving devices and multiple transaction sending devices, wherein the transaction receiving devices and the transaction sending devices are all connected to the switching chip, wherein the transaction sending device is configured to: send multiple first transaction packets to the switching chip, and receive the second transaction packet returned by the switching chip; wherein the first transaction packet includes data length information of the transaction request return; the switching chip is configured to: respectively obtain the target interval duration required for forwarding multiple first transaction packets of each transaction sending device, and obtain the number of transaction packets that are not returned to each transaction sending device; count the forwarding interval duration of each first transaction packet, when multiple transaction sending devices correspond to the same target transaction receiving device, if multiple forwarding interval durations all reach the corresponding target interval duration and the number of non-returned transaction packets of the corresponding multiple transaction sending devices is less than the corresponding preset threshold, then the traffic is allocated to the first target transaction sending device; wherein the data length of the transaction request return in the first transaction packet corresponding to the first target transaction sending device is the smallest.

[0006] The second aspect of the present application provides a flow control method, which is applied to the flow control system provided by the first aspect of the present application, and the method includes: a transaction sending device sends multiple transaction packets to the switching chip; wherein the transaction packet includes data length information of the requested return transaction; the switching chip respectively obtains the target interval duration required for forwarding the multiple transaction packets of each transaction sending device, and obtains the number of transaction packets that are not returned to each transaction sending device; the switching chip counts the forwarding interval duration of each transaction packet, and when the multiple transaction sending devices correspond to the same target transaction receiving device, if the multiple forwarding interval durations all reach the corresponding target interval duration and the corresponding number of unreturned transaction packets of the multiple transaction sending devices is less than the corresponding preset threshold, the flow is allocated to the target transaction sending device; wherein the data length of the requested return transaction in the transaction packet sent by the target sending device is the smallest.

[0007] As can be seen from the above, through the implementation of the scheme of the present application, the switching chip transmits the first transaction packet sent by the transaction sending device to the transaction receiving device, and at the same time, the second transaction packet returned by the transaction receiving device can be transmitted to the transaction sending device. For multiple transaction sending devices that expect to occupy the same transmission link, the switching chip can determine which transaction sending device to allocate traffic to based on whether the corresponding first transaction packet has reached the sending time and the number of corresponding unreturned transaction packets. When multiple transaction sending devices simultaneously meet the above two conditions, the traffic is allocated to the target transaction sending device corresponding to the first transaction packet with the smallest data length, so as to transmit the first transaction packet sent by the target transaction sending device to the transaction receiving device, thereby avoiding the transaction sending device corresponding to the transaction with a large transaction data length to be returned and a large number of transaction packets to be returned occupying too much traffic and affecting the operation of other devices with transaction requests and meeting the transmission conditions, thereby effectively providing the reliability and efficiency of the overall data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 A schematic diagram of the structure of a flow control system provided in this embodiment;

[0010] Figure 2 A schematic diagram of the structure of another flow control system provided in this embodiment;

[0011] Figure 3 A schematic diagram of a flow control principle provided in this embodiment;

[0012] Figure 4 A schematic diagram of the structure of a switching chip provided in this embodiment;

[0013] Figure 5 A cache distribution diagram of a transceiver module provided in this embodiment;

[0014] Figure 6 A basic flow chart of a flow control method provided in this embodiment. DETAILED DESCRIPTION

[0015] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0016] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0017] In order to solve the problem of low reliability and large delay of data transmission caused by unreasonable traffic allocation of transmission links in the related art, an embodiment of the present application provides a traffic control system, see Figure 2 As shown in the structural diagram of the flow control system, the flow control system includes a switching chip, multiple transaction receiving devices and multiple transaction sending devices, and the transaction receiving devices and the transaction sending devices are all connected to the switching chip, wherein:

[0018] The transaction sending device is configured to: send multiple first transaction packets to the switching chip, and receive the second transaction packet returned by the switching chip; wherein the first transaction packet includes the transaction data length information requested to be returned; the switching chip is configured to: respectively obtain the target interval duration required for forwarding multiple first transaction packets of each transaction sending device, and obtain the number of transaction packets that have not been returned to each transaction sending device; count the forwarding interval duration of each first transaction packet, and when multiple transaction sending devices correspond to the same target transaction receiving device, if multiple forwarding interval durations all reach the corresponding target interval duration and the number of unreturned transaction packets of the corresponding multiple transaction sending devices is less than the corresponding preset threshold, then the traffic is allocated to the first target transaction sending device; wherein the data length of the transaction requested to be returned in the first transaction packet corresponding to the first target transaction sending device is the smallest.

[0019] Specifically, in this embodiment, taking the common PCIe link topology as an example, the link adopts an end-to-end data transmission method, that is, there is only one link between the two devices, and the data flows between the upstream and downstream through the link, and the data stop nodes are RC, EP, and SW. The transaction sending device and the transaction receiving device in this embodiment can be any one of SW, RC, and EP. Among them, the transaction sending device is responsible for sending multiple first transaction packets to the switching chip, and the switching chip is responsible for transmitting the first transaction packet sent by each transaction sending device to the transaction receiving device. At the same time, the second transaction packet returned by the transaction receiving device can be returned to the transaction sending device. The second transaction packet is the transaction packet requested to be returned by the transaction sending device. The number of unreturned transaction packets can be obtained by counting the number of returned transaction packets. When there are multiple transaction sending devices that expect to occupy the same transmission link, the switching chip can determine which transaction sending device to allocate traffic to based on whether the corresponding first transaction packet has reached the sending time and the number of corresponding unreturned transaction packets. When multiple transaction sending devices meet the above two conditions at the same time, the traffic is allocated to the target transaction sending device corresponding to the first transaction packet requesting the smallest transaction data length to be returned, so as to transmit the first transaction packet sent by the target transaction sending device to the transaction receiving device, thereby preventing the transaction sending device corresponding to the transaction with a large length of transaction data to be returned and a large number of transaction packets to be returned from occupying too much traffic and affecting the operation of other devices with transaction requests and meeting the transmission conditions, thereby effectively providing the reliability and efficiency of the overall data transmission.

[0020] In some embodiments, when the switching chip executes the function of respectively obtaining the target interval duration required to forward multiple first transaction packets of each transaction sending device, the switching chip is specifically configured to: respectively obtain the first data transmission link width corresponding to each transaction sending device, the second data transmission link width corresponding to the transaction receiving device, and the data length of the transaction packet requested to be returned by each transaction sending device; and determine the target interval duration required to forward multiple first transaction packets of the transaction sending device according to the first data transmission link width, the second data transmission link width and the data length.

[0021] Specifically, in this embodiment, the flow of the link can be considered as the product of time and link width. After the link is established, the link width of the switching chip is stable, so the flow control can be performed based on time. Figure 1 Taking the traffic control system shown as an example, assuming that the transaction packet sent by port A this time comes from port B, the link width between port B and the corresponding transaction sending device is Ws, the link width between port A and the transaction receiving device is Wd, and the data length of the transaction packet required to be returned by the transaction sending device corresponding to port B is P, then the time interval Tp (that is, the forwarding interval duration) for port A to send the next transaction packet from port B can be expressed as a mapping of the above variables: Tp=f(Ws, Wd, P).

[0022] Further, in some embodiments, when the switching chip performs the function of determining the target interval duration required for forwarding multiple first transaction packets of a transaction sending device according to the first data transmission link width, the second data transmission link width and the data length, the switching chip is specifically configured to: determine the length level of the data length; match the first data transmission link width, the second data transmission link width and the length level with the corresponding interval duration index table; and determine the matched interval duration as the target interval duration required for forwarding multiple first transaction packets of the corresponding transaction sending device.

[0023] Specifically, in this embodiment, in order to perform the flow control of this implementation, the aforementioned mapping relationship can be made into an index table in advance to quickly find the corresponding Tp according to Ws, Wd, and P. The mapping relationship can be adjusted according to the system application scenario and the actual performance of the chip circuit, so the index table is reconfigurable. After a large number of tests in a specific system application scenario, a relatively optimal or approximately optimal mapping relationship can be found to configure the index table. Moreover, in the scenario of the same target port and different source ports, a unified lookup table can be set, and in order to obtain better performance, different lookup tables can also be set for different source ports. In addition, the data length of the transaction packet can be further graded, and P can be used to calculate the value of the mapping relationship. level Indicates the data length level of the transaction packet, and P level It can be determined from the piecewise function about P, ​​and the length of the request return data can be obtained through the transaction header. Therefore, the above mapping can be changed to: Tp = f(Ws, Wd, P level ). Among them, the relationship between Ws, Wd and Tp can be described as follows: the smaller the Ws / Wd, the more the data length required to be returned by the transaction sending device will occupy the internal cache resources of the chip, thereby affecting the return of other port request transactions. Therefore, it is necessary to set Tp to a larger value to reduce the internal cache occupied by the return transaction of the same source port; similarly, P level The larger it is, the larger the internal buffer occupied by the return transaction of the transaction sending device is. Therefore, Tp also needs to be set larger.

[0024] In other embodiments, the switching chip is further configured as follows: if multiple forwarding interval durations all reach the corresponding target interval durations, the traffic is allocated to the first target transaction sending device; if the number of unreturned transaction packets corresponding to multiple transaction sending devices is less than the corresponding threshold, the traffic is allocated to the first target transaction sending device; if only one second target transaction sending device has its corresponding forwarding interval duration reach the corresponding target interval duration, the traffic is allocated to the second target transaction sending device; if only one third target transaction sending device has its corresponding number of unreturned transaction packets less than the corresponding threshold, the traffic is allocated to the third target transaction sending device.

[0025] Specifically, in this embodiment, in addition to determining which transaction sending device to allocate traffic to based on the forwarding interval duration corresponding to each transaction packet, the allocated traffic can also be controlled based on the number of transaction packets that have been accumulated and have not yet been returned. This is also to avoid a large amount of cache being occupied by return transactions from the same source port. Therefore, N timers, N lookup tables, and 1 arbiter A can be set in a port. Among them, the timer is used to time Tpi. When Tpi is reached (called condition one), port A can release the transaction from port i. When the timers of multiple source ports all reach Tp, the arbiter can be used to select which port's transaction packet to send. This embodiment chooses to give priority to sending transactions with a smaller data length (i.e., P level At the same time, N counters, N thresholds, and an arbiter B are also set in the port. The counter is used to count the number of transaction packets that have been accumulated but not returned corresponding to the request transaction from port i. When the number of unreturned transaction packets is less than the corresponding threshold Th i When the counters of multiple source ports indicate a value less than the corresponding Th, the arbitrator can select which port to issue the transaction. In this embodiment, the transaction with the smaller data length (i.e., P) is issued first. level The threshold is related to factors such as the cache resources of the switch chip port, application scenarios, and link performance. i It can be preset or configured after testing, and the threshold comparison can be completed in the threshold. The arbitrator A and arbitrator B in this embodiment can be reused, for example Figure 3 As shown in the flow control principle diagram, when condition one and / or condition two are met, the transaction is released and arbitration is performed.

[0026] like Figure 4 FIG. 1 is a schematic diagram of the structure of a switching chip provided in this embodiment. Figure 4 The switching chip includes a routing module and multiple transceiver modules. The transceiver module includes multiple transceiver ports, which are respectively connected to the routing module, the transaction sending device or the transaction receiving device; the first transceiver port as the input port is configured to: transmit the first transaction packet to the routing module; the second transceiver port as the output port is configured to: receive the first transaction packet transmitted by the routing module and transmit it to the transaction receiving device.

[0027] Specifically, in this embodiment, the switching chip needs to process multiple transactions specified by the PCIe protocol. These transactions are divided into P (Posted) packets, NP (Non-Posted) packets, and Cpl (Completion) packets. These packets need to be transmitted in the order of transactions specified by the PCIe protocol to ensure the correct flow of data in the system. Therefore, the flow control mechanism of the switching chip needs to ensure reliability and real-time performance on the basis of meeting the sorting requirements. The switching chip in this embodiment includes a routing module and multiple transceiver modules, and each transceiver module includes multiple ports. Each transceiver module and each port can undertake the task of transaction entry and exit, and the routing module sends the transaction to the correct exit module and exit port. The transaction data is pushed forward step by step as indicated by the arrows to complete the transaction packet entry, routing, and exit, while ensuring that the transaction is sorted correctly.

[0028] Furthermore, in some embodiments, a back pressure module is also included, which is connected to the routing module, and the transceiver port includes a buffer pool; the back pressure module is configured as follows: when the bandwidth of the first transceiver port is greater than the bandwidth of the second transceiver port, the routing module is controlled to back pressure the first transaction packet to the buffer pool of the first transceiver port until the back pressure duration reaches a preset duration threshold; when the bandwidth of the first transceiver port is less than the bandwidth of the second transceiver port, the routing module is controlled to back pressure the first transaction packet to the buffer pool of the first transceiver port until the transaction data in the first transaction packet is complete; or, the routing module is controlled to back pressure the first transaction packet to the buffer pool of the first transceiver port until the length of the transaction data in the first transaction packet reaches a preset threshold.

[0029] Specifically, in this embodiment, efficient use of cache is an important means of flow control. On the one hand, transaction sorting has a natural requirement for cache capacity. On the other hand, the more cache capacity that can be used, the more transactions that can be cached, which is conducive to transaction transmission. In this embodiment, each transceiver port contains a cache pool, and the cache pool includes an in-chip cache and an out-chip cache. Since the bandwidth (link width × rate) of the in-chip port and the out-chip port may be inconsistent, it is necessary to set a back pressure module, which is designed to deal with the following two situations: If the bandwidth of the in-chip port is continuously greater than the bandwidth of the out-chip port, then the out-chip cache will be full. If it is written again, the valid data will be overwritten and the transaction integrity will be damaged. Therefore, at this time, the back pressure module needs to control the routing module to back pressure the out-chip cache, and at the same time control the routing module to back pressure the in-chip cache to temporarily stop the data flow before the out-chip cache. If the bandwidth of the in-chip port is continuously less than the bandwidth of the out-chip port, then the out-chip port will definitely exhaust the data from the in-chip port in advance. After exhaustion, invalid data will be repeatedly read out or empty data will be sent, causing transmission transaction deformity. Therefore, the back pressure module can be designed into two modes. The first mode adopts the basic circuit (BaseCircuit, BC), which can back pressure all single transaction data into the in-chip cache of the in-chip port until the transaction data is collected, that is, as long as the out-chip port starts sending, it can send a complete transaction data. The second mode adopts the high-performance back pressure circuit (High Performance Backpressure Circuit, HPBC). This mode no longer back pressures the in-chip cache all the time, thereby avoiding possible link disconnection and waste of transmission bandwidth. The principle of the HPBC mode is: when the transaction data enters the in-chip cache for a period of time, the back pressure module controls its back pressure until it meets condition A and releases its back pressure; condition A is described as: releasing the back pressure at a certain time will not cause the subsequent transaction data to be exhausted. Among them, the transaction data length len can be obtained through the transaction packet header. Assuming that the bandwidth of the in-chip port is 1:n compared with the bandwidth of the out-chip port, then the transaction data length reaches the threshold l th When , the back pressure can be relieved. Therefore, l th Need to meet: len-l th =len / n, that is, The l th The threshold is dynamically updated with each transaction packet header. The first mode is applicable when the system transmits low-frequency, low-real-time demand, and small-scale data streams; the second mode is applicable when the system transmits high-frequency, high-real-time demand, and large-scale data streams.

[0030] Furthermore, in some embodiments, the cache pool includes a private cache pool and a shared cache pool; the back pressure module is specifically configured to: control the routing module to back pressure the first transaction packet to the private cache pool of the first transceiver port; if the private cache pool is full and there is uncached transaction data, then control the routing module to back pressure the uncached transaction data to the shared cache pool.

[0031] Specifically, in this embodiment, all ports of each transceiver module have a private in-chip buffer pool and a private out-chip buffer pool, and each transceiver module also has a shared buffer pool for in-chip and out-chip buffers. The shared buffer pool refers to the same buffer that can be shared by the in-chip and out-chip of the same port in the same transceiver module. At the same time, different ports in the same transceiver module can share the same buffer, for example Figure 5 When back pressure is applied to transaction packets, the transaction packets are back pressured into the private buffer pool first. When the private buffer pool is full, the remaining transaction data to be cached are back pressured into the shared buffer pool.

[0032] In some embodiments, before executing the function of sending multiple first transaction packets to the switching chip, the transaction sending device is also configured to: send a first cache resource update instruction to the switching chip at an interval of a preset first time duration, and receive a second cache resource update instruction sent by the switching chip at an interval of a preset second time duration; wherein the second cache resource update instruction is used to instruct the transaction receiving device to update a preset unit cache amount; based on the total unit cache amount of the switching chip, the number of remaining cache resources of the switching chip, the total first cache amount updated by the transaction sending device from the initial moment to the current moment, the total second cache amount updated by the transaction sending device within a single first time duration, and the unit cache amount, determine whether the cache resources of the transaction sending device and the switching chip are abnormal; if abnormal, reset the cache resources, and at the same time instruct the switching chip to reset the cache resources based on the first cache resource update instruction; when the cache resources are reset, execute the function of sending multiple first transaction packets to the switching chip.

[0033] Furthermore, in some implementations, the transaction sending device is further configured to: obtain a preset number of cache resource partitions; calculate a ratio of the total cache amount of the switching chip to the number of cache resource partitions to obtain a unit cache amount.

[0034] Specifically, in this embodiment, to avoid abnormal situations such as loss of transaction data during transmission, the credit between the transaction sending device and the switching chip can also be controlled to ensure the reliability and efficiency of data transmission. Here, credit refers to the buffer resources reserved by devices at both ends of the link (such as device A and device B) for input data. Sufficient credit indicates that the input data packet can be cached, while insufficient credit indicates that the data input packet cannot be cached and waiting is required. According to the PCIe protocol, device A will inform device B of its updated credit through a credit update DLLP (Data Link Layer Packet); device A will also record the credit that the issued transactions should occupy. These two parts of information can help device A decide whether to send transaction data to avoid loss of transaction data after transmission.

[0035] However, in the actual design process, situations where credit updates are incorrect often occur. The main reason is that credit updates are judged based on the transaction volume read from the buffer. This leads to the possibility that if a transmission error occurs during transaction transmission or the device itself does not support a certain type of transaction, and thus the transaction is determined to be a malformed packet, the credit may not be updated (i.e., the credit is updated at the A end, but at the B end, due to the determination of the malformed packet, even though data is read from the buffer, the credit is not updated), resulting in permanent occupation of credit resources on the link. This situation often leads to credit overflow, and the link needs to be reset to make it resume operation. Therefore, a control mechanism for credit recovery needs to be set up. By periodically sending in-band signals (such as vendor-defined DLLP) or sideband signals, it is借此 to indicate whether the devices at both ends of the link perform credit reset. Taking the device at the A end as the transaction sending device (the device type of this transaction sending device can be any one of SW, RC, EC), and the device at the B end as the switching chip as an example, the transaction sending device transmits a credit update instruction (such as sending DLLP) every T1 to instruct the switching chip to perform credit update, and the switching chip transmits a credit update instruction every T2 (T2 << T1) to instruct the transaction sending device to update the unit credit amount (i.e., the unit buffer amount) each time. Whether to perform credit reset can be judged based on the updated credit amount of the transaction sending device and the remaining credit amount of the switching chip. It should also be noted that when the total cache of the switching chip is divided into multiple parts, each cache block contains multiple buffer areas, and the remaining number of buffer resource parts refers to the number of cache blocks in which none of the multiple buffer areas are occupied.

[0036] Further, in some embodiments, the transaction sending device is specifically configured to: calculate a first ratio of the duration from the initial moment to the current moment to the second duration and a second ratio of the first duration to the second duration; calculate a first sum of x unit cache amounts and a second sum of y unit cache amounts; wherein x is the integer part of the first ratio and y is the integer part of the second ratio; multiply the number of cache resource divisions by the unit cache total amount and then subtract the result from the first cache total amount to obtain a first difference, and add the first difference to the first sum to obtain a third sum; multiply the number of remaining cache resource shares by the unit cache total amount and then subtract the result from the second cache total amount to obtain a second difference, and add the second difference to the second sum to obtain a fourth sum; if the third sum is less than the unit cache total amount and the fourth sum is greater than the unit cache total amount, it is determined that the cache resources of the transaction sending device and the switching chip are abnormal.

[0037] Specifically, in this embodiment, assuming that the current time is T, the credit amount updated by the transaction sending device each time within T is CT j (j is the jth issuance, and m times have been issued within T), then the total amount of credit updated by the transaction sending device within T (i.e., the total amount of the first cache) can be expressed as The credit amount of each transaction update issued by the transaction sending device within T1 is CT k (k is the kth issuance, and p times have been issued in T1), then the total amount of credit updated by the transaction sending device in T1 (i.e., the total amount of the second cache) can be expressed as The switching chip indicates that the transaction sending device updates the unit credit amount CR each time. i (i is the i-th update), the credit amount to be updated within T3 (x times have been issued within T3) (i.e., the first sum of x units of credit, x is the integer part of T / T2) can be expressed as The credit amount to be updated within T4 (y times issued within T4) (i.e., the second sum of y units of credit, y is the integer part of T1 / T2) can be expressed as Assume that the number of cache resource partitions of the switching chip is S1, the total cache amount of the switching chip is N, and the number of remaining cache resource shares of the switching chip is S2. Then, when the updated credit amount and the total cache amount satisfy the following formula:

[0038]

[0039] Then, the transaction sending device will reset its own credit when it issues a credit update instruction next time, and inform the switching chip to reset the credit. This is because the above formula (a) indicates that according to the credit update mechanism of the PCIe protocol, the total credit is about to be exhausted; the above formula (b) indicates that according to the credit recovery control mechanism, there is still credit left. That is, the two formulas will be contradictory when they are true at the same time. Therefore, in this case, it can be considered that errors such as bit errors occur in the transactions transmitted by the link, causing the credit to be permanently occupied, and the credit of the devices at both ends can be recovered.

[0040] The present application also provides a flow control method, which is applied to the aforementioned flow control system, see Figure 6 The basic flow chart of the flow control method shown in FIG. 1 includes:

[0041] Step 601: The transaction sending device sends multiple transaction packets to the switching chip;

[0042] Step 602: The switching chip respectively obtains the target interval time required to forward the multiple transaction packets of each transaction sending device, and obtains the number of transaction packets that are not returned to each transaction sending device;

[0043] Step 603, the switching chip counts the forwarding interval duration of each transaction packet. When multiple transaction sending devices correspond to the same target transaction receiving device, if multiple forwarding interval durations reach the corresponding target interval durations and the number of unreturned transaction packets of the corresponding multiple transaction sending devices is less than the corresponding preset threshold, the traffic is allocated to the target transaction sending device.

[0044] Among them, the transaction packet sent by the transaction sending device includes the data length information of the transaction requested to be returned; the data length of the transaction requested to be returned in the transaction packet sent by the target sending device is the smallest. In this embodiment, the switching chip transmits the first transaction packet sent by the transaction sending device to the transaction receiving device, and at the same time, the second transaction packet returned by the transaction receiving device can be returned to the transaction sending device. Since the flow of the link can be considered as the product of time and link width, after the link is established, the link width of the switching chip is stable, so the flow control can be performed based on time. In addition, the allocated flow can also be controlled according to the number of transaction packets that have been accumulated and have not yet been returned to each transaction sending device, which is also to avoid a large amount of cache being occupied by the return transaction of the same source port. When there are multiple transaction sending devices that expect to occupy the same transmission link, the switching chip can determine which transaction sending device to allocate traffic to based on whether the corresponding first transaction packet meets the sending time requirement and the number of corresponding unreturned transaction packets. When multiple transaction sending devices meet the above two conditions at the same time, the traffic is allocated to the target transaction sending device corresponding to the first transaction packet with the smallest data length, so as to transmit the first transaction packet sent by the target transaction sending device to the transaction receiving device, thereby preventing the transaction sending device corresponding to the larger length of the transaction data to be returned and the larger number of transaction packets to be returned from occupying too much traffic and affecting the operation of the remaining devices with transaction requests and meeting the transmission conditions, thereby effectively providing the reliability and efficiency of the overall data transmission.

[0045] It should be noted that, for the above-mentioned embodiments, for the sake of simplicity of description, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0046] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0047] The above is a description of the flow control system and method provided in the present application. For technicians in this field, according to the ideas of the embodiments of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A flow control system, characterized in that: It includes a switching chip, a plurality of transaction receiving devices and a plurality of transaction sending devices, wherein the transaction receiving devices and the transaction sending devices are both connected to the switching chip, wherein: The transaction sending device is configured to: send a plurality of first transaction packets to the switch chip, and receive a second transaction packet returned by the switch chip; wherein the first transaction packet includes data length information of a request return transaction; The switching chip is configured to: respectively obtain the target interval duration required for forwarding multiple first transaction packets of each transaction sending device, and obtain the number of transaction packets that have not been returned to each transaction sending device; when multiple transaction sending devices correspond to the same target transaction receiving device, count the forwarding interval duration of each first transaction packet, and if multiple forwarding interval durations reach the corresponding target interval duration and the number of unreturned transaction packets of the corresponding multiple transaction sending devices is less than the corresponding preset threshold, then allocate the traffic to the first target transaction sending device; wherein, the data length of the requested return transaction in the first transaction packet corresponding to the first target transaction sending device is the smallest.

2. The flow control system according to claim 1, characterized in that: When the switching chip performs the function of respectively acquiring the target interval durations required for forwarding the plurality of first transaction packets of each transaction sending device, the switching chip is specifically configured as follows: Respectively obtain a first data transmission link width corresponding to each of the transaction sending devices, a second data transmission link width corresponding to the transaction receiving device, and a data length of a transaction packet requested to be returned by each of the transaction sending devices; The target interval duration required for forwarding the plurality of first transaction packets of the transaction sending device is determined accordingly according to the first data transmission link width, the second data transmission link width and the data length.

3. The flow control system according to claim 2, characterized in that: When the switching chip performs the function of determining the target interval duration required for forwarding the plurality of first transaction packets of the transaction sending device according to the first data transmission link width, the second data transmission link width and the data length, the switching chip is specifically configured as follows: Determining a length level of the data length; Matching the first data transmission link width, the second data transmission link width and the length level with a corresponding interval duration index table; The matched interval duration is determined as the target interval duration required for forwarding the plurality of first transaction packets of the corresponding transaction sending device.

4. The flow control system according to claim 1, characterized in that: The switching chip is further configured as: If the multiple forwarding interval durations all reach the corresponding target interval durations, the traffic is allocated to the first target transaction sending device; If the number of unreturned transaction packets corresponding to the plurality of transaction sending devices is less than the corresponding threshold, the traffic is allocated to the first target transaction sending device; If the forwarding interval duration corresponding to only one second target transaction sending device reaches the corresponding target interval duration, the traffic is allocated to the second target transaction sending device; If there is only one third target transaction sending device whose corresponding number of unreturned transaction packets is smaller than the corresponding threshold, the traffic is allocated to the third target transaction sending device.

5. The flow control system according to claim 1, characterized in that: The switching chip includes a routing module and a plurality of transceiver modules, the transceiver module includes a plurality of transceiver ports, and the transceiver ports are respectively connected to the routing module, the transaction sending device or the transaction receiving device; The first transceiver port as an in-chip port is configured to: transmit the first transaction packet to the routing module; The second transceiver port serving as an outgoing port is configured to receive the first transaction packet transmitted by the routing module and transmit the first transaction packet to the transaction receiving device.

6. The flow control system according to claim 5, characterized in that: It also includes a back pressure module, the back pressure module is connected to the routing module, and the transceiver port includes a buffer pool; The back pressure module is configured to: when the bandwidth of the first transceiver port is greater than the bandwidth of the second transceiver port, control the routing module to back pressure the first transaction packet to the buffer pool of the first transceiver port until the back pressure duration reaches a preset duration threshold; When the bandwidth of the first transceiver port is smaller than the bandwidth of the second transceiver port, the routing module is controlled to push the first transaction packet back to the buffer pool of the first transceiver port until the transaction data in the first transaction packet is complete; or, the routing module is controlled to push the first transaction packet back to the buffer pool of the first transceiver port until the length of the transaction data in the first transaction packet reaches a preset threshold.

7. The flow control system according to claim 6, characterized in that: The cache pool includes a private cache pool and a shared cache pool; The back pressure module is specifically configured to: control the routing module to back pressure the first transaction packet to the private buffer pool of the first transceiver port; if the private buffer pool is full and there is uncached transaction data, control the routing module to back pressure the uncached transaction data to the shared buffer pool.

8. The flow control system according to claim 1, characterized in that: Before executing the function of sending the plurality of first transaction packets to the switching chip, the transaction sending device is further configured to: Sending a first cache resource update instruction to the switching chip at a preset first time interval, and receiving a second cache resource update instruction sent by the switching chip at a preset second time interval; wherein the second cache resource update instruction is used to instruct the transaction receiving device to update a preset unit cache amount; According to the total unit cache amount of the switching chip, the number of remaining cache resources of the switching chip, the total first cache amount updated by the transaction sending device during the time period from the initial moment to the current moment, the total second cache amount updated by the transaction sending device during the single first time period, and the unit cache amount, it is determined whether the cache resources of the transaction sending device and the switching chip are abnormal; If abnormal, the cache resource is reset, and at the same time, based on the first cache resource update instruction, the switching chip is instructed to reset the cache resource; When the cache resource is reset, the function of sending the plurality of first transaction packets to the switch chip is executed.

9. The flow control system according to claim 8, characterized in that: The transaction sending device is further configured to: Get the preset number of cache resource partitions; The ratio of the total cache amount of the switching chip to the number of shares into which the cache resources are divided is calculated to obtain the total unit cache amount.

10. The flow control system according to claim 9, characterized in that: The transaction sending device is specifically configured as follows: respectively calculating a first ratio of the duration from the initial moment to the current moment to the second duration and a second ratio of the first duration to the second duration; Calculating respectively a first sum of x unit buffer amounts and a second sum of y unit buffer amounts; wherein x is the integer part of the first ratio, and y is the integer part of the second ratio; Multiplying the number of cache resource divisions by the total unit cache amount and then subtracting the resultant from the first total cache amount to obtain a first difference, and adding the first difference to the first total to obtain a third total; Multiplying the remaining number of cache resources by the total unit cache amount and then subtracting the resultant from the second total cache amount to obtain a second difference, and adding the second difference to the second total to obtain a fourth total; If the third total is smaller than the total unit cache amount and the fourth total is larger than the total unit cache amount, it is determined that the cache resources of the transaction sending device and the switching chip are abnormal.

11. A flow control method, characterized in that: Applied to the flow control system according to any one of claims 1 to 10, the flow control method comprises: The transaction sending device sends a plurality of transaction packets to the switching chip; wherein the transaction packets include data length information of the request return transaction; The switching chip respectively obtains the target interval time required for forwarding the multiple transaction packets of each transaction sending device, and obtains the number of transaction packets that are not returned to each transaction sending device; The switching chip counts the forwarding interval duration of each of the transaction packets. When multiple transaction sending devices correspond to the same target transaction receiving device, if multiple forwarding interval durations reach the corresponding target interval duration and the number of unreturned transaction packets of the corresponding multiple transaction sending devices is less than the corresponding preset threshold, the traffic is allocated to the target transaction sending device; wherein, the data length of the transaction requested to be returned in the transaction packet sent by the target sending device is the smallest.

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