Method for producing power component based on wide bandgap semiconductor, and power component

Abstract

According to a first aspect of the invention, a method for manufacturing a power structural element based on a wide bandgap semiconductor is proposed, in which a device wafer having a substrate is provided. One or more functional layers are formed on the substrate, and the one or more functional layers form the power structural element. At least one engineering layer is arranged between the functional layer and the substrate. According to the present invention arrangements, the substrate is completely removed from the device wafer by targeted removal of at least one engineered layer.

Description

Technical Field

[0001] The invention relates to a method for producing a power component based on a wide bandgap semiconductor, in particular a vertical power component. The invention also relates to a power component. Background Art

[0002] Semiconductors with wide band gaps (also referred to as wide band gap semiconductors or WBG semiconductors or WBGS) are semiconductor materials that have a larger band gap than conventional semiconductors. Conventional semiconductors, such as silicon, have band gaps in the range of 0.6-1.5 electron volts (eV), while wide band gap semiconductors have band gaps in the range of greater than 2 eV. Generally speaking, wide band gap semiconductors have electronic properties that are between those of conventional semiconductors and those of insulators.

[0003] Generally speaking, semiconductors with wide band gaps enable devices to operate at higher voltages, frequencies and temperatures than traditional semiconductor materials, such as silicon and gallium arsenide.

[0004] Typical wide bandgap semiconductors are silicon carbide (SiC) and gallium nitride (GaN).Many further wide bandgap semiconductors are known to those skilled in the art.

[0005] Transistors based on gallium nitride (GaN) offer the possibility of realizing components with a lower on-resistance at a higher breakdown voltage than similar components based on silicon or silicon carbide. GaN transistors are known primarily through so-called high electron mobility transistors (HEMTs), in which the current flows laterally on the substrate top side through a two-dimensional electron gas that forms the transistor channel. Such lateral structural elements can be produced by heteroepitaxial growth of functional GaN layers on silicon wafers.

[0006] For high breakdown voltages at low on-resistance per unit area, so-called vertical structural elements, in which the current flows from the substrate front to the substrate back, are more advantageous not only with regard to the structural size but also with regard to the electric field distribution within the component.

[0007] This cannot be demonstrated directly with heteroepitaxial GaN layers on silicon (Si), since an insulating intermediate layer (so-called buffer) is required to adapt the lattice mismatch between GaN and Si and to reduce the substrate curvature. The buffer itself is mechanically tensioned in such a way that it exactly compensates for the tension of the GaN layer at room temperature. However, since the buffer is an insulator, the current flow from the front side to the back side is prevented by the buffer. Although there are also native GaN substrates on which the required additional epitaxial GaN layers of the component can be grown without an insulating buffer, these native GaN substrates are small (typically 50 mm in diameter) and relatively expensive.

[0008] In order to reduce the In order to reduce the transistor price, it is advantageous to utilize the available heteroepitaxial GaN layers on a large silicon substrate. For this purpose, vertical structural elements are shown in the literature, for example, see Khadar et al. "Fully vertical GaN-on-Si power MOSFETs" (IEEE Electron Device Letters (2019)) or Zhang et al. "720-V / 0.35-mOhmcm^2 Fully Vertical GaN-on-Si Power Diodes by Selective Removal of Si Substrates and Buffer Layers" (IEEE Electron Device Letters (2018)). In the vertical structural elements manufactured in this way, the silicon substrate and the non-conductive buffer below the component are selectively removed so that the back side of the drift region of the component can be directly contacted.

[0009] Figure 1a ) shows the basic structure of such a component with an insulating buffer and a backside trench (here taking a trench MOSFET as an example). The backside trench is also called a backside cavity or a backside aperture or a notch. It should be understood that the possibility of providing such a conductive access to the back side of the drift region is not limited to this type of component, so that in principle any vertical power structure element can be produced by this technology.

[0010] For manufacturing, the following III-V nitride semiconductor layers (GaN except the buffer) are epitaxially grown on a silicon substrate 61 or, in general, on a carrier substrate: an insulating buffer 33, a highly doped contact semiconductor layer 34 with n-conductivity, a lowly doped drift layer 35 with n-conductivity, a p-conductivity body layer 36, and a highly doped n-conductivity source contact layer 37. The source contact layer 37 and the body layer 36 are penetrated by a channel (trench), the sidewalls and bottom of which are separated from the gate electrode 21 by the gate dielectric 22. The source contact layer 37 and the body layer 36 are connected by a source electrode 41, which is separated from the gate electrode 21 by the insulating layer 31.

[0011] On the back side, the silicon substrate and the buffer are removed by a back side trench 51, which ends in a highly conductive contact semiconductor layer 34. The contact semiconductor layer is contacted by a drain electrode 52 on the back side. In operation, by applying a gate voltage to the gate electrode 21, a conductive channel is formed in the body layer 16, through which a current flow from the source electrode 41 to the drain electrode 52 can be achieved. Figure 1a ), for the sake of simplicity, a transistor with three cells, i.e. three repeating structures, is shown. In a real transistor, typically there are a plurality of such cells and are therefore effectively connected in parallel. This can reduce the resistance of the component and increase the current carrying capacity. The typical active area is in the range of a few square millimeters, and the remaining GaN layer has a thickness of a few micrometers. This aspect ratio It is difficult to show in the figure. The drain electrode 52 may consist of multiple metal layers and may also include thickened metal. In the extreme case, the backside trench 51 may be completely filled with metal (not shown).

[0012] In the case of incompletely filled cavities, the described method produces membranes with a thickness in the micrometer range and lateral dimensions of several millimeters. In order to protect these fragile membranes during processing, the wafer can be glued on the front side to a carrier wafer 63 by means of a bonding layer 62 before the trenches 51 are produced in the silicon, see Figure 1b ). This process is hereinafter referred to as temporary bonding.

[0013] After the silicon has been removed and the described metal layers have been applied, the transistor chips are separated by means of sawing or laser cutting along so-called sawing roads or separation roads in order to produce the individual chips.

[0014] The membrane, consisting of the above-mentioned semiconductor and metal layers, has only limited stability. Handling, wafer handling and, in particular, separation of the wafer into individual chips by sawing or laser cutting can lead to deformation or cracking of the membrane, which can destroy or damage components or change parameters (such as threshold voltage). Summary of the invention

[0015] It can therefore be seen as an object of the present invention to provide a method for producing a power component based on a wide bandgap semiconductor (for example GaN or GaO) which can be advantageously processed with the aid of established construction and connection technologies (for example sintering for die bonding, wire bonding for front contacts or also embedding) and which has particularly low thermal and electrical resistances. For this purpose, a layer structure and a production method are proposed which in particular enable a vertical current flow in the power component even if the component is grown heteroepitaxially on an insulating substrate or using an insulating epitaxial intermediate layer. In this case, in contrast to the prior art, no cavities are generated which are disadvantageous with regard to thermal or electrical connection and with regard to the use of the established construction and connection technologies.

[0016] The membrane, consisting of the above-mentioned semiconductor and metal layers, has only limited stability. Handling, wafer handling and, in particular, separation of the wafer into individual chips by sawing or laser cutting can lead to deformation or cracking of the membrane, which can destroy or damage components or change parameters (such as threshold voltage).

[0017] By virtue of the complete removal of the substrate according to the invention, the semiconductor layer can be stabilized more effectively and more comprehensively in a subsequent process than in the case of a membrane.

[0018] According to a first aspect of the present invention, a method for manufacturing a power structure element based on a wide bandgap semiconductor is proposed, wherein a device wafer having a substrate is provided. One or more functional layers are constructed on the substrate, and the one or more functional layers construct the power structure element. At least one engineering layer is arranged between the functional layer and the substrate. According to the invention, the substrate is completely removed from the device wafer by targeted removal of at least one engineering layer.

[0019] Therefore, the present invention enables a method for stripping an active semiconductor layer from a substrate without destroying the substrate. Typically, the substrate accounts for a significant portion of the cost and can be reused with the method. In addition, the process can be significantly more advantageous because it requires fewer process steps than when the substrate is completely or partially removed from the back side.

[0020] For example, for GaN on so-called engineered substrates (eg QST wafers), this approach of completely removing the substrate can be implemented. This approach is also conceivable for gallium oxide (GaO) on foreign substrates.

[0021] By completely removing the substrate, parasitic resistances are reduced, in particular in the case of vertical power components, and the thermal connection to the circuit carrier is improved, so that this approach is also advantageous for lateral components.

[0022] Preferably, the applied layer is stabilized by means of a carrier layer, in particular a carrier wafer, before the substrate is removed. For this purpose, for example, a temporary bonding to a glass wafer or a silicon wafer can be performed. This advantageously ensures that the component is stabilized efficiently. By releasing the bonding layer, the carrier wafer can be removed in a simple manner, and the power component can be present in an already separated form and can be directly processed further.

[0023] Before the carrier wafer is removed, the device wafer can advantageously be bonded to a dicing tape. The invention thus further simplifies separation and further processing.

[0024] A particularly preferred embodiment of the method according to the invention comprises the following steps:

[0025] a. providing a device wafer (100) having a substrate (1), wherein one or more functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12) are formed on the substrate (1), wherein the one or more functional layers form the power structure element, and wherein at least one engineering layer (2, 3) is arranged between the functional layer (4, 5, 6, 7, 8, 9, 10, 11, 12) and the substrate (1),

[0026] b. constructing at least one trench (23) through the functional layer (4, 5, 6, 7, 8, 9, 10, 11, 12), wherein the trench (23) extends to the one or more engineering layers (2, 3);

[0027] c. applying a passivation portion (13) to the surface of the device wafer (100) and to the sidewalls of the at least one trench (23)

[0028] d. removing the passivation portion on the bottom (23') of the at least one trench (23), and constructing the recess (24) of the trench (23) in such a way that the one or more engineering layers (2, 3) are exposed;

[0029] e. applying a carrier wafer (15) to the surface of the device wafer (100), wherein the carrier wafer (15) has openings (25) at defined locations, through which an etching medium can be introduced into the trenches (23) and the recesses (24);

[0030] f. introducing an etching medium into the opening (25) and thereby removing at least one engineering layer (2, 3);

[0031] g. removing the device wafer (100) from the substrate (1),

[0032] h. Remove each power structure component.

[0033] In one possible embodiment, at least one engineering layer is designed as a silicon layer. The silicon layer can be removed by introducing an etching medium comprising xenon difluoride gas.

[0034] In another possible embodiment, at least one engineering layer is designed as a silicon dioxide layer. The silicon dioxide layer can be removed by introducing an etching medium comprising HF gas.

[0035] Preferably, after the device wafer has been removed from the substrate, any engineering layers and / or buffer layers that may still be present are removed, in particular by means of plasma etching.

[0036] After the device wafer has been removed from the substrate, one or more metallization layers can be applied to the exposed functional layer. In this way, for example, drain contacts can be produced efficiently when the power component is a MOSFET.

[0037] According to a second aspect of the invention, a power structure element based on a wide bandgap semiconductor is proposed, wherein the power structure element is produced according to the method according to the first aspect and is in particular configured as a power transistor or as a diode. Examples of power structure elements of this type are Schottky diodes, pn diodes, vertical diffusion MOSFETS (VDMOS), current aperture vertical electron transistors (CAVETs), vGroove vertical high electron mobility transistors or fin field effect transistors (FinFETs). Other examples are common to those skilled in the art.

[0038] In particular, the power components have GaN or GaO or SiC as functional semiconductor material, thereby enabling low losses, handling of high voltages, operation at high (ambient) temperatures, handling of higher frequencies and / or increased reliability, in particular in the case of switching regulators. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Embodiments of the present invention are described in detail with reference to the accompanying drawings.

[0040] FIG. 1 illustrates the fabrication of a GaN trench MOSFET according to the prior art.

[0041] FIG. 2 illustrates the fabrication of a vertical GaN MOSFET according to one possible embodiment of the present invention. DETAILED DESCRIPTION

[0042] In the following description of exemplary embodiments of the present invention, identical elements are denoted by identical reference numerals, wherein a repeated description of these elements is omitted where necessary. The figures merely schematically illustrate the subject matter of the present invention.

[0043] Figure 2a )-f)4 Taking the manufacture of GaN-MOSFET as a vertical power structural element as an example, an intermediate step in a possible process flow for realizing the invention a described herein is shown. First, a substrate 1 is provided, on which a plurality of layers are constructed. In the example shown, two so-called engineering layers 2 and 3 are constructed on the substrate 1. Above the engineering layers 2 and 3, a drain contact layer 4 and a GaN epitaxial drift layer 5 are arranged. Above the drift layer 5, a p-doped layer 6 of the semiconductor is arranged, and above the p-doped layer, an n-doped source layer 7 and an insulating layer 8 are arranged. 10 represents the power metallization of the structural element, 11 is the gate dielectric, and 12 is the gate electrode.

[0044] After processing the front side, a stabilizing metal layer 9 can optionally be applied. First, etching is performed along the sawing channel 23 through all functional layers, including the epitaxial layers 5 and 4, and the side walls and the surface are protected by means of the passivation 13. The passivation 13 is then opened at the bottom of the opening during a second etching, and the engineering layers 2 and 3 located below the passivation are etched through, so that a recess 24 is produced. In this case, the passivation 13 should not be removed at any other location along the flanks of the opening. Ideally, care should be taken to open the passivation in the area of ​​the contact pads on the wafer surface. Optionally, it is conceivable to carry out the etching process at another advantageous time point during the front side processing. And during the subsequent deposition the opening is protected, for example, by a mask.

[0045] In the next step ( Figure 2b )), a carrier wafer 15 is applied to the front side of the device wafer 100, for example, by means of a temporary bonding layer 14. The carrier wafer 15 and the bonding layer 14 have openings 25, 26, through which gas can enter the previously etched trenches 23, 24 of the device wafer 100. The openings 25, 26 can be designed, for example, as holes at the intersections of the sawing paths.

[0046] During the subsequent gas phase etching, the etching gas 40 is conducted through these openings 25, 26 into the trenches 23, 24 to the engineering layers 2, 3. The etching gas 40 and the material of the passivation 13 can be selected so that there is a very high etching selectivity between them. An example is silicon dioxide as a passivation, which is in the presence of xenon difluoride (XeF 2) is not etched. However, at the same time, at least one of the exposed engineering layers 2, 3 should be etched by the etching gas 40. Typically, GaN epitaxy is started on a thin silicon layer that is heated by XeF 2 Alternatively, the process can be reversed and an etching gas 40, such as hydrofluoric acid gas (HF gas), can be used to etch the SiO in the engineering layers 2, 3. 2 In this case, the passivation portion 13 can be selected as a polysilicon layer, which is not etched in HF gas. 2 Etching of silicon (layer 2) Figure 2c ) or in the process for etching SiO with HF gas 2 (Layer 3) Figure 2d ) is shown in .

[0047] The gas is then used in order to remove at least one of the engineering layers 2, 3 beneath the epitaxy between the openings in the device wafer 100. After complete removal, the device wafer 100 can be taken away from the substrate 1.

[0048] like Figure 2e ), the device wafer 100 is then flipped over to remove any layers that may still be present (in this example, the engineering layer 3) and the buffer layer (not shown) ( Figure 2e )). This can be done, for example, by means of plasma etching.

[0049] If the epitaxial drain layer 4 is exposed (see Figure 2f )),like Figure 2g ), a contact metal is applied as a metallization layer 16 and optionally a further metal layer for stabilization. The power structure element is now complete and the chips have been separated because the initial etching has reached the substrate 1. The device wafer 100 can now be turned over again and can be bonded to the dicing tape 17, see Figure 2h ). After the carrier wafer 15 is peeled off, the bonding layer 14 is removed. Then, the chips can be removed individually.

Claims

1. A method for producing a power structure component based on a wide bandgap semiconductor, wherein: A device wafer (100) having a substrate (1) is provided, wherein one or more functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12) are constructed on the substrate (1), the one or more functional layers constructing the power structure element, and wherein at least one engineering layer (2, 3) is arranged between the functional layer (4, 5, 6, 7, 8, 9, 10, 11, 12) and the substrate (1), characterized in that the substrate (1) is completely removed from the device wafer (100) by targeted removal of at least one engineering layer (2, 3).

2. The method according to claim 1, wherein: Before the substrate (1) is removed, the already applied layers (4, 5, 6, 7, 8, 9, 10, 11, 12) are stabilized by means of a carrier layer, in particular a carrier wafer (15).

3. The method according to claim 1 or 2, comprising the steps of: a. Providing a device wafer (100) having a substrate (1), wherein One or more functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12) are formed on the substrate (1), the one or more functional layers forming the power structure element, and at least one engineering layer (2, 3) is arranged between the functional layer (4, 5, 6, 7, 8, 9, 10, 11, 12) and the substrate (1), b. constructing at least one trench (23) through the functional layer (4, 5, 6, 7, 8, 9, 10, 11, 12), wherein the trench (23) extends to the one or more engineering layers (2, 3); c. applying a passivation portion (13) to the surface of the device wafer (100) and to the sidewalls of the at least one trench (23) d. removing the passivation portion on the bottom (23') of the at least one trench (23), and constructing the recess (24) of the trench (23) in such a way that the one or more engineering layers (2, 3) are exposed; e. applying a carrier wafer (15) to the surface of the device wafer (100), wherein the carrier wafer (15) has openings (25) at defined locations, through which an etching medium can be introduced into the trenches (23) and the recesses (24); f. introducing an etching medium into the opening (25) and thereby removing at least one engineering layer (2, 3); g. removing the device wafer (100) from the substrate (1), h. Remove each power structure component.

4. The method according to any one of claims 1 to 3, wherein: At least one first engineering layer (2) is configured as a silicon layer and the first engineering layer (2) is removed by means of an etching medium comprising xenon difluoride gas.

5. The method according to any one of claims 1 to 4, wherein: At least one second engineering layer (3) is formed as a silicon dioxide layer and the second engineering layer (3) is removed by means of an etching medium comprising HF gas.

6. The method according to any one of claims 2 to 5, wherein: The carrier wafer (15) is connected to the surface of the device wafer (100) by means of a bonding layer (14).

7. The method according to any one of claims 1 to 6, wherein: After the device wafer (100) has been removed from the substrate (1), any engineering layers (2, 3) and / or buffer layers still present are removed, in particular by means of plasma etching.

8. The method according to any one of claims 1 to 7, wherein: After the device wafer (100) has been removed from the substrate (1), one or more metallization layers (16) are applied to the exposed functional layer (4).

9. The method according to any one of claims 2 to 8, wherein: After the device wafer (100) has been removed from the substrate (1), the carrier wafer (15) and, if necessary, the bonding layer (14) are removed.

10. The method according to any one of claims 2 to 10, wherein: The device wafer (100) is bonded to a dicing tape (17) before removing the carrier wafer (15).

11. A power structure element based on a wide bandgap semiconductor, wherein: The power component is produced according to the method according to any one of claims 1 to 10 and is in particular designed as a power transistor or as a diode.

12. The power structure element according to claim 11, wherein: The power structure element includes GaN or GaO or SiC as functional semiconductor material.

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