SiP microsystem chip internal single particle fault transmission test method

Abstract

The application discloses a kind of SiP microsystem chip internal single particle fault transmission test methods, belong to integrated circuit single particle effect test technical field.The method of the present application is analyzed to each key node of SiP core processing chip FPGA and SiP single particle soft error transmission path, the single particle detection of FPGA sensitive module is carried out by simulation, the influence of single particle fault generated by FPGA under different operating modes on SiP device operating state is obtained, and the test data of single particle flip and single particle function interruption of each sensitive module of FPGA chip, the single particle cross section of each sensitive module of FPGA is calculated, the problem that SiP single particle effect ground test is not accurate, fault transmission path and data are difficult to obtain is solved, and basis is provided for SiP single particle ground simulation test.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit single event effect test, in particular to a SiP microsystem chip internal single event upset transmission test method. BACKGROUND

[0002] System in package (SiP) is a microsystem that adopts three-dimensional stacked packaging technology to package multiple electronic components and chips with different functions into one whole chip which can realize various operation functions. It mainly includes field programmable gate array (FPGA), configuration chip, memory chip, digital signal processor (DSP) and the like. Due to its high performance, miniaturization, light weight and fast iteration, it is widely used in the field of aerospace.

[0003] However, under the influence of space radiation environment, when a single high-energy particle is incident on the SiP chip, a certain number of electron-hole pairs are generated in the chip due to energy deposition. The charges are collected to the sensitive nodes in the process of movement, resulting in instantaneous change of current. The transient current propagates in the circuit, causing single event effect of the SiP core chip FPGA, and further causing SiP data operation error, program runaway and even device burnout and the like. In order to study the single event upset transmission characteristics of the internal core operation chip (FPGA) of SiP device and carry out anti-radiation reinforcement design for the sensitive modules inside SiP, ground simulation irradiation test needs to be carried out.

[0004] At present, in the field of integrated circuit chip single event effect test, the single event test method of single integrated circuit chip is relatively mature, but due to the diversity of the packaged chips in SiP device and the particularity of its work, there is no single event upset transmission test method for the internal single event upset of SiP device. When SiP is working normally, its core chip needs to interact with other component-level chips, resulting in intermittent signal operating voltage, which is equivalent to intermittent radiation bias. Therefore, the single event effect sensitivity of the working chip in SiP is different from the static bias condition of a single device, and due to the transmission of single event upset of the core chip in SiP device, it will cause abnormal work of other chips, so the traditional independent chip single event test method cannot be used to evaluate the anti-single event capability of SiP device.

[0005] Therefore, it is necessary to further study the SiP microsystem chip internal single event upset transmission test method, test the single event latch-up (SEL), single event functional interrupt (SEFI) and single event upset (SEU) of the FPGA chip inside SiP device, and test the transmission of single event upset of the FPGA chip in SiP device, so as to provide basis for SiP single event ground simulation test. SUMMARY

[0006] The problem to be solved by the present application is to provide a SiP microsystem chip internal single particle fault transmission test method, which solves the problems of inaccurate ground test of SiP single particle effect, and difficult to obtain fault transmission path and data.

[0007] The present application adopts the following technical scheme: a SiP microsystem chip internal single particle fault transmission test method, comprising the following steps:

[0008] Step S1, power on and configure the SiP device, so that the SiP device is in a normal working state, and the working current of the internal core processing chip FPGA of the SiP device is monitored;

[0009] Step S2, analyze the structural characteristics of the core processing chip FPGA, divide and combine the single particle sensitive circuit modules inside the SiP device, configure four working modes of the core processing chip FPGA, and establish a single particle fault transmission model of the core processing chip FPGA in the SiP device;

[0010] Step S3, analyze the sensitive module key nodes of the core processing chip FPGA, and perform single particle detection on the FPGA sensitive module;

[0011] Step S4, single particle soft error propagation process analysis, analyze the influence of single particle faults generated under each working mode of the core processing chip FPGA on the entire SiP working state;

[0012] Step S5, simulate error injection, respectively inject single particle soft errors into each sub-module inside the core processing chip FPGA through simulation means, and detect fault transmission results by a test system;

[0013] Step S6, single particle irradiation is performed on the core processing chip FPGA to verify the feasibility of the test method, analyze the single particle fault transmission characteristics of the core processing chip FPGA of the SiP device, and calculate the single particle cross section of each sensitive module of the FPGA.

[0014] Preferably, in step S1, the SiP device comprises components: a core processing chip FPGA, a configuration chip, a storage chip and an auxiliary operation refresh chip; when the SiP device is in a normal working state, the core processing chip FPGA performs data interaction with the configuration chip through a BPI configuration mode, performs data interaction with the storage chip through a DDR2 controller, performs data interaction with the auxiliary processing refresh chip and an external controller through SRIO and EMIF interfaces, and performs data interaction with an upper computer through UART and GPIO ports.

[0015] Preferably, in step S2, the core processing chip FPGA is of SRAM type structure, and the underlying resources include sub-modules: block memory, programmable logic block, input / output module, arithmetic circuit and digital clock management unit.

[0016] Firstly, the SiP device internal single event sensitive circuit module is divided, the programmable logic block is configured as a DRAM memory and a FF flip-flop chain, and the core processing chip FPGA works in four different working modes: in the first working mode, the block memory, programmable logic block and arithmetic circuit resources in the FPGA are in a running state; in the second working mode, the programmable logic block in the FPGA is in an inactive state; in the third working mode, the block memory is in an inactive state, and the programmable logic block is configured as a DRAM memory; and in the fourth working mode, the block memory is in an inactive state, and the programmable logic block is configured as a FF flip-flop chain.

[0017] Then, a single event fault transmission model of the core processing chip FPGA in the SiP device is established, including the following sub-steps:

[0018] Step S2.1, analyzing the internal resources of the programmable logic block, each programmable logic block is connected to a switch matrix, each switch matrix contains a pair of Slices, SliceL and SliceM, respectively, and the Slices connected by each programmable logic block form a column, and each Slice in the column has an independent carry chain;

[0019] The switch matrix is used to access a general routing matrix, and the two Slices of each switch matrix are not directly connected to each other, and each Slice contains four logic function generators, four storage elements, a multifunction multiplexer and a carry logic, which are used for logic, arithmetic and ROM function operations, and the four logic function generators form a LUT lookup table; some Slices store data using distributed RAM and perform data shifting using 32-bit registers;

[0020] Step S2.2, configuring the programmable logic block as different logic circuits by Verilog programming, including a LUT resource chain, a FF flip-flop chain and a DRAM memory; the LUT resource chain contains all resources of SliceL and SliceM, the FF flip-flop chain contains D flip-flops in Slice resources, and the DRAM memory only uses SliceM;

[0021] Step S2.3, configuring the block memory, arithmetic circuit and input / output module, so that each module independently completes the function of a sub-circuit.

[0022] Preferably, in step S3, the sensitive module key nodes of the core processing chip FPGA include: FPGA internal block memory nodes, programmable logic block nodes, FF flip-flop nodes, DRAM memory nodes, and transmission nodes for data interaction between the FPGA chip and other components; node single event soft error detection is set at each sensitive module key node to perform node error detection and record error transmission information.

[0023] Preferably, in step S4, the single event soft error propagation path of the core processing chip FPGA in each working mode is as follows:

[0024] Path 1: In the first working mode, the single event soft error propagation path is: configuration chip→block memory→programmable logic block→operation circuit→input / output module→auxiliary processing refresh chip and host computer.

[0025] The core processing chip FPGA reads the configuration data in the configuration chip through the BPI mode, temporarily stores the data in the block memory, transmits the data in the block memory to the programmable logic block and the auxiliary operation refresh chip for operation processing, transmits the operation result to the storage chip through the GPIO interface, transmits the operation result to the auxiliary operation refresh chip through the EMIF interface, and transmits the operation result to the host computer through the UART interface; real-time detection of single event errors generated by each node and the influence of errors generated by each resource on the next level of resources and other chips;

[0026] Path 2: In the second working mode, on the basis of the first working mode, the programmable logic block in the core processing chip FPGA is controlled not to work, the influence of the block storage module fault on the other modules of the FPGA and the entire SiP chip is studied, and the single event soft error propagation path is: configuration chip→block memory→operation circuit→input / output module→auxiliary processing refresh chip and host computer.

[0027] Path 3: In the third working mode, on the basis of the first working mode, the block memory in the core processing chip FPGA is controlled not to work, the programmable logic block is configured as DRAM, the influence of the DRAM module fault on the other modules of the FPGA and the entire SiP chip is studied, and the single event soft error propagation path is: configuration chip→DRAM→operation circuit→input / output module→auxiliary processing refresh chip and host computer.

[0028] Path 4: In the fourth working mode, on the basis of the third working mode, the programmable logic block is configured as a FF flip-flop chain, the influence of the D flip-flop module fault on the other modules of the FPGA and the entire SiP chip is studied, and the single event soft error propagation path is: configuration chip→FF flip-flop chain→operation circuit→input / output module→auxiliary processing refresh chip and host computer.

[0029] Preferably, in step S5, before the irradiation test, the BRAM module, the FF flip-flop chain module and the DRAM module in the core processing chip FPGA are injected with single event soft errors by simulation means, to obtain the error times, error addresses and current change of each sub-module.

[0030] Preferably, in step S6, the core processing chip FPGA is irradiated with single particles to perform single particle locking, single particle function interruption, single particle flip-flop and single particle soft error fault transmission test in the SiP device, to sequentially obtain the single particle flip-flop times of the programmable logic block, the FF flip-flop, the block memory of the FPGA in four working modes and the single particle function interruption times of the UART interface circuit, and obtain the single particle fault transmission characteristic test result.

[0031] Further, after the SiP device completes the heavy ion test, the single particle fault transmission characteristic test result is uploaded to the upper computer, the influence of the core processing chip FPGA in different working modes under irradiation conditions on the SiP operation condition is analyzed, the single particle cross section of each sensitive module of the FPGA is calculated, and a basis is provided for the single particle ground simulation test of the SiP.

[0032] Compared with the prior art, the above technical scheme has the following technical effects:

[0033] 1. The single particle fault transmission test method for the SiP microsystem chip provided by the application can simply and effectively realize the single particle fault transmission test of the SiP device, instead of the independent test of each component level chip of the SiP device in the prior art.

[0034] 2. The method can obtain the influence of the single particle fault generated by the FPGA in different working modes on the working state of the SiP device, and the test data of the single particle flip-flop and the single particle function interruption of each sensitive module of the FPGA chip, through the analysis of each key node and transmission path of the core processing chip FPGA of the SiP, saves the irradiation beam current machine time, avoids repeated tests, and provides a basis for the subsequent device radiation hardening. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 The SiP microsystem chip internal single particle fault transmission test method flowchart of the application;

[0036] Figure 2 The SiP chip function block diagram of the embodiment of the application;

[0037] Figure 3 The CLB configuration circuit diagram of the embodiment of the application;

[0038] Figure 4A circuit diagram for configuring a flip-flop chain in an embodiment of the present application;

[0039] Figure 5 A circuit diagram for configuring a DRAM in an embodiment of the present application;

[0040] Figure 6 A block diagram of a SiP fault transmission path in an embodiment of the present application;

[0041] Figure 7 A simulation fault injection diagram in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the application are further described in detail below in combination with the drawings, and the described embodiments are only a part of the embodiments involved in the present application. All non-innovative embodiments of other researchers in the field on the basis of the embodiments belong to the protection scope of the present application. Meanwhile, the step numbers in the embodiments are only set for the convenience of description and explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0043] In an embodiment of the present application, as shown in Figure 1 A SiP microsystem chip internal single particle fault transmission test method mainly includes the following steps:

[0044] S1, power on the SiP chip, and distribute work tasks to the SiP according to the SiP working characteristics.

[0045] The SiP device selected in the embodiment is composed of a core processing chip FPGA, a configuration chip PROM, a storage chip DDR2 and an auxiliary operation refresh chip DSP.

[0046] Specifically, the working flow of the SiP device in the embodiment is as shown in Figure 2 The SiP device realizes power-on control and monitoring of the working voltage and working current of each component-level chip by means of two LTM4644, and performs automatic power-off operation on the SiP when a large current is detected (when a single particle lock is detected) during irradiation, so as to prevent the SiP chip from being burnt out.

[0047] When the SiP device is working normally, the component-level FPGA chip is in a core position, and the core processing chip FPGA can interact with the configuration chip, the storage chip and the auxiliary processing refresh chip, and realize monitoring of the working current of the FPGA chip.

[0048] Preferably, the SiP realizes the data interaction between the FPGA and the PROM through the BPI configuration mode, realizes the data interaction between the FPGA and the DSP and the external controller through the SRIO and EMIF interfaces, realizes the data interaction between the FPGA and the DDR2 through the DDR2 controller, and realizes the data interaction between the FPGA and the host computer through the UART and GPIO ports.

[0049] S2, analyzing the structural features of the core processing chip FPGA of the SiP device and dividing sensitive circuit modules.

[0050] In order to establish the single event fault transmission model of the SiP core processing chip in the SiP, the structure inside the FPGA needs to be analyzed, and the single event sensitive circuits inside are divided and combined.

[0051] It needs to be particularly pointed out that the core processing chip FPGA used in the SiP device in the application is of an SRAM type structure, and the underlying resources thereof mainly include block memories (BRAMs), programmable logic blocks (CLBs), input / output modules (I / O Blocks), operation circuits (adders and multipliers), and digital clock management units (CMTs). The CLB is the main logic resource for realizing the timing circuit and the combination circuit, and the single event fault of the FPGA mainly occurs in the BRAM and the CLB, so the focus of the research on the fault transmission of the FPGA is to study the transmission path of the CLB first. The CLB can be configured into a DRAM memory and an FF flip-flop chain, so that the core processing chip FPGA is configured into four different working modes, and the fault transmission characteristics thereof are further researched.

[0052] Specifically, the four mode working states of the core processing chip FPGA are as follows: the mode 1 makes all the resources in the FPGA such as the BRAM, the CLB, and the operation circuit in a running state; the mode 2 makes the CLB in the FPGA in a non-working state; the mode 3 makes the BRAM in a non-working state and configures the CLB into a DRAM memory; and the mode 4 makes the BRAM in a non-working state and configures the CLB into an FF flip-flop chain.

[0053] Firstly, the internal resources of the CLB are analyzed, and the CLB configuration circuit diagram of the embodiment is as shown in Figure 3 Each CLB is connected to a switch matrix (GMR) that can access a general routing matrix, and includes a pair of Slices, the two Slices are not directly connected to each other, each Slice is organized into a column, and each Slice in the column has an independent carry chain.

[0054] For each CLB, the Slice at the bottom of the CLB is labeled SLICE(0) and the Slice at the top of the CLB is labeled SLICE(1). Each Slice contains four logic function generators (i.e., LUTs), four storage elements, a multipurpose multiplexer, and carry logic. All Slices perform logic, arithmetic, and ROM function operations through these elements. In addition, some Slices support two additional functions: storing data in distributed RAM and shifting data with 32-bit registers.

[0055] Secondly, according to the diversity of Slice functions, the CLB is configured as different logic circuits by Verilog programming, including LUT resource chain (including all resources in Slice L and Slice M), FF trigger chain (D trigger in Slice resource), and DRAM memory (only using Slice M).

[0056] The FF trigger chain configuration circuit diagram of the embodiment is shown in Figure 4 The DRAM configuration circuit diagram is shown in Figure 5

[0057] Finally, in addition to the CLB module, there are BRAM storage modules, operation modules, and IO port output modules, the functions and logic circuits of the three are single, so they do not need to be configured as multiple circuits like CLB, but only need to ensure that each module is configured as a sub-circuit that can independently complete the function.

[0058] S3, sensitive module key node analysis of SiP core processing chip FPGA.

[0059] According to the division of the FPGA internal circuit in step S2, a node single event upset detection function needs to be set in each sub-module to realize single event detection of the FPGA sensitive module, including BRAM node, CLB node, FF trigger node, DRAM node in the FPGA, and transmission node for data interaction between the FPGA chip and other chips.

[0060] The input and output ports of each sub-circuit in step S2 are tested by writing a test program, and error transmission information is recorded.

[0061] S4, SiP single event soft error propagation process analysis.

[0062] After the FPGA internal circuit and key nodes are configured, the FPGA is configured in four different working states to analyze the influence of single event faults generated in each mode on the working state of the entire SiP. The nodes inside and outside the FPGA are connected, and all component-level chips in the SiP are in working condition, with four working modes and transmission paths:​

[0063] Mode 1: In this mode, all resources in FPGA are used, so it is the most complete test path. The SiP fault transmission path is shown in Fig. 1, PROM BRAM CLB operation circuit IO interface DSP and host computer. Figure 6

[0064] First, FPGA reads the configuration data in PROM by BPI mode, and temporarily stores the data in BRAM; then, the data in BRAM is transmitted to CLB and DSP operation module for simple operation processing.

[0065] Second, the operation result is transmitted to DDR2 by means of GPIO interface, to DSP by means of EMIF interface, and to host computer by means of UART interface.

[0066] Finally, the single event error generated by each node is detected in real time, and the influence of the error generated by each resource on the next level resource and other chips is detected.

[0067] In the whole process, all resources of FPGA are used, including BRAM, CLB, DSP operation module and IO interface, and the resource utilization rate reaches 90%.

[0068] Mode 2: In the transmission path of mode 1, the CLB link is removed, so that the CLB in FPGA does not work, that is, the influence of BRAM error on operation resource, interface circuit and other chips is studied, and the transmission path is: PROM BRAM operation circuit IO interface DSP and host computer.

[0069] Mode 3: In the transmission path of mode 1, FPGA is in abnormal working state, CLB of FPGA is configured as DRAM resource, and runs simultaneously with DSP operation resource, and the influence of error generated by DRAM module of CLB on operation module, IO interface and other chips is observed, and the transmission path is: PROM DRAM operation circuit IO interface DSP and host computer.

[0070] Mode 4: On the basis of mode 3, the CLB resource of FPGA is configured as FF flip-flop chain, and the influence of single event error of D flip-flop on operation module, IO interface and other chips is observed, and the transmission path is: PROM FF flip-flop chain operation circuit IO interface DSP and host computer.

[0071] S5, verify the feasibility of the test system by means of simulation error injection.

[0072] ​Before the irradiation test, the single event soft errors are injected into the BRAM module, FF trigger chain module and DRAM module in the FPGA by simulation means, and the test system is used to detect the fault transmission result, so as to verify whether the designed test system and test method can meet the test requirements. If the simulation test is passed, the heavy ion test is carried out, and then step S6 is entered, otherwise step S3 is returned.

[0073] The single event fault injection diagram of the SiP device under mode 1 operation is as shown in the figure. Figure 7 The single event soft errors are injected into the BRAM module, FF trigger chain module and DRAM module in the FPGA by simulation means, and the test system is used to detect the fault transmission result.

[0074] As can be seen from the figure, the test system has captured the error times, error addresses and current change of the BRAM module and DRAM (CLB) module. Since irradiation is not carried out, the fault has not caused the entire SiP to be in an abnormal working state during transmission, which meets the design requirements.

[0075] S6, the SiP device core processing chip is irradiated and tested to verify the feasibility of the test method and analyze the single event fault transmission characteristics of the SiP core processing chip.

[0076] The single event flip-flop times of the CLB, FF trigger, BRAM and other modules of the FPGA and the single event function interruption times of the UART interface circuit under four working modes are tested in turn, and the test results are as shown in Table 1:

[0077] Table 1 FPGA fault transmission test results

[0078]

[0079] According to the test results, it is found that no single event lock is generated under all working modes; under the same LET value, the single event soft error generated under working mode 1 is the most, and has the greatest impact on the running state of the SiP, and the CLB module in the FPGA generates the most single event errors, while the operation module and the POR circuit do not generate single event effects.

[0080] Further, after the SiP device completes the heavy ion test, the test data is uploaded to the host computer, and according to the test results, the influence of the different working modes of the FPGA on the running conditions of the SiP under irradiation conditions is analyzed, and finally the single event cross section of each sensitive module of the FPGA is calculated, and the cross section is as shown in Table 2:

[0081] Table 2 Single event cross section of FPGA

[0082]

[0083] The results of Table 2 show that in the working mode 1, the single particle cross section is maximum, a large number of single particle soft errors are generated in the FPGA, and the single particle soft errors make the SiP in an abnormal working state in the process of propagation; and the single particle errors generated in the mode 2, the mode 3 and the mode 4 have less influence on the SiP, the SiP will process data according to the fault result of the FPGA, and all are in a normal working state.

[0084] In conclusion, the SiP microsystem chip internal single particle fault transmission test method provided by the application solves the problems that the SiP single particle effect ground test is inaccurate, the fault transmission path and data are difficult to obtain, realizes the single particle locking (SEL), single particle function interruption (SEFI) and single particle flip (SEU) test of the core chip FPGA of the SiP device, and the fault transmission test of the single particle soft error of the FPGA chip in the SiP device, and provides a basis for the SiP single particle ground simulation test.

[0085] The above only describes the preferred embodiments of the application, and it should be noted that for those skilled in the art, some improvements and refinements can be made without departing from the principles of the application, and these improvements and refinements should also be considered as the protection scope of the application.

Claims

1. A method for testing single-event fault propagation within a SiP microsystem chip, characterized in that, Includes the following steps: Step S1: Power on and configure the SiP device to ensure it is in normal working condition, and monitor the operating current of the FPGA chip, the core processing chip inside the SiP device. Step S2: Analyze the structural characteristics of the core processing chip FPGA, divide and combine the single-event sensitive circuit modules inside the SiP device, configure the four working modes of the core processing chip FPGA, and establish a single-event fault transmission model of the core processing chip FPGA in the SiP device. The core processing chip FPGA has an SRAM-type structure, and its underlying resources include sub-modules: block memory, programmable logic blocks, input / output modules, arithmetic circuits, and digital clock management unit; The internal single-event sensitive circuit module of the SiP device is partitioned, and the programmable logic block is configured as DRAM memory and FF flip-flop chain, so that the core processing chip FPGA can work in four different working modes: In the first working mode, the block memory, programmable logic block and arithmetic circuit resources in the FPGA are all in the running state; in the second working mode, the programmable logic block in the FPGA is in the non-working state; in the third working mode, the block memory is in the non-working state, and the programmable logic block is configured as DRAM memory; in the fourth working mode, the block memory is in the non-working state, and the programmable logic block is configured as FF flip-flop chain. Establish a single-event fault propagation model for the core processing chip FPGA within a SiP device, including the following sub-steps: Step S2.1: Analyze the internal resources of the programmable logic block. Each programmable logic block is connected to a switch matrix. Each switch matrix contains a pair of slices, namely SliceL and SliceM. The slices connected to each programmable logic block are organized into a column. Each slice in the column has an independent carry chain. Step S2.2: Configure the programmable logic block into different logic circuits using Verilog programming, including a LUT resource chain, an FF flip-flop chain, and a DRAM memory; the LUT resource chain includes all resources of SliceL and SliceM, the FF flip-flop chain includes D flip-flops in the Slice resources, and the DRAM memory only uses SliceM; Step S2.3: Configure the block memory, arithmetic circuit and input / output module so that each module can independently complete the sub-circuit function; Step S3: Analyze the key nodes of the sensitive modules of the core processing chip FPGA and perform single-event detection of the sensitive modules of the FPGA. Step S4: Single-event soft error propagation process analysis, analyzing the impact of single-event faults generated in each working mode of the core processing chip FPGA on the overall SiP working state; The single-event soft error propagation path of the core processing chip FPGA in each operating mode is as follows: Path 1: First working mode, the single-event soft error propagation path is: configuration chip → block memory → programmable logic block → arithmetic circuit → input / output module → auxiliary processing refresh chip and host computer; The core processing chip FPGA reads the configuration data from the configuration chip through BPI mode, temporarily stores it in the block memory, transmits the data in the block memory to the programmable logic block and the auxiliary operation refresh chip for operation and processing, transmits the operation results to the storage chip through the GPIO interface, transmits the operation results to the auxiliary operation refresh chip through the EMIF interface, and transmits them to the host computer through the UART interface. Real-time detection of single-event errors generated by each node, and the impact of errors generated by each resource on next-level resources and other chips; Path 2: Second working mode. Based on the first working mode, the programmable logic block in the control core processing chip FPGA is not working. The impact of block memory module failure on other modules of FPGA and the entire SiP chip is studied. The single-event soft error propagation path is: configuration chip → block memory → arithmetic circuit → input / output module → auxiliary processing refresh chip and host computer. Path 3: The third working mode, based on the first working mode, controls the block memory in the core processing chip FPGA to be inactive, and configures the programmable logic block as DRAM. The impact of DRAM module failure on other FPGA modules and the entire SiP chip is studied. The single-event soft error propagation path is: configuration chip → DRAM → arithmetic circuit → input / output module → auxiliary processing refresh chip and host computer. Path 4: Fourth working mode. Based on the third working mode, the programmable logic block is configured as an FF flip-flop chain. The impact of D flip-flop module failure on other FPGA modules and the entire SiP chip is studied. The single-event soft error propagation path is: configuration chip → FF flip-flop chain → arithmetic circuit → input / output module → auxiliary processing refresh chip and host computer. Step S5: Simulate and inject errors. Single-event soft errors are injected into each sub-module inside the core processing chip FPGA using simulation methods, and the fault transmission results are detected using a test system. Step S6: Irradiate the core processing chip FPGA with single-event irradiation to verify the feasibility of the test method, analyze the single-event fault transmission characteristics of the core processing chip FPGA of SiP device, and calculate the single-event cross section of each sensitive module of FPGA.

2. The method for testing single-event fault propagation within a SiP microsystem chip according to claim 1, characterized in that, In step S1, the SiP device includes components: a core processing chip FPGA, a configuration chip, a storage chip, and an auxiliary operation and refresh chip; When the SiP device is in normal working condition, the core processing chip FPGA interacts with the configuration chip through the BPI configuration mode, interacts with the memory chip through the DDR2 controller, interacts with the auxiliary processing refresh chip and external controller through the SRIO and EMIF interfaces, and interacts with the host computer through the UART and GPIO ports.

3. The method for testing single-event fault propagation within a SiP microsystem chip according to claim 1, characterized in that, The switch matrix is ​​used to access the general wiring matrix. The two slices of each switch matrix are not directly connected to each other. Each slice contains four logic function generators, four storage elements, a multi-function multiplexer, and carry logic for logic, arithmetic, and ROM function operations. The four logic function generators form a LUT lookup table. Some slices use distributed RAM to store data and 32-bit registers to shift data.

4. The method for testing single-event fault propagation within a SiP microsystem chip according to claim 3, characterized in that, In step S3, the key nodes of the sensitive modules of the core processing chip FPGA include: FPGA internal block memory nodes, programmable logic block nodes, FF flip-flop nodes, DRAM memory nodes, and transmission nodes for data interaction between the FPGA chip and other components; single-event soft error detection is set at each key node of the sensitive module to perform node error detection and record error transmission information.

5. The method for testing single-event fault propagation within a SiP microsystem chip according to claim 1, characterized in that, In step S5, before conducting the irradiation test, single-event soft errors are injected into the BRAM module, FF flip-flop chain module, and DRAM module inside the core processing chip FPGA using simulation methods to obtain the error count, error address, and current change of each sub-module.

6. The method for testing single-event fault propagation within a SiP microsystem chip according to claim 5, characterized in that, In step S6, the core processing chip FPGA is subjected to single-event irradiation to perform single-event lockout, single-event interrupt, single-event flip, and single-event soft error fault propagation tests within the SiP device. The number of single-event flips of the FPGA's programmable logic blocks, FF flip-flops, and block memory, and the number of single-event interrupts of the UART interface circuit are obtained sequentially under four operating modes to obtain the single-event fault propagation characteristic test results.

7. The method for testing single-event fault propagation within a SiP microsystem chip according to claim 6, characterized in that, After the SiP device completes the heavy ion test, the test results of the single-particle fault transport characteristics are uploaded to the host computer. The influence of different working modes of the core processing chip FPGA under irradiation conditions on the SiP operating conditions is analyzed, and the single-particle cross section of each sensitive module of the FPGA is calculated to provide a basis for SiP single-particle ground simulation test.

Images