Overlay mark placement method

Abstract

The invention discloses an overlay mark placement method, which comprises the following steps of: 1, determining a distribution structure of crystal grains in an exposure area; step 2, performing lattice division on each crystal grain according to the distribution structure of the crystal grains to obtain a lattice area of each crystal grain; and step 3, grouping the photomasks according to the process layers. And 4, selecting a plurality of lattice point areas from the crystal grains of the photomask corresponding to each group of process layers as mark placement areas, and placing device area inner overlay marks in the mark placement areas, wherein the arrangement and the number of the overlay marks in the device area corresponding to the crystal grains meet the high-order compensation requirement of overlay errors. According to the method, the compensation value of the high-order correction overlay error of the device area can be accurately simulated and calculated, so that error compensation of the high-order compensation parameter of the overlay error in the exposure area can be prevented, and the yield of products, especially large-size crystal grain products, is improved.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for placing an overlay (OVL) mark. Background Art

[0002] Existing photolithography relies on scribe line (Scribe Line) overlay (OVL) marks to measure the overlay accuracy between chip layers. With the continuous advancement of technology and the continuous reduction of critical device dimensions, the overlay accuracy between layers has an increasingly important impact on the overall yield of the wafer. Especially for large-size chips, due to the large device area and few scribe lines, and because the scribe line OVL mark can only be placed in the scribe line, the number and distribution of the scribe line OVL mark will be limited by the scribe line. When the scribe line area is reduced, no matter how the scribe line OVL mark is laid out, it is impossible to accurately simulate and calculate the high-order corrected OVL compensation value in the device area, resulting in abnormal OVL high-order feedback.

[0003] For inline large-size die products, since the size of the exposure area (shot) is determined by the lithography machine and is usually fixed, when the size of the die increases, the area of ​​the cut lane around the die will become smaller, which will reduce the number of cut lane OVL marks placed on the cut lane and affect the distribution. In some products, the insufficient number of OVL marks will cause the high-order compensation values ​​corresponding to K12, K13 and K14 of OVL to continue to trend up; K12, K13 and K14 are high-order fitting parameters in light field level models such as the intra-field high order process correction (iHOPC) model.

[0004] After analysis, it was found that the existing OVL mark placement layout and insufficient number of OVL marks caused the K12 / 13 / 14 high-order OVL compensation project to be incorrectly compensated, causing the system alarm. The incorrect compensation caused the actual OVL impact to be about 3.5nm.

[0005] like Figure 1As shown, it is a normalized model uncertainty (nMU) data diagram of the overlay error measurement technology (Diffraction-Based overlay, DBO) based on diffraction light detection measured for the overlay mark placed by the existing overlay mark placement method; it can be seen that six grains 102 are arranged on the exposure area 101, and the peripheral side of the grain 102 has a cutting road 103, and a plurality of cutting road overlay marks 104 are arranged on the cutting road 103. Figure 1 The total number of overlay marks shown is 13.

[0006] The nMU data is two-dimensional data. The nMU data corresponding to each coordinate is nMU(x, y). The smaller the nMU data, the less noise it means, and the more accurate the measurement result of the corresponding overlay mark. Usually, the corresponding specification range (spec) is less than 1. It can be seen that the maximum value of nMU in the x direction, that is, nMU max(x), is 2.177, and the maximum value of nMU in the y direction, that is, nMU max(y), is 0.984. Therefore, nMU max(x) is greater than 1, which does not meet the specification requirements.

[0007] like Figure 2 As shown, it is a vector distribution diagram of the overlay deviation after overlay compensation of the overlay mark placed by the existing overlay mark placement method; in the exposure area 101, the arrow line 105 is used to represent the corresponding overlay deviation. In the X direction, 99.7% of the overlay deviation reaches 3.47nm, so the actual OVL impact caused by the wrong compensation is about 3.5nm. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a method for placing overlay marks, which can accurately simulate and calculate the compensation value of the high-order corrected overlay error of the device area, thereby preventing the erroneous compensation of the high-order compensation parameters of the overlay error inside the exposure area, and improving the yield of products, especially large-size grain products.

[0009] In order to solve the above technical problems, the present invention provides a method for placing an overlay mark, comprising the following steps:

[0010] Step 1: Determine the distribution structure of grains in the exposure area.

[0011] Step 2: divide each of the crystal grains into grid points according to the distribution structure of the crystal grains to obtain the grid point area of ​​each of the crystal grains.

[0012] Step 3: Group the masks according to the process layers.

[0013] Step 4: Select a plurality of the grid areas in the grains of the mask corresponding to each group of the process layers as mark placement areas and place device area (in cell) overlay marks in the mark placement areas, and the arrangement and number of the device area overlay (in cell OVL, ICOVL) marks corresponding to the grains meet the high-order compensation requirements of the overlay error.

[0014] A further improvement is that, in step 1, the distribution structure of the grains includes an X-direction distribution and a Y-direction distribution.

[0015] The X-direction distribution is obtained from the X-direction size of the exposure area, the X-direction size of the grain, and the X-direction size of the cutting road.

[0016] The Y-direction distribution is obtained by the Y-direction size of the exposure area, the Y-direction size of the grain, and the Y-direction size of the cutting road.

[0017] A further improvement is that the calculation formula for the number of columns of the distribution structure of the grains in the X direction is:

[0018] m=integer[(Rx-Sx) / (Cx+Sx)].

[0019] m represents the number of columns of the distribution structure of the grain in the X direction, integer() represents rounding down, Rx represents the X direction size of the exposure area, Sx represents the X direction size of the cutting road, and Cx represents the X direction size of the grain.

[0020] The calculation formula for the number of rows of the grain distribution structure in the Y direction is:

[0021] n=integer[(Ry-Sy) / (Cy+Sy)].

[0022] n represents the number of rows of the distribution structure of the grain in the Y direction, Ry represents the Y direction size of the exposure area, Sy represents the Y direction size of the cutting road, and Cy represents the Y direction size of the grain. A further improvement is that the X direction size of the grain is the sum of the X direction sizes of the prime chip and the seal ring on the periphery of the prime chip.

[0023] The Y-direction dimension of the crystal grain is the sum of the Y-direction dimensions of the main chip and the sealing ring around the main chip.

[0024] A further improvement is when the sealing ring is added at the factory end:

[0025] The calculation formula of the X-direction size of the grain is:

[0026] Cx=(C0x*0.9+2*22.2)μm;

[0027] The calculation formula of the Y-direction size of the grain is:

[0028] Cy=(C0y*0.9+2*22.2)μm;

[0029] Cox represents the X-direction dimension of the main chip;

[0030] Coy represents the Y-direction dimension of the main chip.

[0031] Or, when the sealing ring is added on the client side:

[0032] The calculation formula of the X-direction size of the grain is:

[0033] Cx=(C0x+2*24)*0.9μm;

[0034] The calculation formula of the Y-direction size of the grain is:

[0035] Cy=(C0y+2*24)*0.9μm.

[0036] A further improvement is that the maximum size of the exposure area in the X direction is 26 mm; and the maximum size of the exposure area in the Y direction is 33 mm.

[0037] A further improvement is that the grid point division in step 2 includes: dividing each of the crystal grains equally according to a first value in the X direction and dividing each of the crystal grains equally according to a second value in the Y direction.

[0038] In the exposure area, the dimensions of the grid point areas in the X direction are equal, the dimensions of the grid point areas in the Y direction are equal, and the first value and the second value ensure that the difference between the dimensions of the grid point areas in the X direction and the dimensions of the grid point areas in the Y direction is minimized.

[0039] A further improvement is that m is one of 1, 2 and 3, n is one of 1, 2 and 3; and the combinations of m×n include: 1×1, 1×2, 2×1, 2×2, 1×3, 3×1.

[0040] A further improvement is that in step three, the process layer includes a FEOL layer and a BEOL layer.

[0041] A further improvement is that before step 4, a plurality of legends are obtained in advance, each of which is a corresponding distribution map of the mark placement area.

[0042] Each group of the process layers and various combinations of the distribution structures corresponding to the die has a legend, and the mark placement area distribution diagram in the legend ensures that the high-order compensation of the overlay error of the die corresponding to the legend meets the requirements.

[0043] In step four, the corresponding legend is selected according to the corresponding process layer and the distribution structure of the die to obtain a distribution map of the mark placement area corresponding to the die.

[0044] A further improvement is that in step 4, the distance between the edge of the overlay mark in the device area and the edge of the corresponding mark placement area is greater than or equal to 2380 μm.

[0045] A further improvement is that in step 4, the high-order compensation parameters of the overlay error are fitting parameters of the product terms of the square of the X coordinate or the square of the Y coordinate in the fitting formula of the overlay error at the corresponding coordinates.

[0046] A further improvement is that in step four, the arrangement and number of the overlay marks in the device area corresponding to the grain meet the high-order compensation requirements of the overlay error, which means that after the overlay marks are set in the device area, the noise amplification factor (normalized model uncertainty, nMU) of the overlay error obtained by measuring the overlay marks in the device area is less than 1.

[0047] The present invention sets an overlay mark in the device area, that is, an overlay mark in the device area, and obtains a grid area of ​​the grains by grid division according to the distribution structure of the grains in the exposure area, groups the mask according to the process layer, and finally sets the distribution of the mark placement area according to the distribution structure of the grains and the corresponding process layer grouping, and sets the overlay mark in the device area in the selected mark placement area. By combining the overlay mark in the device area set with the distribution structure of the grains and the grouping of the process layer, the compensation value of the high-order corrected overlay error of the device area can be accurately simulated and calculated, thereby preventing the high-order compensation parameters of the overlay error inside the exposure area from being erroneously compensated, thereby improving the yield of the product, especially the large-size grain product.

[0048] The present invention can pre-form a legend of mark placement areas corresponding to grains with various distribution structures and process layers according to various distribution structures of grains and various grouping combinations of corresponding process layers. After the legend is formed, subsequent grains can directly apply the distribution of mark placement areas in the legend when obtaining the grouping of distribution structures and process layers to achieve the setting of overlay marks in the device area, which can simplify the process of setting overlay marks in the device area. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0050] Figure 1 is a nMU data diagram of DBO measurement of an overlay mark placed using an existing overlay mark placement method;

[0051] Figure 2 A vector distribution diagram of overlay deviation after overlay compensation is performed on an overlay mark placed by an existing overlay mark placement method;

[0052] Figure 3 is a flow chart of a method for placing an overlay mark according to an embodiment of the present invention;

[0053] Figure 4 is a schematic diagram of the distribution structure of grains in an exposure area of ​​an overlay mark placement method according to an embodiment of the present invention;

[0054] Figure 5A It is an example of a distribution diagram of the mark placement area of ​​grains with various distribution structures corresponding to the FEOL layer in the overlay mark placement method according to an embodiment of the present invention;

[0055] Figure 5B It is an example of a distribution diagram of the mark placement area of ​​the grains of various distribution structures corresponding to the BEOL layer in the overlay mark placement method according to an embodiment of the present invention;

[0056] Figure 6 is a schematic diagram of placing an overlay mark in a device region within a mark placement region in an overlay mark placement method according to an embodiment of the present invention;

[0057] Figure 7 This is a nMU data diagram of DBO measurement of an overlay mark placed using the overlay mark placement method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0058] like Figure 3 As shown, it is a flow chart of the method for placing an overlay mark according to an embodiment of the present invention; Figure 4 As shown, it is a schematic diagram of the distribution structure of grains in the exposure area of ​​the overlay mark placement method according to an embodiment of the present invention; Figure 5A As shown, it is an example of a distribution diagram of the mark placement area 204a of the grains 202 with various distribution structures corresponding to the FEOL layer in the overlay mark placement method according to an embodiment of the present invention; Figure 5B As shown, it is an example of a distribution diagram of the mark placement area 204a of the grains 202 with various distribution structures corresponding to the BEOL layer in the overlay mark placement method according to an embodiment of the present invention; the overlay mark placement method according to an embodiment of the present invention comprises the following steps:

[0059] Step 1: Figure 4As shown, the distribution structure of the grains 202 in the exposure area 201 is determined.

[0060] In the embodiment of the present invention, the distribution structure of the crystal grains 202 includes an X-direction distribution and a Y-direction distribution.

[0061] The X-direction distribution is obtained from the X-direction size of the exposure region 201 , the X-direction size of the grain 202 , and the X-direction size of the cutting path 203 .

[0062] The Y-direction distribution is obtained from the Y-direction size of the exposure region 201 , the Y-direction size of the grain 202 , and the Y-direction size of the cutting path 203 .

[0063] In the embodiment of the present invention, the calculation formula for the number of columns of the distribution structure of the grains 202 in the X direction is:

[0064] m=integer[(Rx-Sx) / (Cx+Sx)].

[0065] m represents the number of columns of the distribution structure of the crystal grain 202 in the X direction, integer() represents rounding down, Rx represents the X direction size of the exposure area 201, Sx represents the X direction size of the cutting road 203, and Cx represents the X direction size of the crystal grain 202. Figure 4 Also marked in.

[0066] The calculation formula for the number of rows of the distribution structure of the grains 202 in the Y direction is:

[0067] n=integer[(Ry-Sy) / (Cy+Sy)].

[0068] n represents the number of rows of the distribution structure of the grain 202 in the Y direction, Ry represents the Y direction size of the exposure area 201, Sy represents the Y direction size of the cutting road 203, and Cy represents the Y direction size of the grain 202. Figure 4 Also marked in.

[0069] Furthermore, the X-direction dimension of the crystal grain 202 is the sum of the X-direction dimensions of the main chip and the sealing ring around the main chip.

[0070] The Y-direction dimension of the die 202 is the sum of the Y-direction dimensions of the main chip and the sealing ring around the main chip.

[0071] In some embodiments, when the sealing ring is added at the factory:

[0072] The calculation formula of the X-direction dimension of the grain 202 is:

[0073] Cx=(C0x*0.9+2*22.2)μm;

[0074] The calculation formula of the Y-direction dimension of the grain 202 is:

[0075] Cy=(C0y*0.9+2*22.2)μm;

[0076] Cox represents the X-direction dimension of the main chip;

[0077] Coy represents the Y-direction dimension of the main chip.

[0078] In some embodiments, it is also possible that: when the sealing ring is added at the client:

[0079] The calculation formula of the X-direction dimension of the grain 202 is:

[0080] Cx=(C0x+2*24)*0.9μm;

[0081] The calculation formula of the Y-direction dimension of the grain 202 is:

[0082] Cy=(C0y+2*24)*0.9μm.

[0083] In some embodiments, the maximum dimension of the exposure area 201 in the X direction is 26 mm; the maximum dimension of the exposure area 201 in the Y direction is 33 mm.

[0084] In some embodiments, for Sx and Sy, the following specific settings are included:

[0085] The width of a single scribe line is 66 μm; the width of other scribe lines is k*60 μm, where k=2, 3, 4, 5, 6, etc.

[0086] Depend on Figure 4 As shown, more than one crystal grain 202 can be placed in one exposure area 201. The embodiment of the present invention is mainly to solve the technical problem caused by the large-sized crystal grains 202, that is, the area of ​​the cutting road 203 corresponding to the large-sized crystal grains 202 becomes smaller and the distribution position is not conducive to placing the overlay mark, that is, the overlay mark in the cutting road area. In this way, the number of overlay marks in the cutting road area will be small and the layout is not good, so it is impossible to reflect the real overlay, thereby causing the technical problem of the present invention.

[0087] For the large-sized die 202 , in some embodiments, m is one of 1, 2 and 3, n is one of 1, 2 and 3, and combinations of m×n include: 1×1, 1×2, 2×1, 2×2, 1×3, and 3×1.

[0088] Figure 5A and Figure 5B In the figure, the distribution structure of the die 202 corresponding to various combinations of m×n are respectively represented by 1×1die, 2×1die, 1×2die, 2×2die, 1×3die, and 3×1die.

[0089] Figure 5A The sizes of the various crystal grains 202 shown in the figure are relatively large, and the use of existing methods to place overlay marks is prone to the technical problems pointed out by the present invention. If the size of the crystal grains 202 is further reduced, the value of m or n will further increase, the number of the crystal grains 202 in the same exposure area 201 will increase, and the number of the cutting lanes 203 will also increase. If the number and distribution of the cutting lanes 203 are sufficient to meet the requirements of avoiding high-order overlay error compensation, it is possible to choose or not to use the method of the embodiment of the present invention to place the overlay mark 301 in the device area.

[0090] Step 2: divide each of the crystal grains 202 into grid points according to the distribution structure of the crystal grains 202 to obtain the grid point regions 204 of each of the crystal grains 202 .

[0091] In the embodiment of the present invention, the grid point division includes: dividing each of the crystal grains 202 equally according to a first value in the X direction and dividing each of the crystal grains 202 equally according to a second value in the Y direction.

[0092] In the exposure area 201, the X-direction dimensions of each of the grid point areas 204 are equal, the Y-direction dimensions of each of the grid point areas 204 are equal, and the first value and the second value ensure that the difference between the X-direction dimensions and the Y-direction dimensions of each of the grid point areas 204 is minimized.

[0093] Figure 5A and Figure 5B In the example, the exposure area 201 has a maximum size of 26 mm in the X direction and a maximum size of 33 mm in the Y direction, and the distribution structures of the various grains 202 can be divided into the following grid points:

[0094] For a 1x1 die, divide it into 11 equal parts in the X direction and 13 equal parts in the Y direction; Figure 5A In the figure, the corresponding grains are individually indicated by reference numeral 202a.

[0095] For a 2x1 die, divide it into 5 equal parts in the X direction and 13 equal parts in the Y direction; Figure 5A In the figure, the corresponding grain is individually indicated by a mark 202b, and the corresponding cutting road is individually indicated by a mark 203b.

[0096] For a 1x2 die, divide it into 11 equal parts in the X direction and 5 equal parts in the Y direction;

[0097] For a 2x2 die, divide it into 7 equal parts in the X direction and 9 equal parts in the Y direction;

[0098] For a 1x3 die, divide it into 11 equal parts in the X direction and 5 equal parts in the Y direction;

[0099] For a 3x1 die, divide it into 5 equal parts in the X direction and 13 equal parts in the Y direction.

[0100] In other embodiments, when the size of the exposure area 201 is not 26 mm×33 mm, the grid division can be performed as needed without being limited to the above division results.

[0101] Step 3: Group the masks according to the process layers.

[0102] In wafer manufacturing, the crystal grain 202 needs to undergo a multi-step process. In the multi-step process, some process steps need to be defined by a mask. Therefore, the crystal grain 202 needs to use multiple layers of masks in the actual process. Usually, one layer corresponds to one layer of mask, and multiple process layers can share the same mask.

[0103] The process of the crystal grain 203 is generally divided into the front-end process (FEOL), the middle process (MOL) and the back-end process (BEOL), wherein the FEOL process is mainly used to form a semiconductor device structure on a wafer, that is, to complete the manufacture of a semiconductor device such as a gate structure, a source region and a drain region of a MOSFET. The MOL is mainly used to form contact holes to achieve connection with the gate structure, the source region and the drain region of the semiconductor device. The BEOL is used to form a metal interconnection layer.

[0104] The FEOL process may include multiple process layers, and the BEOL process may also include multiple process layers. In this application, the process layers in the FEOL are collectively referred to as FEOL layers, and the process layers in the BEOL are collectively referred to as BEOL layers. In the embodiment of the present invention, the process layers related to the photomask used in the manufacturing process of the die 202 are grouped according to the FEOL layer and the BEOL layer, that is, the process layers include the FEOL layer and the BEOL layer.

[0105] so, Figure 5AThe distribution structure of the grains 202 and the corresponding grid point division corresponding to each process layer in the FEOL layer that needs to use a mask; Figure 5B The distribution structure of the grains 202 and the corresponding grid point divisions corresponding to each process layer in the FEOL layer that requires a photomask.

[0106] Step 4: Select a plurality of the grid areas 204 as mark placement areas 204a in the grains 202 of the mask corresponding to each group of the process layers and place the overlay marks 301 in the device area in the mark placement areas 204a. The arrangement and number of the overlay marks 301 in the device area corresponding to the grains 202 meet the high-order compensation requirements of the overlay errors.

[0107] In the embodiment of the present invention, before step 4, it also includes pre-obtaining a plurality of legends, each of which is a distribution map of the corresponding mark placement area 204a.

[0108] Each group of the process layers and various combinations of the distribution structures corresponding to the die 202 has a legend, and the distribution diagram of the mark placement area 204a in the legend ensures that the high-order compensation of the overlay error of the die 202 corresponding to the legend meets the requirements.

[0109] In step 4, the corresponding legend is selected according to the corresponding process layer and the distribution structure of the die 202 to obtain a distribution diagram of the mark placement area 204a corresponding to the die 202.

[0110] In some embodiments, the distribution structure of the large-sized die 202 includes 1×1die, 2×1die, 1×2die, 2×2die, 1×3die, and 3×1die as an example:

[0111] For FEOL layers, you can set Figure 5A The 6 figures shown in Figure 5A In the figure, the mark placement area is represented by mark 204a alone.

[0112] For BEOL layers, you can set Figure 5B The 6 figures shown in .

[0113] For specific distribution of the mark placement area 204a in each of the above-mentioned legends, please refer to Figure 5A and Figure 5B As shown, I will not describe them one by one here. Figure 5A and Figure 5B The various examples of FIG. 1 are verified by experiments and meet the high-order compensation requirements of the overlay error. In other embodiments, the Figure 5A and Figure 5B The legends shown are subject to change.

[0114] When the process layer and distribution structure corresponding to the die 202 are obtained, the corresponding legend can be selected, and then the mark placement area 204a is set according to the provisions of the legend. For example, when the process layer of the die 202 is the FEO layer and the distribution structure is 1×3die, the mark placement area 204a can be used. Figure 5A The legend corresponding to the 1×3 die sets the mark placement area 204a.

[0115] like Figure 6 As shown, it is a schematic diagram of placing the overlay mark 301 in the device area in the overlay mark placement method of the embodiment of the present invention; the distance between the edge of the overlay mark 301 in the device area and the edge of the corresponding mark placement area 204a is greater than or equal to 2380μm, that is, the overlay mark 301 in the device area should be set Figure 6 In the region 205, the distance between each side of the region 205 and the corresponding side of the mark placement region 204a is 2380 μm.

[0116] In an embodiment of the present invention, the high-order compensation parameter of the overlay error is a fitting parameter of a product term of the square of the X coordinate or the square of the Y coordinate in the fitting formula of the overlay error at the corresponding coordinate. For example, a light field level model is used in some fitting formulas of the overlay error, and the corresponding high-order compensation generates fitting parameters K12, K13 and K14 in the light field level model, where:

[0117] K12 is the overlay error in the y direction, i.e., the x value of OVLy 2 y 0 The fitted parameters of the product term;

[0118] K13 is the overlay error in the x direction, i.e. the x value of OVLx 3 y 0 The fitted parameters of the product term;

[0119] K14 is the overlay error in the y direction, i.e. the x value of OVLy 0 y 3 Fitted parameters of the product term.

[0120] In an embodiment of the present invention, the arrangement and number of the overlay marks 301 in the device area corresponding to the die 202 meet the high-order compensation requirements of the overlay error, which means that after the overlay marks 301 are set in the device area, the noise amplification factor of the overlay error obtained by measuring the overlay marks 301 in the device area, i.e., nMU, is less than 1.

[0121] like Figure 7As shown, it is a nMU data diagram of DBO measurement of the overlay mark placed by the overlay mark placement method according to the embodiment of the present invention; Figure 7 The corresponding exposure area is marked with a mark 201c, and the grain is marked with a mark 202c. It can be seen that the distribution structure of the grain 202c is 1×3die. Figure 5A The legend corresponding to the 1×3 die in the device area sets multiple overlay marks 301. Figure 7 In the figure, the overlay mark also includes a plurality of overlay marks 302 arranged in the cutting path area in the cutting path. The entire overlay data can be obtained by measuring the overlay marks 301 in all the device areas and the overlay marks 302 in the cutting path area together, and forming corresponding nMU data. The nMU data is two-dimensional data, and the nMU data corresponding to each coordinate is nMU (x, y). The smaller the nMU data, the more accurate the measurement result of the overlay mark. Usually, the corresponding specification range (spec) is less than 1. It can be seen that the maximum value of nMU in the x direction, that is, nMU max (x), is 0.692, and the maximum value of nMU in the y direction, that is, nMU max (y), is 0.967, both of which meet the requirement of being less than 1.

[0122] The embodiment of the present invention sets an overlay mark in the device area, that is, an overlay mark in the device area, and performs grid division according to the distribution structure of the grains 202 in the exposure area 201 to obtain the grid area 204 of the grains 202, groups the masks according to the process layers, and finally sets the distribution of the mark placement area 204a according to the distribution structure of the grains 202 and the corresponding process layer grouping, and sets the overlay mark 301 in the device area in the selected mark placement area 204a. By combining the distribution structure of the grains 202 and the grouping setting of the process layer, the overlay mark 301 in the device area can accurately simulate and calculate the compensation value of the high-order corrected overlay error of the device area, thereby preventing the high-order compensation parameters of the overlay error inside the exposure area 201 from being erroneously compensated, thereby improving the yield of the product, especially the product with large-size grains 202.

[0123] The embodiment of the present invention can pre-form a legend of the mark placement area 204a corresponding to the grain 202 with each distribution structure and process layer according to various distribution structures of the grain 202 and various grouping combinations of corresponding process layers. After the legend is formed, the subsequent grain 202 can directly apply the distribution of the mark placement area 204a in the legend when obtaining the grouping of the distribution structure and process layer to achieve the setting of the overlay mark 301 in the device area, which can simplify the process of setting the overlay mark 301 in the device area.

[0124] The lack of OVL measurement marks or insufficient mark arrangement and quantity inside the shot of large die products will cause the OVL high-order correction parameter calculation to miscompensate for the mark-free area, resulting in deviations in the actual wafer layer-to-layer overlay in the mark-free area, causing a large range of low-quality products. The in-cell OVL mark arrangement rule balances the precious intra-cell space with the OVL high-order calculation requirements, allowing both to be taken into account during layout design to avoid low-quality products and waste of layout area. The embodiment of the present invention standardizes the placement method and quantity rules of in-cell OVL marks in the device area to standardize the in-cell OVL mark arrangement of large-die products, avoiding subsequent high-order OVL miscompensation cases due to mark layout.

[0125] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for placing an overlay mark, characterized in that: The steps include: Step 1, determining the distribution structure of grains in the exposure area; Step 2: performing grid point division on each of the crystal grains according to the distribution structure of the crystal grains to obtain a grid point region of each of the crystal grains; Step 3: grouping the masks according to the process layers; Step 4: select a plurality of the grid point areas as mark placement areas in the grains of the mask corresponding to each group of the process layers and place overlay marks in the device area in the mark placement areas, and the arrangement and number of overlay marks in the device area corresponding to the grains meet the high-order compensation requirements of the overlay error.

2. The method for placing an overlay mark according to claim 1, wherein: In step 1, the distribution structure of the grains includes distribution in the X direction and distribution in the Y direction; The X-direction distribution is obtained by the X-direction size of the exposure area, the X-direction size of the grain and the X-direction size of the cutting road; The Y-direction distribution is obtained by the Y-direction size of the exposure area, the Y-direction size of the grain, and the Y-direction size of the cutting road.

3. The method for placing an overlay mark according to claim 2, wherein: The calculation formula for the number of columns of the distribution structure of the grains in the X direction is: m=integer[(Rx-Sx) / (Cx+Sx)]; m represents the number of columns of the distribution structure of the grains in the X direction, integer() represents rounding down, Rx represents the size of the exposure area in the X direction, Sx represents the size of the cutting path in the X direction, and Cx represents the size of the grains in the X direction; The calculation formula for the number of rows of the grain distribution structure in the Y direction is: n=integer[(Ry-Sy) / (Cy+Sy)]; n represents the number of rows of the distribution structure of the grains in the Y direction, Ry represents the size of the exposure area in the Y direction, Sy represents the size of the cutting road in the Y direction, and Cy represents the size of the grains in the Y direction.

4. The method for placing an overlay mark according to claim 3, wherein: The X-direction size of the crystal grain is the sum of the X-direction size of the main chip and the sealing ring around the main chip; The Y-direction dimension of the crystal grain is the sum of the Y-direction dimensions of the main chip and the sealing ring around the main chip.

5. The method for placing an overlay mark according to claim 4, wherein: When the sealing ring is added at the factory: The calculation formula of the X-direction size of the grain is: Cx=(C0x*0.9+2*22.2)μm; The calculation formula of the Y-direction size of the grain is: Cy=(C0y*0.9+2*22.2)μm; Cox represents the X-direction dimension of the main chip; Coy represents the Y-direction size of the main chip; Or, when the sealing ring is added on the client side: The calculation formula of the X-direction size of the grain is: Cx=(C0x+2*24)*0.9μm; The calculation formula of the Y-direction size of the grain is: Cy=(C0y+2*24)*0.9μm.

6. The method for placing an overlay mark according to claim 3, wherein: The maximum dimension of the exposure area in the X direction is 26 mm; the maximum dimension of the exposure area in the Y direction is 33 mm.

7. The method for placing an overlay mark according to claim 3, wherein: The grid point division in step 2 includes: dividing each of the crystal grains equally by a first value in the X direction and dividing each of the crystal grains equally by a second value in the Y direction; In the exposure area, the dimensions of the grid point areas in the X direction are equal, the dimensions of the grid point areas in the Y direction are equal, and the first value and the second value ensure that the difference between the dimensions of the grid point areas in the X direction and the dimensions of the grid point areas in the Y direction is minimized.

8. The method for placing an overlay mark according to claim 6, wherein: m is one of 1, 2 and 3, n is one of 1, 2 and 3; And, the combinations of m×n include: 1×1, 1×2, 2×1, 2×2, 1×3, 3×1.

9. The overlay mark placement method according to claim 1, characterized in that: In step three, the process layer includes a FEOL layer and a BEOL layer.

10. The overlay mark placement method according to claim 9, characterized in that: Before step 4, it also includes obtaining a plurality of legends in advance, each of which is a distribution map of the corresponding mark placement area; Each group of the process layers and various combinations of the distribution structures corresponding to the die has a legend, and the mark placement area distribution diagram in the legend ensures that the high-order compensation of the overlay error of the die corresponding to the legend meets the requirements; In step four, the corresponding legend is selected according to the corresponding process layer and the distribution structure of the die to obtain a distribution map of the mark placement area corresponding to the die.

11. The method for placing an overlay mark according to claim 1, wherein: In step 4, the distance between the edge of the overlay mark in the device area and the edge of the corresponding mark placement area is greater than or equal to 2380 μm.

12. The overlay mark placement method according to claim 1, characterized in that: In step 4, the high-order compensation parameters of the overlay error are fitting parameters of the product terms of the square of the X coordinate or the square of the Y coordinate in the fitting formula of the overlay error at the corresponding coordinates.

13. The overlay mark placement method according to claim 12, characterized in that: In step four, the arrangement and number of the overlay marks in the device area corresponding to the grain meet the high-order compensation requirements of the overlay error, which means that after the overlay marks are set in the device area, the noise amplification factor of the overlay error measured according to the overlay marks in the device area is less than 1.

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