Over-temperature protection circuit with simple structure

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to an over-temperature protection circuit with a simple structure, which comprises a nmos tube MNO, a nmos tube MN1, a nmos tube MN2, a nmos tube MN4, a nmos tube MN5, a nmos tube MN6, a nmos tube MN7, a nmos tube MN8, a pmos tube MP1, a pmos tube MP2, a pmos tube MP3, a pmos tube MP4, a pmos tube MP5, a pmos tube MP6, a pmos tube MP7, a hysteresis inverter, a triode Q, an adjusting resistor R and a capacitor C, compared with the prior art, the circuit is simple in structure, easy to implement and low in overall power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more particularly to an over-temperature protection circuit with a simple structure. Background Art

[0002] With the continuous development of integrated circuits, the integration of integrated circuits continues to increase, resulting in a continuous increase in power consumption of integrated circuits. The continuous increase in power consumption will cause the temperature to continue to rise, which will affect the reliability of the integrated circuit. Therefore, in some high-power power modules, over-temperature protection is very important.

[0003] However, the over-temperature protection circuit is usually based on the architecture of the operational amplifier, which has a complex structure, relatively high power consumption, and is difficult to implement. Summary of the invention

[0004] In view of the deficiencies in the prior art, an object of the present invention is to provide an over-temperature protection circuit with a simple structure and low power consumption.

[0005] To achieve the above object, the present invention provides the following technical solutions: An over-temperature protection circuit with a simple structure comprises a nmos tube MNO, a nmos tube MN1, a nmos tube MN2, a nmos tube MN4, a nmos tube MN8, a pmos tube MP1, a pmos tube MP2, a pmos tube MP3, a pmos tube MP4, a pmos tube MP5, a pmos tube MP7, a hysteresis inverter, a triode Q, an adjusting resistor R and a capacitor C; The hysteresis inverter includes a pmos tube MP6, a nmos tube MN5, a nmos tube MN6 and a nmos tube MN7; The drain of nmos tube MN1 is connected to the input current IPTAT, the source of nmos tube MN1 is connected to the ground terminal and the power supply, the gate of nmos tube MN2, one end of the regulating resistor R, the emitter of transistor Q, the drain of nmos tube MN4, the negative electrode of capacitor C, the drain of nmos tube MN6 and the drain of nmos tube MN8; The drain of the nmos tube MN2 is connected to the other end of the regulating resistor R, the emitter of the transistor R, the drain of the nmos tube MN4, the negative electrode of the capacitor C, the drain of the nmos tube MN6 and the drain of the nmos tube MN8; One end of the regulating resistor R is connected to the drain of the nmos tube MN0, the base of the transistor, the gate of the nmos tube MN4, the gate of the nmos tube MN5, the gate of the nmos tube MN6, the gate of the nmos tube MN7 and the gate of the nmos tube MN8; the gate of the nmos tube MN0 outputs a voltage OVTP; The power supply end is connected to the drain of pmos tube MP1, the source of pmos tube MP2, the source of pmos tube MP3, the source of pmos tube MP4, the source of pmos tube MP5, the source of pmos tube MP6, and the source of pmos tube MP7. The gate of the pmos tube MP1 is connected to the gate of the pmos tube MP2, the source of the pmos tube MP3, the source of the pmos tube MP4 and the source of the pmos tube MP5; The drain of pmos tube MP6 is connected to the gate of nmos tube N7, and the gate of pmos tube MP7 is connected to the gate of nmos tube MN8; The drain of the pmos tube MP7 and the source of the nmos tube MN8 are grounded; The gate of the nmos tube MN4 is connected to the positive electrode of the capacitor C, and the negative electrode of the capacitor C is connected to the drain of the nmos tube MN5.

[0006] The present invention is further configured as follows: the size of the hysteresis inverter can adjust the size of the hysteresis temperature, and the formula is: .

[0007] The present invention is further configured as follows: the collector of the transistor Q is connected to the gate of the nmos tube MNO, and the emitter of the transistor Q is connected to the drain of the nmos tube MN4.

[0008] The present invention is further configured as follows: a voltage Vr is formed between the nmos tube MNO and the transistor Q, a voltage Vq is formed between the transistor Q and the nmos tube MN4, a voltage Vc is formed between the nmos tube MN4 and the capacitor C, and a voltage Vd is formed between the nmos tube MN5 and the nmos tube MN7.

[0009] Compared with the shortcomings of the prior art, the beneficial effects of the present invention are: By setting up the over-temperature protection circuit of transistor Q and hysteresis comparator, the circuit structure is simple and easy to implement, and the overall power consumption is relatively low. When the temperature rises, the positive temperature coefficient current IPTAT is used to mirror the current to the branch of the regulating resistor R. As the temperature rises to about 500mV, the transistor Q is turned on to pull the voltage of Vq to a low level, and the voltage of Vc will be pulled from low to high. After passing through the hysteresis comparator, the voltage of Vd is pulled from high to bottom, and finally the OVTP signal is pulled from low to high. The current at the R end is provided by two branches. When the temperature gradually decreases from high temperature, due to the effect of the nmos tube MN0, a lower temperature is required to achieve the reduction of OVTP. Adjusting the size of the hysteresis inverter can achieve the adjustment of the hysteresis temperature. Increasing the width-to-length ratio of MN6 and reducing the width-to-length ratio of MN7 can increase the flip threshold of the hysteresis inverter. Adjusting the size of the resistor R can adjust the trigger temperature point of the high temperature protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A circuit diagram of an embodiment of the present invention; Figure 2 This is a graph showing the relationship between the OVTP signal and temperature. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0012] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0013] like Figure 1 to Figure 2 As shown, An over-temperature protection circuit with a simple structure comprises a nmos tube MNO, a nmos tube MN1, a nmos tube MN2, a nmos tube MN4, a nmos tube MN8, a pmos tube MP1, a pmos tube MP2, a pmos tube MP3, a pmos tube MP4, a pmos tube MP5, a pmos tube MP7, a hysteresis inverter, a triode Q, an adjusting resistor R and a capacitor C; The hysteresis inverter includes a pmos tube MP6, a nmos tube MN5, a nmos tube MN6 and a nmos tube MN7; The size of the hysteresis inverter can adjust the hysteresis temperature. The formula is: .

[0014] The hysteresis inverter uses threshold voltage and hysteresis voltage to achieve a stable output state and flexible control function; it mainly realizes the function of a hysteresis inverter. The hysteresis inverter is an inverter with hysteresis characteristics. Its output state depends not only on the comparison result between the input voltage and a fixed threshold voltage, but also on its previous output state. This hysteresis characteristic makes the circuit have a certain anti-interference ability for small changes in the input voltage.

[0015] The drain of nmos tube MN1 is connected to the input current IPTAT, the source of nmos tube MN1 is connected to the ground terminal and the power supply, the gate of nmos tube MN2, one end of the regulating resistor R, the emitter of transistor Q, the drain of nmos tube MN4, the negative electrode of capacitor C, the drain of nmos tube MN6 and the drain of nmos tube MN8; The drain of the nmos tube MN2 is connected to the other end of the regulating resistor R, the emitter of the transistor R, the drain of the nmos tube MN4, the negative electrode of the capacitor C, the drain of the nmos tube MN6 and the drain of the nmos tube MN8; One end of the regulating resistor R is connected to the drain of the nmos tube MN0, the base of the transistor, the gate of the nmos tube MN4, the gate of the nmos tube MN5, the gate of the nmos tube MN6, the gate of the nmos tube MN7 and the gate of the nmos tube MN8; the gate of the nmos tube MN0 outputs a voltage OVTP; The power supply end is connected to the drain of pmos tube MP1, the source of pmos tube MP2, the source of pmos tube MP3, the source of pmos tube MP4, the source of pmos tube MP5, the source of pmos tube MP6, and the source of pmos tube MP7. The gate of the pmos tube MP1 is connected to the gate of the pmos tube MP2, the source of the pmos tube MP3, the source of the pmos tube MP4 and the source of the pmos tube MP5; The drain of pmos tube MP6 is connected to the gate of nmos tube N7, and the gate of pmos tube MP7 is connected to the gate of nmos tube MN8; The drain of the pmos tube MP7 and the source of the nmos tube MN8 are grounded; The gate of nmos tube MN4 is connected to the positive electrode of capacitor C, and the negative electrode of capacitor C is connected to the drain of nmos tube MN5; The collector of transistor Q is connected to the gate of nmos tube MNO, and the emitter of transistor Q is connected to the drain of nmos tube MN4.

[0016] A voltage Vr is formed between the nmos tube MNO and the transistor Q, a voltage Vq is formed between the transistor Q and the nmos tube MN4, a voltage Vc is formed between the nmos tube MN4 and the capacitor C, and a voltage Vd is formed between the nmos tube MN5 and the nmos tube MN7.

[0017] Working principle: When the temperature rises, the positive temperature coefficient current IPTAT is used to mirror the current to the branch of the regulating resistor R. As the temperature rises, the Vr voltage rises to about 500mV. The VBE on the transistor Q is turned on to pull the voltage of Vq to a low level, and the voltage of Vc will be pulled from low to high. After passing through the hysteresis inverter, the voltage of Vd is pulled from high to bottom, and finally the OVTP signal is pulled from low to high. The current at the R end is provided by two branches. When the temperature gradually decreases from high temperature, due to the effect of MN0, a lower temperature is required to reduce OVTP. The size of the hysteresis inverter can adjust the size of the hysteresis temperature. Increasing the width-to-length ratio of MN6 and reducing the width-to-length ratio of MN7 can increase the flip threshold of the hysteresis inverter. The trigger temperature point of the high temperature protection can be adjusted by adjusting the size of the resistor R.

[0018] The relevant formula is as follows:

[0019] in is the voltage difference between the base and emitter of transistor Q, and K are constants, T is the temperature; The relationship between the OVTP signal and temperature is as follows: Figure 2 As shown, T2 is the trigger temperature of the over-temperature protection circuit output port OVTP jumping from low to high during the temperature rise process, and T1 is the trigger temperature of the OVTP signal jumping from high to low during the temperature recovery process. The NMOS tube MN0 and the hysteresis comparator behind it in the circuit are used to generate a hysteresis temperature to prevent the over-temperature protection circuit from flipping back and forth at the trigger temperature point.

[0020] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. An over-temperature protection circuit with a simple structure, characterized in that: Including nmos tube MNO, nmos tube MN1, nmos tube MN2, nmos tube MN4, nmos tube MN8, pmos tube MP1, pmos tube MP2, pmos tube MP3, pmos tube MP4, pmos tube MP5, pmos tube MP7, hysteresis inverter, transistor Q, adjustment resistor R and capacitor C; The hysteresis inverter includes a pmos tube MP6, a nmos tube MN5, a nmos tube MN6 and a nmos tube MN7; The drain of nmos tube MN1 is connected to the input current IPTAT, the source of nmos tube MN1 is connected to the ground terminal and the power supply, the gate of nmos tube MN2, one end of the regulating resistor R, the emitter of transistor Q, the drain of nmos tube MN4, the negative electrode of capacitor C, the drain of nmos tube MN6 and the drain of nmos tube MN8; The drain of the nmos tube MN2 is connected to the other end of the regulating resistor R, the emitter of the transistor R, the drain of the nmos tube MN4, the negative electrode of the capacitor C, the drain of the nmos tube MN6 and the drain of the nmos tube MN8; One end of the regulating resistor R is connected to the drain of the nmos tube MN0, the base of the transistor, the gate of the nmos tube MN4, the gate of the nmos tube MN5, the gate of the nmos tube MN6, the gate of the nmos tube MN7 and the gate of the nmos tube MN8; the gate of the nmos tube MN0 outputs a voltage OVTP; The power supply end is connected to the drain of pmos tube MP1, the source of pmos tube MP2, the source of pmos tube MP3, the source of pmos tube MP4, the source of pmos tube MP5, the source of pmos tube MP6, and the source of pmos tube MP7. The gate of the pmos tube MP1 is connected to the gate of the pmos tube MP2, the source of the pmos tube MP3, the source of the pmos tube MP4 and the source of the pmos tube MP5; The drain of pmos tube MP6 is connected to the gate of nmos tube N7, and the gate of pmos tube MP7 is connected to the gate of nmos tube MN8; The drain of the pmos tube MP7 and the source of the nmos tube MN8 are grounded; The gate of the nmos tube MN4 is connected to the positive electrode of the capacitor C, and the negative electrode of the capacitor C is connected to the drain of the nmos tube MN5.

2. An over-temperature protection circuit with a simple structure according to claim 1, characterized in that: The size of the hysteresis inverter can adjust the hysteresis temperature, and the formula is: .

3. The over-temperature protection circuit with a simple structure according to claim 1 is characterized in that: The collector of the transistor Q is connected to the gate of the nmos tube MNO, and the emitter of the transistor Q is connected to the drain of the nmos tube MN4.

4. The over-temperature protection circuit with a simple structure according to claim 1 is characterized in that: A voltage Vr is formed between the nmos tube MNO and the transistor Q, a voltage Vq is formed between the transistor Q and the nmos tube MN4, a voltage Vc is formed between the nmos tube MN4 and the capacitor C, and a voltage Vd is formed between the nmos tube MN5 and the nmos tube MN7.

Images