Data transmission method of asynchronous FIFO and asynchronous FIFO

Abstract

The invention provides an asynchronous FIFO data transmission method and an asynchronous FIFO.The asynchronous FIFO performs data transmission between a write-in user side and a read-in user side, the method comprises the steps that when the asynchronous FIFO performs data transmission, a configuration bit of the asynchronous FIFO is obtained, if the configuration bit is equal to a first configuration value, the read-in user side detects whether data read by the read-in FIFO has errors or not, if yes, the read-in FIFO performs data transmission, and if not, the read-in FIFO performs data transmission; if the error data exists, stopping reading the data, and feeding back an error mark signal to the writing user side by the reading user side; the error mark signal at least comprises a pause signal and a read address corresponding to the error data; and the write-in user side pauses the write data of the write-side FIFO according to the pause signal, and transmits corresponding correct data according to the read address corresponding to the error data so as to replace the error data. According to the method and the device, the data transmission efficiency and accuracy can be improved by detecting the error data of the read-side FIFO and retransmitting the corresponding error data.

Description

Technical Field

[0001] The present application belongs to the technical field of data transmission, and in particular, relates to an asynchronous FIFO data transmission method and an asynchronous FIFO. Background Art

[0002] FIFO (First In First Out) is a first-in-first-out data buffer. Data is written from one end and read from the other end. The read order is exactly the same as the write order. The read and write of FIFO is designed based on the full and empty signals to write / read FIFO. When FIFO is full, it cannot be written into it, and when FIFO is empty, data cannot be read.

[0003] For asynchronous FIFO, data is written into the FIFO by a control signal in one clock domain, and read out of the FIFO by a control signal in another clock domain. In other words, the changes in the read and write pointers are generated by different clocks. Therefore, the judgment of whether the FIFO is empty or full is across clock domains. However, due to the asynchrony of the write and read clock domains, or the mismatch between the read data and the FIFO empty signal, or the control signal error, the data read on the read side may be inconsistent or erroneous. In traditional asynchronous FIFO designs, once an error is detected, all data is usually retransmitted from the write side. Although this method can detect and correct errors, it has low flexibility and poor multiplexing, because once an error occurs, the entire FIFO needs to be retransmitted from the beginning, resulting in resource waste and low efficiency.

[0004] Therefore, an efficient retransmission solution is urgently needed to solve the problem of asynchronous FIFO data transmission errors. Summary of the invention

[0005] The present application discloses an asynchronous FIFO data transmission method, which can improve the efficiency and accuracy of data transmission by detecting erroneous data in a read-side FIFO and retransmitting the corresponding erroneous data.

[0006] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0007] To achieve one or part or all of the above purposes or other purposes, in a first aspect, the present application provides a data transmission method of an asynchronous FIFO, wherein the asynchronous FIFO includes a write-side FIFO for connecting to a write user side to write data, a storage body for accessing data, and a read-side FIFO for connecting to a read user side to read data, so that the asynchronous FIFO performs data transmission between the write user side and the read user side, and the method includes: when the asynchronous FIFO performs data transmission, obtaining the configuration bit of the asynchronous FIFO, if the configuration bit is equal to a first configuration value, the read user side detects whether there is an error in the data read by the read side FIFO, if there is error data, stops reading the data, and the read user side feeds back an error flag signal to the write user side; wherein the error flag signal includes at least a pause signal and a read address corresponding to the error data; the write user side pauses the writing of data by the write side FIFO according to the pause signal, and transmits corresponding correct data according to the read address corresponding to the error data to replace the error data.

[0008] In one implementation, the writing user side determines the write address corresponding to the error data in the write side FIFO according to the read address corresponding to the error data in response to the first preset information; The write user side instructs the write pointer of the write side FIFO to point to the write address corresponding to the erroneous data again, and the write side FIFO recovers the write data starting from the write address corresponding to the erroneous data, rewrites the erroneous data and the data after the erroneous data, and replaces the erroneous data and the data after the erroneous data with correct data.

[0009] In one implementation, after recovering the write data, the writing user side feeds back a solution flag signal to the reading user side; The reading user side responds to the resolution flag signal and instructs the reading side FIFO to restart reading data from the reading address corresponding to the erroneous data.

[0010] In one implementation, the writing user side responds to the second preset information, determines the correct data corresponding to the erroneous data according to the read address corresponding to the erroneous data, writes the correct data into the storage body, and only replaces the erroneous data with the correct data.

[0011] In one implementation, after replacing the erroneous data with the correct data, the writing user side performs a handshake with the reading user side to notify the reading user side that the data has been updated; The writing user side instructs the writing side FIFO to resume writing data from the address when it was suspended; the reading user side responds to the data being updated and resumes reading data after re-reading the correct data.

[0012] In one implementation, when the asynchronous FIFO performs data transmission, the asynchronous FIFO obtains a write flag of the write-side FIFO and a read flag of the read-side FIFO, wherein the write flag includes a write-full flag, a nearly full flag, a half-full flag, and an empty flag, and the read flag includes a full flag, a half-empty flag, a nearly empty flag, and a read-empty flag; If the configuration bit is equal to the second configuration value, the asynchronous FIFO performs data transmission between different clock domains according to the write flag and the read flag.

[0013] In one implementation, if the configuration bit is equal to the first configuration value, there is error data and the write flag is a non-write full empty flag, the write user side assigns the read address corresponding to the error data to the write address of the write side FIFO to stop writing data to the write side FIFO according to the pause signal; If the configuration bit is equal to the first configuration value, there is error data and the read flag is not a read empty flag, the reading user side stops reading data from the read side FIFO according to the read address corresponding to the error data.

[0014] In a second aspect, the present application also provides an asynchronous FIFO, which includes a write-side FIFO for connecting to a write user side to write data, a storage body for accessing data, and a read-side FIFO for connecting to a read user side to read data. The asynchronous FIFO is used to transmit data between the write user side and the read user side to implement a data transmission method of an asynchronous FIFO as claimed in any one of claims 1 to 7. The write-side FIFO also includes a data correction module, which is used to transmit corresponding correct data to replace the erroneous data when erroneous data exists.

[0015] In one implementation, the write side FIFO includes a full judgment module, which is used to judge the write flag of the write side FIFO; the read side FIFO includes an empty judgment module, which is used to judge the read flag of the read side FIFO, wherein the write flag includes full, nearly full, half full, and empty flags, and the read flag includes full flag, half empty, nearly empty, and read empty.

[0016] In a third aspect, the present application provides a computer-readable storage medium, in which a program code is stored, and the program code is called by a processor to execute an asynchronous FIFO data transmission method according to any one of the first aspects.

[0017] In a fourth aspect, the present application also provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute an asynchronous FIFO data transmission method as described in any one of the first aspects.

[0018] The above-mentioned asynchronous FIFO data transmission method and asynchronous FIFO obtain the configuration bit of the asynchronous FIFO when the asynchronous FIFO performs data transmission. If the configuration bit is equal to the first configuration value, the reading user side detects whether there is an error in the data read by the read side FIFO. If there is erroneous data, the reading of the data is stopped, and the reading user side feeds back an error flag signal to the writing user side. The writing user side pauses the writing of the write side FIFO according to the pause signal, and transmits the corresponding correct data to replace the erroneous data according to the read address corresponding to the erroneous data, thereby realizing the detection of erroneous data in the read side FIFO and retransmitting the corresponding erroneous data, thereby improving the efficiency and accuracy of data transmission.

[0019] In order to make the above and other purposes, features and advantages of the present application more obvious and understandable, preferred embodiments are specifically listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 This is a first flow chart of the asynchronous FIFO data transmission method according to an embodiment of the present application.

[0022] Figure 2 A schematic diagram of data transmission by an asynchronous FIFO according to an embodiment of the present application.

[0023] Figure 3 This is a second flow chart of the asynchronous FIFO data transmission method according to an embodiment of the present application.

[0024] Figure 4 This is a third flow chart of the asynchronous FIFO data transmission method according to an embodiment of the present application.

[0025] Figure 5 This is a fourth flow chart of the asynchronous FIFO data transmission method according to an embodiment of the present application.

[0026] Figure 6 This is a structural block diagram of an asynchronous FIFO according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] The aforementioned and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0028] In traditional asynchronous FIFO designs, once an error is detected, all data is usually retransmitted from the write side. Although this method can detect and correct errors, it has low flexibility and poor multiplexing because once an error occurs, the entire FIFO needs to be retransmitted from the beginning, resulting in resource waste and low efficiency.

[0029] In order to improve the efficiency and accuracy of data transmission, an embodiment of the present application provides a data transmission method of an asynchronous FIFO, wherein the asynchronous FIFO performs data transmission between a writing user side and a reading user side, and the asynchronous FIFO includes a writing side FIFO for connecting to the writing user side to write data, a storage body for accessing data, and a reading side FIFO for connecting to the reading user side to read data. The data transmission method implemented in this embodiment includes: when the asynchronous FIFO performs data transmission, obtaining the configuration bit of the asynchronous FIFO, if the configuration bit is equal to the first configuration value, the reading user side detects whether there is an error in the data read by the reading side FIFO, if there is erroneous data, stopping reading the data, and the reading user side feeds back an error flag signal to the writing user side; the writing user side transmits corresponding correct data according to the error flag signal to replace the erroneous data. This method can insert and replace data in the port of the storage body RAM (Random Access Memory) by modifying the write address waddr of the write-side FIFO. It does not need to rewrite all data, but only needs to replace the write data wdata or the subsequent data in the current storage body. It is applicable to any data scenario. This method can also replace all data after the erroneous data after the erroneous data is replaced. It is applicable to the scenario where the subsequent data depends on the previous data. It can meet the different scenario requirements of various users, has high performance, and can improve the efficiency and reliability of data transmission.

[0030] The present application is described in detail below with reference to the accompanying drawings.

[0031] refer to Figure 1 and Figure 2 , an embodiment of the present application provides an asynchronous FIFO data transmission method, comprising the following steps: Step S1: When the asynchronous FIFO is transmitting data, the configuration bit of the asynchronous FIFO is obtained. If the configuration bit is equal to the first configuration value, the reading user side detects whether there is an error in the data read by the read side FIFO. If there is erroneous data, the reading of data is stopped, and the reading user side feeds back an error flag signal to the writing user side.

[0032] Among them, the configuration bit is used to control the working mode of the asynchronous FIFO, and the specific configuration value can be set according to user needs. It should be noted that this application is mainly aimed at the problem that the data read by the read side FIFO is erroneous due to data transmission errors on the write side FIFO. The erroneous data includes but is not limited to data confusion, data missing, etc. Therefore, when erroneous data occurs, the reading user side feeds back an error flag signal to the writing user side, so that the writing user side controls the writing of the write side FIFO to correct the data.

[0033] Specifically, when the configuration bit is equal to the first configuration value (such as 1), it indicates that the asynchronous FIFO enters the data insertion and replacement mode, which can also be called the data correction mode. In this mode, the reading user side detects whether there is an error in the data read by the reading side FIFO, for example, by detecting the erroneous data through CRC check. The detection method is not specifically limited here. If there is erroneous data, the reading side FIFO stops reading the data to avoid reading more erroneous data or generating anomalies. Moreover, the reading user side feeds back an error flag signal to the writing user side to notify the writing user side that there is an error in the data transmission so as to adopt the corresponding error correction mechanism. Among them, the error flag signal can be synchronized by a dual trigger to ensure the stability and reliability of cross-clock domain signal synchronization.

[0034] At the same time, the error flag signal includes at least a pause signal and a read address corresponding to the error data, so that the user side can more accurately locate the error data and the correct data corresponding to the error data. The error flag signal can also be transmitted through the cross-clock domain synchronization module inside the asynchronous FIFO to ensure the correct synchronous conversion of the read address.

[0035] Step S2: The writing user side suspends writing data of the writing side FIFO according to the suspension signal, and transmits corresponding correct data according to the read address corresponding to the erroneous data to replace the erroneous data.

[0036] Specifically, the writing user side pauses the writing of the writing side FIFO according to the pause signal, so as to avoid writing more erroneous data when the data being transmitted is associated with the previous erroneous data. The writing user side can also determine the corresponding correct data according to the read address corresponding to the erroneous data, and the writing user side instructs the writing side FIFO to rewrite the corresponding correct data into the asynchronous FIFO, thereby replacing the erroneous data. It should be noted that the replacement here can mean inserting correct data when there is a data missing error, overwriting erroneous data when there is data disorder, etc., so as to retransmit the correct data.

[0037] According to the above description, the data transmission method of the asynchronous FIFO of the present application obtains the configuration bit of the asynchronous FIFO when the asynchronous FIFO performs data transmission. If the configuration bit is equal to the first configuration value, the reading user side detects whether there is an error in the data read by the read side FIFO. If there is erroneous data, the reading of the data is stopped, and the reading user side feeds back an error flag signal to the writing user side. The writing user side pauses the writing of the write side FIFO according to the pause signal, and transmits the corresponding correct data to replace the erroneous data according to the read address corresponding to the erroneous data, thereby achieving the transmission efficiency and data accuracy of real-time data transmission.

[0038] It should be noted that, although the above embodiment emphasizes that the method performs detection and retransmission during data transmission, in actual applications, the method is not limited to performing detection and retransmission after data transmission is completed.

[0039] In some embodiments, reference Figure 3 , the data transmission method of the present application also includes: Step S101: When the asynchronous FIFO is transmitting data, the asynchronous FIFO obtains the write flag of the write side FIFO and the read flag of the read side FIFO, wherein the write flag includes full, nearly full, half full, and empty flags, and the read flag includes full, half empty, nearly empty, and full flags.

[0040] Specifically, asynchronous FIFO is used for data transmission between different clock domains. Writing data is controlled by the write clock signal, and the write pointer indicates the location of the write data. Reading data is controlled by the read clock signal, and the read pointer indicates the location of the read data. The write flag of the write-side FIFO can be determined by comparing the write pointer and the temporary write address: If the write pointer is different from the first slice of the temporary write address, and the write pointer is the same as the second slice of the temporary write address, it is determined to be a full flag; If the write pointer is the same as the first slice of the temporary write address, and the value of the second slice of the write pointer minus the second slice of the temporary write address is greater than or equal to the half-full threshold, and the value of the second slice of the temporary write address minus the second slice of the write pointer is less than or equal to the half-full threshold, it is determined as a half-full flag; If the write pointer is the same as the first slice of the temporary write address, and the difference between the write pointer and the second slice of the temporary write address is greater than the near-full low threshold, and the value of the second slice of the temporary write address minus the second slice of the write pointer is less than the half-full threshold; then it is determined as a near-full flag; If the write pointer is the same as the first slice of the temporary write address, and the difference between the write pointer and the second slice of the temporary write address is less than the half-full threshold, and the value of the second slice of the temporary write address minus the second slice of the write pointer is greater than the half-full threshold, it is judged as an empty flag.

[0041] Similarly, the read flag of the read-side FIFO can be determined by comparing the read pointer with the temporary read address: If the read pointer is the same as the temporary read address, it is determined to be a read empty flag; If the read pointer is the same as the first slice of the temporary read address, and the second slice of the temporary read address minus the second slice of the read pointer is less than or equal to the half-empty threshold, and the second slice of the read pointer minus the second slice of the temporary read address is greater than the half-empty threshold, it is determined as a half-empty flag; If the read pointer is the same as the first slice of the temporary read address, and the second slice of the temporary read address minus the second slice of the read pointer is less than or equal to the near-empty low threshold, and the second slice of the read pointer minus the second slice of the temporary read address is greater than the near-empty high threshold, it is determined as a near-empty flag; If the read pointer is the same as the first slice of the temporary read address, and the second slice of the temporary read address minus the second slice of the read pointer is greater than the half-empty threshold, and the second slice of the read pointer minus the second slice of the temporary read address is less than or equal to the half-empty threshold, it is determined as a read full flag.

[0042] Among them, the first slice represents the total bit width of the write pointer / temporary write address / read pointer / temporary read address minus 1; the second slice represents the continuous bits starting from the 0th bit of the bit vector and ending at the total bit width of the write pointer / temporary write address / read pointer / temporary read address minus 2 bits.

[0043] Furthermore, the empty and full flags of the asynchronous FIFO are used to better coordinate the read and write data: data is written when the write enable signal is valid and the write-side FIFO is not full, and data is read when the read enable signal is valid and the read-side FIFO is not empty. Moreover, the real-time empty and full flags can be updated at the rising edge of the clock or the rising edge of the reset signal to coordinate the read and write data more accurately. Therefore, when the asynchronous FIFO is transmitting data, the write flag of the write-side FIFO and the read flag of the read-side FIFO are obtained to ensure the validity of the data transmission.

[0044] At the same time, the empty flag of the write side FIFO and the full flag of the read side FIFO can also be designed according to the specific needs of the user to improve the flexibility of the control logic of the present application. Among them, the generation of the empty flag and the full flag can be, but is not limited to, generated by adding a few additional cycles after the clock beats.

[0045] Step S102: If the configuration bit is equal to the second configuration value, the asynchronous FIFO performs data transmission between different clock domains according to the write flag and the read flag.

[0046] Specifically, when configured to be equal to the second configuration value (such as 0), the asynchronous FIFO transmits data between different clock domains according to the write flag and the speed flag, that is, at this time, there is no data error in the read side FIFO, the data correction mode is not triggered, and the asynchronous FIFO performs normal data transmission according to the write flag and the read flag.

[0047] Step S103: If the configuration bit is equal to the first configuration value, there is error data and the write flag is not a full flag, the write user side assigns the read address corresponding to the error data to the write address of the write side FIFO to stop writing data to the write side FIFO according to the pause signal.

[0048] Specifically, when writing data, the write pointer indicates the location of the current write data. Whenever data is written into the FIFO, the write pointer increments to point to the next writable location. Therefore, the write pointer points to the write address corresponding to the erroneous data in the write-side FIFO, and the write pointer is controlled not to increment, so as to suspend subsequent data writing operations.

[0049] More specifically, the write reset signal and the write clock signal can be used to control whether the write pointer is updated: If the write reset signal is low (i.e., reset state), the write pointer is cleared; Otherwise, if the configuration bit is equal to the second configuration value, and the write enable signal is high, and the write full flag is low (i.e., the FIFO is not full), the write pointer is incremented; Otherwise, if the configuration bit is equal to the first configuration value, and the write enable signal is high and the write full flag is low, the error flag signal is determined: if the error flag signal is high, the write pointer is updated to the value of the read pointer corresponding to the error data; if the error flag signal is low, the write pointer is incremented; Otherwise, the write pointer remains unchanged.

[0050] In this way, accurate control of the write pointer is ensured.

[0051] Step S104: if the configuration bit is equal to the first configuration value, there is error data and the read flag is not a read empty flag, the reading user side stops reading data from the read side FIFO according to the read address corresponding to the error data.

[0052] Specifically, when reading data, the read pointer indicates the current read data position. Each time data is read out, the read pointer increments to point to the next readable position. Therefore, the reading user side controls the read pointer not to increment according to the read address corresponding to the erroneous data to suspend subsequent data read operations of the read side FIFO.

[0053] More specifically, the read reset signal and the read clock signal can be used to control whether the read pointer is updated: If the read reset signal is low, the read address is reset; Otherwise, if the configuration bit is equal to the first configuration value, and the read enable signal is high and the read empty flag is low, the error flag signal is determined: if the error flag signal is high, the read pointer is updated to the read pointer corresponding to the error data; if the error flag signal is low, the read pointer is incremented; Otherwise, the read pointer remains unchanged.

[0054] In this way, accurate control of the read pointer is ensured, and the flexibility of the control logic of this application is improved.

[0055] According to the above description, by controlling the read and write pointers in more detail and accurately, the empty and full status of the asynchronous FIFO can be more accurately judged, so that the reading and writing of data can be more accurate, and at the same time, the normal transmission of the asynchronous FIFO is not affected, and the accurate reading and writing pointers are used to ensure that the erroneous data is accurately located and corrected. Moreover, it also avoids writing more erroneous data in the FIFO, avoids wasting the internal space of the asynchronous FIFO, further improves the efficiency and accuracy of data transmission, and maintains the accuracy of the data in the asynchronous FIFO and the stability of the system.

[0056] In order to adapt to the application scenario where the data transmitted before and after are related, in some embodiments, reference Figure 4 , step S2 comprises: Step S201: The write user side determines the write address corresponding to the error data in the write side FIFO according to the read address corresponding to the error data in response to the first preset information.

[0057] Among them, the first preset information is used to identify the application scenario in which the data transmitted before and after are related, that is, under the first preset information, it means that the erroneous data and the data after the erroneous data need to be rewritten. For example, in a certain video stream processing system, there is an error in the video frame data, and you can choose to retransmit the erroneous video frame and the video frames after it. For another example, the data interaction between some internal systems of an enterprise usually has a strong correlation. If an error occurs, the erroneous data and the data after it need to be resynchronized.

[0058] Specifically, in an asynchronous FIFO, reading and writing data occur in different clock domains. A mapping relationship can be preset to map the read address space to the write address space. For example, each time data is written, the corresponding write address and read address are recorded and stored to construct a mapping relationship between the read and write addresses. This facilitates the writing user side to use the preset mapping relationship to find and determine the corresponding write address of the erroneous data in the write-side FIFO according to the read address corresponding to the erroneous data.

[0059] Step S202: The write user side instructs the write pointer of the write side FIFO to point to the write address corresponding to the erroneous data again, and the write side FIFO recovers the write data starting from the write address corresponding to the erroneous data, rewrites the erroneous data and the data after the erroneous data, and replaces the erroneous data and the data after the erroneous data with correct data.

[0060] Specifically, the write pointer of the write side FIFO can be reset through a state machine or control logic, so that the write pointer of the write side FIFO is reset to the write address corresponding to the erroneous data, and the write user side recovers the write data and starts writing the correct data to overwrite the erroneous data and the data after the erroneous data, thereby ensuring the accuracy of the data.

[0061] Step S203: After recovering the write data, the writing user side feeds back a resolution flag signal to the reading user side to notify the reading user side that the error has been corrected.

[0062] Step S204: The reading user side responds to the resolution flag signal and instructs the reading side FIFO to restart reading data from the read address corresponding to the error data, thereby continuing to read data after the error data to ensure that the corrected data are all re-read.

[0063] Through the above method, in the scenario where the data transmitted before and after are related, the erroneous data and the data after the erroneous data in the asynchronous FIFO can be effectively detected and repaired, and the data can be re-read from the read address corresponding to the original erroneous data after correction to ensure the consistency and integrity of the data, while improving the flexibility and reusability of the method.

[0064] In some embodiments, reference Figure 5 , step S2 may further include: Step S211: The writing user side responds to the second preset information and determines the correct data corresponding to the erroneous data according to the read address corresponding to the erroneous data. The second preset information indicates that only the erroneous data is corrected, including but not limited to only inserting and replacing the missing data, only overwriting and correcting the erroneous data, that is, not retransmitting the data after the erroneous data.

[0065] Step S212: The writing user side writes the correct data into the storage body to replace the erroneous data with the correct data. Specifically, when only the erroneous data is replaced, the write side FIFO does not need to be used for rewriting, and only the correct data needs to be retransmitted through the storage body to save FIFO resources.

[0066] Step S213: After replacing the erroneous data with the correct data, the writing user side performs a handshake with the reading user side to notify the reading user side that the data has been updated.

[0067] Step S214: the writing user side instructs the writing side FIFO to resume writing data from the address when it was paused; the reading user side responds to the data being updated and resumes reading data after re-reading the correct data.

[0068] After re-reading the correct data, the reading user side resumes reading the data from the read address at the time of suspension.

[0069] In this way, in the scenario where only erroneous data is replaced, erroneous data in the asynchronous FIFO can be effectively and quickly detected and repaired, and after correction, it can be synchronously read from the user side through handshake to prevent asynchronous FIFO data overflow and ensure the correct transmission of data between different clock domains, while further improving the practicality, flexibility and multiplexability of this method.

[0070] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0071] Based on the same inventive concept, the embodiment of the present application also provides an asynchronous FIFO for implementing the above-mentioned problem. The implementation scheme for solving the problem provided by the asynchronous FIFO is similar to the implementation scheme recorded in the above-mentioned method, so the specific limitations in the asynchronous FIFO embodiment provided below can refer to the limitations of the data transmission method of an asynchronous FIFO above, which will not be repeated here.

[0072] The present application embodiment also provides an asynchronous FIFO, referring to Figure 6The asynchronous FIFO includes a write-side FIFO for connecting to a write user side to write data, a storage body for accessing data, and a read-side FIFO for connecting to a read user side to read data. The asynchronous FIFO is used to transmit data between the write user side and the read user side to implement a data transmission method of an asynchronous FIFO in any of the above embodiments. The data correction module is used to transmit corresponding correct data to replace the erroneous data when erroneous data exists.

[0073] In some embodiments, the asynchronous FIFO also includes a cross-clock domain synchronization module for realizing address synchronization conversion from the write side FIFO to the read side FIFO and from the read side FIFO to the write side FIFO. The write side FIFO includes a write pointer, a full judgment module, a data conversion module and a data correction module. The write pointer is used to indicate the location of the current write data. The data conversion module is used for mutual conversion between Gray code data and binary code data. The full judgment module is used to receive the synchronized write pointer and read pointer signals to judge the write flag of the write side FIFO. The write flag includes full, nearly full, half full, and empty flags. The full judgment module feeds back the write flag signal to the write user side and the write pointer to control the data write operation. The write pointer is also synchronized with the write clock, connected to the write address input end of the storage body, and writes the data to the storage body. The write data operation is performed on the rising edge of the write clock. The data correction module is used to transmit the corresponding correct data to replace the erroneous data when there is erroneous data. In order to improve the consistency of the data and prevent errors in the data transmission process.

[0074] The read side FIFO includes a read pointer, an empty judgment module and a data conversion module. The read pointer is used to indicate the location of the current read data. The data conversion module is used for mutual conversion between Gray code data and binary code data. The empty judgment module is used to judge the read flag of the read side FIFO. The read flag includes a full flag, half empty, nearly empty, and read empty. The empty judgment module feeds back the read flag signal to the read user side and the read pointer to control the data reading operation.

[0075] Through the collaborative work of these modules and signals, the asynchronous FIFO can reliably transmit data between different clock domains and has the function of correcting erroneous data, thereby improving the accuracy and efficiency of data transmission.

[0076] In one embodiment, the present application further provides a computer-readable storage medium, characterized in that a program code is stored in the computer-readable storage medium, and the program code is called by a processor to execute an asynchronous FIFO data transmission method such as in any embodiment.

[0077] In one embodiment, the present application also provides an electronic device, comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute an asynchronous FIFO data transmission method as in any of the above embodiments.

[0078] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device / equipment / system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0079] It should be noted that, for those of ordinary skill in the art, several improvements and modifications may be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of a separate embodiment for the sake of clarity may also be provided in a single embodiment by combination. Conversely, various features of the present disclosure described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A data transmission method of an asynchronous FIFO, characterized in that: The asynchronous FIFO includes a write-side FIFO for connecting to a write user side to write data, a storage body for accessing data, and a read-side FIFO for connecting to a read user side to read data, so that the asynchronous FIFO performs data transmission between the write user side and the read user side, and the method includes: When the asynchronous FIFO is transmitting data, the configuration bit of the asynchronous FIFO is obtained. If the configuration bit is equal to the first configuration value, the reading user side detects whether there is an error in the data read by the reading side FIFO. If there is error data, the reading user side stops reading the data, and the reading user side feeds back an error flag signal to the writing user side; wherein the error flag signal at least includes a pause signal and a read address corresponding to the error data; The write user side suspends writing data of the write side FIFO according to the pause signal, and transmits corresponding correct data according to the read address corresponding to the erroneous data to replace the erroneous data.

2. The data transmission method of an asynchronous FIFO according to claim 1, characterized in that: The writing user side determines, in response to the first preset information, a writing address corresponding to the error data in the writing side FIFO according to the reading address corresponding to the error data; The write user side instructs the write pointer of the write side FIFO to point to the write address corresponding to the erroneous data again, and the write side FIFO recovers the write data starting from the write address corresponding to the erroneous data, rewrites the erroneous data and the data after the erroneous data, and replaces the erroneous data and the data after the erroneous data with correct data.

3. The data transmission method of an asynchronous FIFO according to claim 2, characterized in that: After recovering the write data, the writing user side feeds back a solution mark signal to the reading user side; The reading user side instructs the reading side FIFO to restart reading data from the reading address corresponding to the erroneous data in response to the resolution flag signal.

4. The data transmission method of an asynchronous FIFO according to claim 1, characterized in that: The writing user side determines correct data corresponding to the erroneous data according to the read address corresponding to the erroneous data in response to the second preset information, writes the correct data into the storage body, and only replaces the erroneous data with correct data.

5. The data transmission method of an asynchronous FIFO according to claim 4, characterized in that: After replacing the erroneous data with correct data, the writing user side performs a handshake with the reading user side to notify the reading user side that the data has been updated; The writing user side instructs the writing side FIFO to resume writing data from the address at the time of suspension; the reading user side responds to the data being updated and resumes reading data after re-reading the correct data.

6. The data transmission method of an asynchronous FIFO according to claim 1, characterized in that: When the asynchronous FIFO performs data transmission, the asynchronous FIFO obtains a write flag of the write-side FIFO and a read flag of the read-side FIFO, wherein the write flag includes a write-full flag, a nearly full flag, a half-full flag, and an empty flag, and the read flag includes a full flag, a half-empty flag, a nearly empty flag, and a read-empty flag; If the configuration bit is equal to a second configuration value, the asynchronous FIFO performs data transmission between different clock domains according to the write flag and the read flag.

7. The data transmission method of an asynchronous FIFO according to claim 6, characterized in that: If the configuration bit is equal to the first configuration value, there is error data and the write flag is not a full flag, the write user side assigns the read address corresponding to the error data to the write address of the write side FIFO to stop the write side FIFO from writing data according to the pause signal; If the configuration bit is equal to the first configuration value, there is error data and the read flag is not a read empty flag, the reading user side stops reading data from the read side FIFO according to the read address corresponding to the error data.

8. An asynchronous FIFO, characterized in that: The asynchronous FIFO includes a write-side FIFO for connecting to a write user side to write data, a storage body for accessing data, and a read-side FIFO for connecting to a read user side to read data. The asynchronous FIFO is used to transmit data between the write user side and the read user side to implement an asynchronous FIFO data transmission method according to any one of claims 1 to 7. The write-side FIFO also includes: The data correction module is used to transmit corresponding correct data to replace the erroneous data when erroneous data exists.

9. An asynchronous FIFO according to claim 8, characterized in that: The write-side FIFO includes a full judgment module, which is used to judge the write flag of the write-side FIFO; the read-side FIFO includes an empty judgment module, which is used to judge the read flag of the read-side FIFO, wherein the write flag includes full, nearly full, half full, and empty flags, and the read flag includes full flag, half empty, nearly empty, and read empty.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes, and the program codes are called by a processor to execute the asynchronous FIFO data transmission method according to any one of claims 1 to 7.

11. An electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute an asynchronous FIFO data transmission method as described in any one of claims 1 to claim 7.

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