Chip data acquisition method

Abstract

The invention relates to the technical field of wireless communication IC (integrated circuit) chips, and discloses a chip data acquisition method, which comprises the following steps of: acquiring physical layer acquisition data of different nodes in a physical layer and preprocessing the physical layer acquisition data; wherein the physical layer acquisition data comprises physical layer data and physical layer maintenance and measurement signals; sOC working information is recorded while physical layer collection data is collected, so that a current SOC maintenance and measurement signal is collected through a data bus; combining the SOC maintenance and measurement signal and the physical layer acquisition data into an acquisition signal, and performing data processing on the acquisition signal; wherein the data processing comprises data selection processing, extraction, trigger control and trigger length control; and the acquisition signal after data processing is written into the Memory unit through the data bus to be recorded or is output from the direct peripheral interface. According to the chip data acquisition method provided by the invention, the physical layer data and the maintenance signal of the chip are acquired, and the technical problem of how to acquire the chip data more efficiently, accurately and comprehensively is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communication IC chips, and in particular to a chip data acquisition method. Background Art

[0002] Chip data acquisition is a common status monitoring method for wireless communication IC chips. It determines the working status of the chip by collecting maintenance signals and recording physical layer data, and provides support for troubleshooting and data analysis. For chip data acquisition, the prior art first uses a physical layer data frame acquisition device to synchronously collect multi-node data, including multiple WTB physical layer interfaces, data processing units, and control units; then obtains the data collected by the interface, including a communication controller, generates a control signal to the communication controller, and controls multiple WTB physical layer interfaces to synchronously collect data; finally, controls multiple WTB physical layer interfaces to start working at the same clock beat to synchronously collect physical layer data between all WTB nodes.

[0003] However, the existing chip data collection methods have the following problems: 1. The data collection control mode is simple and the collection mode is not flexible enough. 2. The collected data is redundant, resulting in a waste of storage space. 3. The real-time performance of the collected data is poor. 4. The collected data type is single. Summary of the invention

[0004] The present invention provides a chip data acquisition method, which acquires chip physical layer data and maintenance measurement signals, and solves the technical problem of how to acquire chip data more efficiently, accurately and comprehensively.

[0005] The present invention provides a chip data acquisition method, comprising: Collecting physical layer data collected from different nodes in the physical layer and preprocessing the data; wherein the physical layer collected data includes physical layer data and physical layer maintenance and measurement signals; While collecting data at the physical layer, record the SOC working information to collect the current SOC maintenance signal through the data bus; Combining the SOC maintenance signal and the physical layer acquisition data into an acquisition signal, and performing data processing on the acquisition signal; wherein the data processing includes data selection processing, extraction, trigger control and trigger length control; The collected signal after data processing is written into the Memory unit for recording through the data bus or output from the direct peripheral interface.

[0006] Furthermore, the step of collecting physical layer data from different nodes in the physical layer and preprocessing the data includes: Collect physical layer data and physical layer maintenance signals of different nodes in the physical layer according to the collection node selection instruction and the collection enable selection instruction; wherein the physical layer data includes I-channel data, Q-channel data and physical layer real-time AGC gain signal; The physical layer data and the physical layer maintenance signal are converted in the clock domain to be synchronized to the data bus clock domain.

[0007] Further, in the step of combining the SOC maintenance signal and the physical layer collected data into a collected signal and performing data processing on the collected signal, the data selection process includes: Receive the control instruction of the bus, and combine the collected signals into three data frames according to the control instruction, and add a timestamp frame header to form a data frame; wherein the three data frames include: only containing physical layer collected data, only containing SOC maintenance and measurement signals, and containing both physical layer collected data and SOC maintenance and measurement signals.

[0008] Further, in the step of combining the SOC maintenance signal and the physical layer collected data into a collected signal and performing data processing on the collected signal, the extraction includes: According to the configured extraction parameters, the corresponding multiple extraction operation is performed on the data after the data frame is composed. Specifically, the sampling data is subjected to 1 / N extraction operation according to the configured extraction multiple, that is, when the extraction multiple is configured as N, the first one of every N collected data is extracted as the extracted data, and the remaining data is discarded; when the extraction multiple is configured as 0, no extraction operation is performed; The extracted data frame is written into the Memory unit through the data bus for recording or directly output from the peripheral interface.

[0009] Further, in the step of combining the SOC maintenance signal and the physical layer collected data into a collection signal and performing data processing on the collection signal, the trigger control includes: For the physical layer data collection and SOC maintenance signal, two modes, edge trigger and condition trigger, are set, and the trigger conditions are configured according to the needs. When it is determined that the trigger conditions are met, counting begins. Among them, the edge trigger is triggered when the level of a bit data in the judgment signal changes; the condition trigger is triggered when the data changes to the set data value.

[0010] Further, in the step of combining the SOC maintenance signal and the physical layer acquisition data into an acquisition signal and performing data processing on the acquisition signal, triggering length control includes: After the trigger condition is met, the trigger count is increased by 1 each time a data frame is recorded. When the count is the same as the trigger length, the sending of recorded data to the Memory unit or peripheral interface is stopped.

[0011] Furthermore, edge and conditional trigger acquisition is performed for physical layer acquisition data, including: Collect physical layer I-channel data, Q-channel data and physical layer real-time AGC gain signal according to configuration parameters, and collect physical layer maintenance signal at the same time; While collecting data, it is determined whether the configured trigger conditions are met. When the trigger conditions are met, the counter starts counting and records the trigger length to end the collection. Among them, when monitoring the AGC gain is the trigger condition, the conditional trigger determines that the AGC gain is equal to the configured trigger condition, and the trigger is satisfied. The counter starts recording the trigger data length, and the collection ends when the counter is equal to the configured counting length. The edge trigger determines the edge change of the AGC lock mark as the trigger condition, selects the rising edge or falling edge of the signal, starts counting after the trigger condition is met, and records the trigger length to end the collection.

[0012] Furthermore, the abnormal trigger collection for SOC includes: The maintenance and measurement signals of various parts of the SOC are collected through the data bus, and the abnormal SOC maintenance and measurement signal status that needs to be monitored is configured as the trigger condition. When the trigger condition is met, the physical layer data and maintenance and measurement signals are recorded, and the analysis data is exported through the data interface to troubleshoot the cause of the SOC abnormality.

[0013] The present invention also provides a chip data acquisition system, based on the chip data acquisition method as described above, comprising a physical layer acquisition module, a SOC acquisition module, a data processing module, a data bus, a memory unit and a peripheral interface, wherein the data processing module is respectively connected to the physical layer acquisition module, the SOC acquisition module and the data bus, and the data bus is also connected to the memory unit and the peripheral interface; The physical layer acquisition module acquires the physical layer data and physical layer maintenance signals of different nodes in the physical layer according to the acquisition node selection instruction and acquisition enable selection instruction given by the acquisition control module, synchronizes them to the data bus clock domain through clock domain conversion, and sends them to the data processing module; The SOC acquisition module collects the current SOC maintenance signal through the data bus while collecting the physical layer signal, and sends it to the data processing module; The data processing module performs data processing on the physical layer data, the physical layer maintenance signal and the SOC maintenance signal, including data selection processing, extraction, trigger control and trigger length control; The memory unit receives the recorded data sent by the data processing module through the data bus, reads the corresponding data according to the input address when exporting, and then sends it to the data interface through the data bus; The peripheral interface sends the recorded data exported from the memory unit or the data bus to the outside of the chip.

[0014] The beneficial effects of the present invention are: 1. The present invention introduces chip maintenance signal recording, which not only records physical layer data but also includes multi-dimensional information such as physical layer working status, link status, SOC status, etc., thereby improving the real-time and integrity of recorded data and providing more comprehensive data support for problem analysis and performance optimization.

[0015] 2. Flexibly select physical layer data and maintenance signal for recording to reduce data redundancy and improve storage space utilization.

[0016] 3. It has a configurable data extraction mechanism, which can save memory storage space and record more data while ensuring the useful information of the data.

[0017] 4. The introduction of trigger mechanism can quickly locate the data position of corresponding conditions. At the same time, under the control of trigger length, it can quickly find the data of corresponding length before and after the trigger point, so as to analyze data more efficiently.

[0018] 5. The entire data acquisition system works independently. When data acquisition is not needed, the entire system can be bypassed to reduce chip power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the process of the chip data acquisition method of the present invention.

[0020] Figure 2 This is a flow chart for triggering physical layer data collection in the present invention.

[0021] Figure 3 This is a trigger flow chart for SOC abnormality trigger collection in the present invention.

[0022] Figure 4 It is a structural schematic diagram of the chip data acquisition system of the present invention.

[0023] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0024] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0025] The present invention is applied to the fields of vehicle-mounted Bluetooth chips, tire pressure monitoring, digital tags, chip monitoring, digital keys, etc. In the wireless communication IC chip, the channel physical layer baseband data and maintenance signals are collected for scenarios such as data analysis, monitoring, IC chip troubleshooting, upgrade optimization, etc.; the collected data can be recorded after being extracted by different multiples to save storage space; various trigger conditions for recording data can be set, such as specific value triggering and edge triggering; when the trigger conditions are met, the collected data of the corresponding length before or after the trigger point can be recorded according to the configured trigger length.

[0026] like Figure 1 As shown, the present invention provides a chip data acquisition method, comprising: S1. Collect physical layer data collected from different nodes in the physical layer and perform preprocessing; wherein the physical layer collected data includes physical layer data and physical layer maintenance and measurement signals.

[0027] Specifically include: 1) Physical layer data acquisition: Collect physical layer data, including I, Q channel data and physical layer real-time AGC gain signal; according to the acquisition node selection instructions and acquisition enable selection instructions given by the acquisition control module, collect data from different nodes in the physical layer, synchronize them to the data bus clock domain through clock domain conversion, and send them to the data processing module.

[0028] 2) Physical layer maintenance signal acquisition: Collect the maintenance signal of the physical layer and work synchronously with the physical layer data acquisition module to ensure the real-time performance of the maintenance signal and the collected data; the maintenance signal also needs to be converted in the clock domain before being sent to the data processing module.

[0029] S2. Record SOC working information while collecting data at the physical layer to collect current SOC maintenance signals through the data bus.

[0030] SOC maintenance signal acquisition: Collect the current SOC maintenance signal through the data bus, and record the SOC working information while collecting the physical layer signal to monitor the SOC working status.

[0031] S3. Combining the SOC maintenance signal and the physical layer acquisition data into an acquisition signal, and performing data processing on the acquisition signal; wherein the data processing includes data selection processing, extraction, trigger control and trigger length control.

[0032] Data processing specifically includes: 1) Data selection processing: According to the control instructions, the input acquisition signals are combined into three types of data frames, including only physical layer acquisition data, only maintenance measurement signals, and both physical layer data and maintenance measurement signals; and a timestamp frame header is added to form a data frame.

[0033] 2) Extraction: According to the configured extraction parameters, the corresponding multiple extraction operation is performed on the data that constitutes the data frame. When the extraction multiple is configured to 0, no extraction operation is performed; the extracted data frame is written into the Memory unit through the data bus for record or directly output from the peripheral interface.

[0034] The specific decimation operation is: perform 1 / N decimation operation on the sampled data according to the configured decimation multiple, that is, when the decimation multiple is configured as N, the first one of every N collected data is extracted as the extracted data, and the remaining data is discarded; when the decimation multiple is configured as 0, no decimation operation is performed. That is, perform 1 / N decimation operation on the sampled data according to the configured decimation multiple, when the decimation multiple is configured as 4, the first one of every 4 collected data is extracted as the extracted data, and the remaining three data are discarded, when the decimation multiple is 8, the first one of 8 data is extracted and the remaining 7 are discarded, and so on.

[0035] 3) Trigger control: There are two modes for data and measurement signals: edge trigger and condition trigger. The trigger condition can be configured according to needs, and counting starts when the trigger condition is met.

[0036] a. Edge triggering is to determine whether a bit of data in the signal changes level when it is triggered, that is, the rising edge or falling edge. For example, when it is necessary to collect data before and after the physical layer link synchronization, the rising edge of the physical layer synchronization indication signal (single bit, pulled high during synchronization) can be configured as the trigger condition.

[0037] b. Conditional triggering is triggered when the data changes to a certain value, such as when the AGC gain changes from 0. If the trigger condition is set to AGC=3, a trigger is generated when the AGC gain value changes to 3. For example, when you need to observe the data when the AGC gain is adjusted to a certain intensity, configure the corresponding AGC gain value as the trigger condition, and collect data when the AGC is adjusted to the corresponding value.

[0038] 4) Trigger length control: After the trigger condition is met, the trigger count is increased by 1 each time a data frame is recorded. When the count is the same as the trigger length, the sending of recorded data to the Memory unit or peripheral interface is stopped, and the data acquisition process ends.

[0039] Specifically, Figure 2 As shown, edge and conditional trigger acquisition is performed for physical layer acquisition data, including: T1. The trigger function can be used to quickly and accurately locate the collected data. After the system is started, the physical layer I, Q data and AGC gain value are collected according to the configuration parameters, and the maintenance signal of the physical layer is collected at the same time.

[0040] T2. While collecting data, determine whether the configured trigger conditions are met. When the trigger conditions are met, the counter starts counting and records the trigger length to end the collection. Taking monitoring AGC gain as the trigger condition as an example, the conditional trigger determines that the AGC gain is equal to the configured trigger condition, and the trigger is satisfied. The counter starts recording the trigger data length, and the collection ends when the counter is equal to the configured count length. The edge trigger determines the edge change of the AGC lock mark as the trigger condition. You can choose to judge the rising edge or falling edge of the signal (the rising edge trigger of the AGC lock signal indicates that the AGC adjustment has reached a stable state and the physical layer link connection is stable; the falling edge AGC loses lock, and the physical layer link signal may swing greatly at this time, and the AGC gain value needs to be readjusted). After the trigger conditions are met, counting starts, and the collection ends when the trigger length is recorded.

[0041] like Figure 3 As shown, the abnormal trigger collection for SOC includes: The maintenance and measurement signals of various parts of the SOC are collected through the data bus. In order to monitor the status information of the chip when the SOC is in an abnormal state, the abnormal SOC maintenance and measurement signal status that needs to be monitored is configured as a trigger condition (such as monitoring the CPU working status mark, triggering data collection when the CPU works abnormally, collecting maintenance and measurement signals to analyze the status information of various parts in the chip, and troubleshooting the causes of the abnormal state of the CPU) to the collection system. When the trigger conditions are met, the physical layer data and maintenance and measurement signals are recorded, and the analysis data is exported through the data interface to troubleshoot the causes of the SOC abnormality. Since the SOC maintenance and measurement signals and the real-time data of the physical layer are recorded at the same time, the analysis of SOC abnormal problems will be more accurate and comprehensive.

[0042] S4, writing the collected signal after data processing into the Memory unit for recording through the data bus or outputting it from the direct peripheral interface.

[0043] like Figure 4 As shown, the present invention also provides a chip data acquisition system, based on the chip data acquisition method as described above, including a physical layer acquisition module, a SOC acquisition module, a data processing module, a data bus, a memory unit and a peripheral interface, the data processing module is respectively connected to the physical layer acquisition module, the SOC acquisition module and the data bus, the data bus is also connected to the memory unit and the peripheral interface, and the data processing module also includes a system control unit.

[0044] (1) Physical layer acquisition module: 1) Physical layer data acquisition: Collect physical layer data, including I, Q channel data and physical layer real-time AGC gain signal; according to the acquisition node selection instructions and acquisition enable selection instructions given by the acquisition control module, collect data from different nodes in the physical layer, synchronize them to the data bus clock domain through clock domain conversion, and send them to the data processing module.

[0045] 2) Physical layer maintenance signal acquisition: Collect the maintenance signal of the physical layer and work synchronously with the physical layer data acquisition module to ensure the real-time performance of the maintenance signal and the collected data; the maintenance signal also needs to be converted in the clock domain before being sent to the data processing module.

[0046] (2) SOC acquisition module: collects the current SOC maintenance signal through the data bus, and records the SOC working information while collecting the physical layer signal to monitor the SOC working status.

[0047] (3) Data processing module: performs data processing on physical layer data, physical layer maintenance and measurement signals, and SOC maintenance and measurement signals, including data selection processing, extraction, trigger control, and trigger length control.

[0048] 1) Data selection processing: According to the control instruction, the input acquisition signal is combined into three types of data frames, including only physical layer acquisition data, only maintenance measurement signals, and both physical layer data and maintenance measurement signals; and a timestamp frame header is added to form a data frame; 2) Extraction: According to the configured extraction parameters, the corresponding multiple extraction operation is performed on the framed data. When the extraction multiple is configured to 0, no extraction operation is performed; the extracted data frame is written into the Memory unit through the data bus for recording or directly output from the peripheral interface; 3) Trigger control: There are two modes for data and measurement signals: edge trigger and condition trigger. The trigger condition can be configured according to the needs. When the trigger condition is met, counting starts; 4) Trigger length control: After the trigger condition is met, the trigger count is increased by 1 each time a data frame is recorded. When the count is the same as the trigger length, the sending of recorded data to the Memory unit or peripheral interface is stopped, and the data acquisition process ends.

[0049] (4) System control: Receive control instructions from the bus, transmit corresponding control instructions to each module, and monitor the working status of the acquisition system.

[0050] (5) Memory unit: Receives the recorded data sent by the acquisition system through the data bus during recording. When exporting, it reads the corresponding data according to the input address and then sends it to the data interface through the data bus.

[0051] (6) Peripheral interface: sends the recorded data exported from the memory unit or data bus to the outside of the chip.

[0052] The present invention introduces chip maintenance signal recording, which includes multi-dimensional information such as physical layer working status, link status, SOC status, etc. while recording physical layer data, thereby improving the real-time and integrity of recorded data and providing more comprehensive data support for problem analysis and performance optimization; it can flexibly select physical layer data and maintenance signal for recording, reduce data redundancy, and improve storage space utilization; at the same time, the present invention has a configurable data extraction mechanism, which can save memory storage space and record more data while ensuring useful data information; the present invention also introduces a trigger mechanism, which can quickly locate the data position of the corresponding conditions, and can quickly find the data of the corresponding length before and after the trigger point under the control of the trigger length, so as to analyze the data more efficiently. The entire data acquisition system works independently, and can bypass the entire system when data acquisition is not needed, thereby reducing chip power consumption.

[0053] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0054] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip data acquisition method, characterized in that: include: Collecting physical layer data collected from different nodes in the physical layer and preprocessing the data; wherein the physical layer collected data includes physical layer data and physical layer maintenance and measurement signals; While collecting data at the physical layer, record the SOC working information to collect the current SOC maintenance signal through the data bus; Combining the SOC maintenance signal and the physical layer acquisition data into an acquisition signal, and performing data processing on the acquisition signal; wherein the data processing includes data selection processing, extraction, trigger control and trigger length control; The collected signal after data processing is written into the Memory unit for recording through the data bus or output from the direct peripheral interface.

2. The chip data acquisition method according to claim 1, characterized in that: The step of collecting physical layer data from different nodes in the physical layer and preprocessing the data comprises: Collect physical layer data and physical layer maintenance signals of different nodes in the physical layer according to the collection node selection instruction and the collection enable selection instruction; wherein the physical layer data includes I-channel data, Q-channel data and physical layer real-time AGC gain signal; The physical layer data and the physical layer maintenance signal are converted in the clock domain to be synchronized to the data bus clock domain.

3. The chip data acquisition method according to claim 2, characterized in that: In the step of combining the SOC maintenance signal and the physical layer collected data into a collected signal and performing data processing on the collected signal, the data selection process includes: Receive the control instruction of the bus, and combine the collected signals into three data frames according to the control instruction, and add a timestamp frame header to form a data frame; wherein the three data frames include: only containing physical layer collected data, only containing SOC maintenance and measurement signals, and containing both physical layer collected data and SOC maintenance and measurement signals.

4. The chip data acquisition method according to claim 3, characterized in that: In the step of combining the SOC maintenance signal and the physical layer collected data into a collected signal and performing data processing on the collected signal, the extraction includes: According to the configured extraction parameters, the corresponding multiple extraction operation is performed on the data after the data frame is composed. Specifically, the sampling data is subjected to 1 / N extraction operation according to the configured extraction multiple, that is, when the extraction multiple is configured as N, the first one of every N collected data is extracted as the extracted data, and the remaining data is discarded; when the extraction multiple is configured as 0, no extraction operation is performed; The extracted data frame is written into the Memory unit through the data bus for recording or directly output from the peripheral interface.

5. The chip data acquisition method according to claim 4, characterized in that: In the step of combining the SOC maintenance signal and the physical layer collected data into a collection signal and performing data processing on the collection signal, the trigger control includes: For the physical layer data collection and SOC maintenance signal, two modes, edge trigger and condition trigger, are set, and the trigger conditions are configured according to the needs. When it is determined that the trigger conditions are met, counting begins. Among them, the edge trigger is triggered when the level of a bit data in the judgment signal changes; the condition trigger is triggered when the data changes to the set data value.

6. The chip data acquisition method according to claim 5, characterized in that: In the step of combining the SOC maintenance signal and the physical layer acquisition data into an acquisition signal and performing data processing on the acquisition signal, triggering length control includes: After the trigger condition is met, the trigger count is increased by 1 each time a data frame is recorded. When the count is the same as the trigger length, the sending of recorded data to the Memory unit or peripheral interface is stopped.

7. The chip data acquisition method according to claim 6, characterized in that: Edge and conditional trigger acquisition for physical layer acquisition data, including: Collect physical layer I-channel data, Q-channel data and physical layer real-time AGC gain signal according to configuration parameters, and collect physical layer maintenance signal at the same time; While collecting data, it is determined whether the configured trigger conditions are met. When the trigger conditions are met, the counter starts counting and records the trigger length to end the collection. Among them, when monitoring the AGC gain is the trigger condition, the conditional trigger determines that the AGC gain is equal to the configured trigger condition, and the trigger is satisfied. The counter starts recording the trigger data length, and the collection ends when the counter is equal to the configured counting length. The edge trigger determines the edge change of the AGC lock mark as the trigger condition, selects the rising edge or falling edge of the signal, starts counting after the trigger condition is met, and records the trigger length to end the collection.

8. The chip data acquisition method according to claim 6, characterized in that: Abnormal trigger collection for SOC, including: The maintenance and measurement signals of various parts of the SOC are collected through the data bus, and the abnormal SOC maintenance and measurement signal status that needs to be monitored is configured as the trigger condition. When the trigger condition is met, the physical layer data and maintenance and measurement signals are recorded, and the analysis data is exported through the data interface to troubleshoot the cause of the SOC abnormality.

9. A chip data acquisition system, characterized in that: A chip data acquisition method according to any one of claims 1 to 8, comprising a physical layer acquisition module, a SOC acquisition module, a data processing module, a data bus, a memory unit and a peripheral interface, wherein the data processing module is respectively connected to the physical layer acquisition module, the SOC acquisition module and the data bus, and the data bus is also connected to the memory unit and the peripheral interface; The physical layer acquisition module acquires the physical layer data and physical layer maintenance signals of different nodes in the physical layer according to the acquisition node selection instruction and acquisition enable selection instruction given by the acquisition control module, synchronizes them to the data bus clock domain through clock domain conversion, and sends them to the data processing module; The SOC acquisition module collects the current SOC maintenance signal through the data bus while collecting the physical layer signal, and sends it to the data processing module; The data processing module performs data processing on the physical layer data, the physical layer maintenance signal and the SOC maintenance signal, including data selection processing, extraction, trigger control and trigger length control; The memory unit receives the recorded data sent by the data processing module through the data bus, reads the corresponding data according to the input address when exporting, and then sends it to the data interface through the data bus; The peripheral interface sends the recorded data exported from the memory unit or the data bus to the outside of the chip.

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