Generation method and device of training sample of graph neural network, and medium

Abstract

The embodiment of the invention provides a method and device for generating a training sample of a graph neural network and a medium. The method comprises the steps that all grammar abstract trees are constructed based on constructed verilog codes; wherein a root node of the grammar abstract tree is a signal, a leaf node is a signal or a numerical value related to the root node, and the control mode is used as an intermediate node; determining pointing and control modes among the nodes through depth-first traversal of the grammar abstract trees, and generating a first data flow diagram containing all the nodes; compiling and simulating the code to obtain a VCD waveform file, determining the value of each time point of each signal, and determining a control degree as an edge weight value based on a grammar abstract tree to update the first data flow diagram; and in the second data flow diagram, marking the signal nodes containing the Trojan horse based on the code to obtain a training sample. The data set constructed by the method comprises more comprehensive feature attributes, and the accuracy and recall rate of the trained neural network test can be obviously improved.

Description

Technical Field

[0001] The present invention relates to the field of data generation technology, and in particular to a method, device and medium for generating training samples of a graph neural network. Background Art

[0002] Hardware Trojans refer to special modules or malicious circuits implanted in integrated circuits. Such malicious circuits are usually not triggered when the hardware is running normally. Once triggered, they often implement some specific malicious functions, such as destroying the current hardware and leaking key information. However, the scale of existing integrated circuits also increases the complexity of hardware Trojan identification. Therefore, a high-precision and high-efficiency hardware Trojan detection solution has become an important technical issue.

[0003] Graph neural network (GNN) is a neural network model that learns graph structures. It uses node information transmission to capture graph dependencies. Compared with other neural networks such as convolutional neural network (CNN) and recurrent neural network (RNN), graph neural network has a natural adaptability in the field of integrated circuits for detecting hardware Trojans. Whether it is register transfer level code, gate level circuit, or transistor level netlist, it can be converted into a graph structure, which is suitable for using graph neural network to extract and learn circuit features, thereby realizing the detection of hardware Trojans.

[0004] However, the accuracy of neural network recognition depends largely on the quality of the data set. How to effectively realize the conversion process from circuit to graph? The existing hardware Trojan data set construction mainly adopts static generation method, which only generates syntax abstract tree by analyzing Verilog code, and converts the nodes and edges of the abstract tree into graph. This generation method is too simple and lacks a lot of valid data such as basic control logic and the loss of flip rate, which affects the accuracy of subsequent graph neural network for hardware Trojan detection.

[0005] In view of this, there is an urgent need to provide hardware Trojan training data with more comprehensive feature attributes in order to train graph neural networks with higher accuracy and recall. Summary of the invention

[0006] In order to overcome the problems existing in the related art, the present disclosure provides a method, device, equipment and medium for generating training samples of a graph neural network to solve the above-mentioned existing technical problems.

[0007] One or more embodiments of this specification provide a method for generating training samples of a graph neural network, including the following steps:

[0008] Based on the constructed Verilog code, extract each Verilog code, determine each signal and construct each syntax abstract tree; wherein the root node of the syntax abstract tree is the signal itself, the leaf nodes are the signals or values ​​related to the root node, and the control method is the intermediate node;

[0009] Determine the pointing and control modes between nodes by depth-first traversing each syntax abstract tree and generate a first data flow graph containing all nodes;

[0010] Compile and simulate the Verilog code to obtain a VCD waveform file, determine the value of each signal at each time point according to the VCD waveform file, and based on the syntax abstract tree corresponding to each time point, determine the number of controls between each node as the control degree, and use it as the edge weight value to update the first data flow graph to obtain the second data flow graph;

[0011] In the second data flow graph, the signal nodes containing the Trojan are marked based on the Verilog code to obtain training samples.

[0012] Furthermore, the method of determining the control mode between each node by depth-first traversal of each syntax abstract tree specifically includes:

[0013] Based on any abstract syntax tree, start from the root node i and perform depth-first traversal. When traversing to the middle node, determine its corresponding control method to the array A until traversing to the leaf node j, and use i and j as the control method matrix F i , j The coordinates (i, j) of the control method are assigned to the feature matrix F i , j superior.

[0014] Furthermore, compiling and simulating the Verilog code to obtain a VCD waveform file, determining the value of each signal at each time point according to the VCD waveform file, and determining the number of controls between each node as the control degree based on the syntax abstract tree corresponding to each time point specifically includes the following steps:

[0015] The value information of all signals recorded in the VCD waveform file at all time points is stored as a matrix D v，t , V represents the node index, t represents the time;

[0016] Based on each signal, obtain the abstract syntax tree corresponding to any time t, start from the root node and perform depth-first traversal. When the control mode corresponding to the first intermediate node is if, the COND path is traversed first. If the next node is a leaf node, then from the matrix D v，tGet the corresponding value from the matrix D. If the next node is the second intermediate node, the first intermediate node needs to be obtained according to the second intermediate node from the matrix D v，t Get the corresponding value in the calculation to obtain the new value. The first intermediate node determines whether to traverse the TRUE path or the FALSE path according to the return value or the new value. Traverse the corresponding path until the leaf node, and increase the control times corresponding to the traversed leaf node by one. If the control mode corresponding to the intermediate node of the control mode does not exist in if, traverse all paths until the leaf node, and increase the control times corresponding to the traversed leaf node by one.

[0017] Repeat the above steps until the abstract syntax tree is traversed at each moment in all signal cycles to determine the degree of control between each node.

[0018] Further, based on the constructed multiple Verilog codes, the Trojans and their trigger signals in the Verilog codes are obtained, and the output signals affected by the Trojans are stored in the corresponding signal random pool;

[0019] A Trojan trigger signal or output signal is randomly obtained from two signal random pools to replace the Trojan trigger signal or output signal in the original Verilog code to form a new Verilog code, so as to obtain more training samples to form a training set.

[0020] Furthermore, the method further includes the step of configuring a unique index for each signal for retrieval, and the indexes of the signals contained in the training samples in the training set are continuously set.

[0021] One or more embodiments of this specification provide a device for generating training samples of a graph neural network, including:

[0022] Syntax abstract tree construction module: used to extract each Verilog code based on the constructed Verilog code, determine each signal and construct each syntax abstract tree; the root node of the syntax abstract tree is the signal itself, the leaf nodes are the signals or values ​​related to the root node, and the control method is the intermediate node;

[0023] A first data flow graph generation module is used to determine the pointing and control mode between each node by depth-first traversal of each syntax abstract tree and generate a first data flow graph containing all nodes;

[0024] The second data flow graph generation module is used to compile and simulate the Verilog code to obtain a VCD waveform file, determine the value of each signal at a time point according to the VCD waveform file, and determine the number of controls between each node as the control degree based on each syntax abstract tree, and use it as the edge weight value to update the first data flow graph to obtain the second data flow graph;

[0025] Training sample generation module: used to mark the signal nodes containing Trojans in the second data flow graph based on the Verilog code to obtain training samples.

[0026] Furthermore, the first data flow graph generation module is used to determine the control mode between each node by depth-first traversal of each syntax abstract tree, specifically including:

[0027] Based on any abstract syntax tree, start from the root node i and perform depth-first traversal. When traversing to the middle node, determine its corresponding control method to the array A until traversing to the leaf node j, and use i and j as the control method matrix F i，j The coordinates (i, j) of the control mode A are assigned to the feature matrix F i，j superior.

[0028] Furthermore, the second data flow graph generating module is specifically used for:

[0029] The value information of all signals recorded in the VCD waveform file at all time points is stored as a matrix D v，t , V represents the node index, t represents the time;

[0030] Based on each signal, obtain the abstract syntax tree corresponding to any time t, start from the root node and perform depth-first traversal. When the control mode corresponding to the first intermediate node is if, the COND path is traversed first. If the next node is a leaf node, then from the matrix D v，t Get the corresponding value and return it. If the next node is the second intermediate node, the second intermediate node needs to calculate the new value according to the value fed back by the next node and the control method corresponding to the intermediate node and feed it back to the first intermediate node. The first intermediate node determines whether to traverse the TRUE path or the FALSE path according to the return value, traverses the corresponding path until the leaf node, and increases the control times corresponding to the traversed leaf node by one; if the control method corresponding to the intermediate node of the control method does not exist if, traverse all paths until the leaf node respectively, and increase the control times corresponding to the traversed leaf node by one;

[0031] Repeat the above steps until the abstract syntax tree is traversed at each moment in all signal cycles to determine the degree of control between each node.

[0032] Furthermore, it also includes a training set construction module, which is used to obtain the Trojan horse and its trigger signal in the Verilog code based on the constructed multiple Verilog codes, and store the output signal affected by the Trojan horse into the corresponding signal random pool;

[0033] A Trojan trigger signal or output signal is randomly obtained from two signal random pools to replace the Trojan trigger signal or output signal in the original Verilog code to form a new Verilog code, so as to obtain more training samples to form a training set.

[0034] One or more embodiments of the present specification provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-mentioned methods for generating training samples for a graph neural network.

[0035] The method, device and medium for generating training samples of graph neural networks provided by the present invention achieve the beneficial effect of static structure analysis and random dynamic simulation based on Verilog hardware description code, specifically, on the basis of constructing the Verilog hardware description code as a syntax abstract tree, extracting the signal control method of the data flow graph from the syntax abstract tree, and generating basic node and edge structures, and using simulation data to analyze the degree of control in the dynamic structure to form the edge weight of the data flow graph, and annotating the Trojan nodes in the data flow graph to form training data, so as to realize the automatic construction of a graph data set with hardware Trojan triggering logic nodes, edge weight features and Trojan labels. The data set constructed by this method contains more comprehensive feature attributes, which can significantly improve the accuracy and recall rate of the trained neural network test. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0037] Figure 1 A flowchart of a method for generating training samples of a graph neural network provided for one or more embodiments of this specification;

[0038] Figure 2 A diagram of the generation process architecture of training samples of a graph neural network provided for one or more embodiments of this specification;

[0039] Figure 3 A schematic diagram of a process of converting a bitCell_cntrH signal into a data flow graph provided in one or more embodiments of this specification;

[0040] Figure 4 A traversal flow diagram of the control degree between signal nodes provided by one or more embodiments of this specification;

[0041] Figure 5 A schematic diagram of a second data flow diagram with a degree of control provided for one or more embodiments of this specification;

[0042] Figure 6 A block diagram of a device for generating training samples of a graph neural network provided in one or more embodiments of this specification;

[0043] Figure 7 A schematic diagram of the structure of a computer provided for one or more embodiments of this specification. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the protection scope of the present invention.

[0045] The present invention is described in detail below in conjunction with specific implementation methods and the accompanying drawings.

[0046] Method Embodiment

[0047] According to an embodiment of the present invention, a method for generating training samples of a graph neural network is provided, such as Figure 1-2 As shown, Figure 1 A flow chart of a method for generating training samples of a graph neural network provided in this embodiment, Figure 2 The generation process architecture diagram of the training samples of the graph neural network provided in this embodiment, the generation method of the training samples of the graph neural network according to the embodiment of the present invention includes:

[0048] Step 101: Based on the constructed Verilog code, extract each Verilog code, determine each signal and construct each syntax abstract tree; wherein the root node of the syntax abstract tree is the signal itself, the leaf nodes are the signals or values ​​related to the root node, and the control method is the intermediate node.

[0049] In this embodiment, the Verilog code is a register transfer level code. The Verilog code is subjected to static syntax analysis to extract each Verilog code, determine each signal and construct each syntax abstract tree. Specifically, if the open source tool Pverilog is used to perform syntax analysis at the Verilog register transfer level, a syntax abstract tree can be generated for each signal in the code, and each signal serves as the root node of the corresponding syntax abstract tree. The leaf nodes represent signals or values ​​related to the root node, and the middle nodes are control methods.

[0050] In this embodiment, the abstract syntax tree can be divided into a root node, an intermediate node, and a leaf node. In this embodiment, the root node represents a controlled signal, the leaf node represents a control signal or a value, and the intermediate node represents a control mode. There are m control modes, such as AND, NAND, OR, NOR, NOR, XOR, XOR, addition, subtraction, multiplication, division, modulus, less than, greater than, equal to, and not equal to. Each control mode has an index for fast positioning.

[0051] In a specific embodiment, reference Figure 3 ,like Figure 3 .(1) is the register transfer level code of the bitCell_cntrH signal, Figure 3 .(2) is a structural diagram of converting the register transfer level code of the bitCell_cntrH signal into a syntax abstraction tree through step S101.

[0052] Step 102: Determine the pointing and control mode between nodes by depth-first traversing each syntax abstract tree and generate a first data flow graph containing all nodes.

[0053] In this embodiment, a complete data flow graph G=(V, E, F, C) is first defined, where V is a node array, V={V 1 ,V 2 ,…V n},v n Represents a signal. The Verilog code contains a total of n signals. Each signal has a unique index for retrieval, and each signal constructs a unique abstract syntax tree to represent the abstract circuit structure of the corresponding signal. is the set matrix of directed edges, where e i,j ∈E, if e i,j =1 represents that the source node i has an edge pointing to the destination node j. In this embodiment, the node i and the node j can be the same node, which means that there is an edge starting from the node and pointing to the node itself. F is the control mode matrix F i，j，k , k is the index of the control method; C is the control degree matrix C i，j , i is the source node, j is the destination node.

[0054] This step mainly builds a data flow graph including V, E and F matrices based on the built syntax abstract trees. First, initialize array A with a length equal to the control mode type and all values ​​0. Based on any abstract syntax tree, start depth-first traversal from the root node i. When traversing to the middle node, determine its corresponding control mode index k, set the kth item of array A to 1, and traverse to the leaf node j. Set i and j as the control feature matrix F. i，j The coordinates (i, j) of the control matrix F are assigned to the array A. i，j superior.

[0055] In a specific example, F theory should be a three-dimensional matrix with three dimensions i, j, and k, where i represents the source node, j is the leaf node, and k represents the control mode. In this embodiment, the k dimension is extracted and assigned to F. i,j is an array. If the array is [0,1,0], it means the control method is the second one, because the second bit of the array is 1, and k is 2. If the array is [0,0,1], it means the control method is the third one, and k is 3. The eighth row of Table 2 shows that the corresponding control method will change the corresponding position of the array to 1.

[0056] During the traversal, from the root node v of the abstract syntax tree i Starting from, the k leaf nodes obtained by depth-first traversal are Then we can establish k edges, Point to v i .like Figure 3 .(3) is traversal Figure 3 .(2) The data flow graph generated by the abstract syntax tree, in which the corresponding bitCell_cntrH signal is controlled by sys_rst_l, cntr_resetH, and bitCell_cntrH. It starts from the root node bitCell_cntrH, traverses to the three leaf nodes, adds three edges, and can add self-loops, so bitCell_cntrH has an edge pointing to bitCell_cntrH.

[0057] For each node v in Verilog i , this method can be used to obtain a data flow graph, and merging each data flow graph can obtain a complete data flow graph under a module. The specific traversal algorithm code is shown in Table 1 below.

[0058] Table 1

[0059]

[0060]

[0061] In this embodiment, the extraction of control methods is also based on the abstract syntax tree. An arbitrary abstract syntax tree is selected and a depth-first traversal is performed starting from the root node i. In the process of traversing the intermediate nodes, the control methods on the path are retained in the array A until the leaf node j is traversed. i and j are used as the feature matrix F i，j The coordinates (i, j) of the retained control mode A are assigned to the feature matrix F i，j Repeat this process until all root nodes to all leaf nodes of all abstract syntax trees are traversed once, and then the first data flow graph is obtained, wherein the algorithm code of the traversal process can be seen in Algorithm 2 of Table 2.

[0062] It is also based on the abstract syntax tree and implemented through a depth-first traversal method. In this embodiment, the control mode vectors between nodes are not one-hot codes, and node i can have multiple control modes controlling node j at the same time.

[0063] Table 2

[0064]

[0065] Step 103, compile and simulate the Verilog code to obtain a VCD (Value Change Dump) waveform file, determine the value of each signal at a time point according to the VCD waveform file, and based on each syntax abstract tree, determine the number of controls between each node as the degree of control, and use it as the edge weight value to update the first data flow graph to obtain the second data flow graph.

[0066] In this embodiment, the steps implemented in step S103 include:

[0067] Step S1031: Store the value information of all signals recorded in the VCD waveform file at all time points as a matrix D v，t , V represents the node index, t represents the time;

[0068] Step S1032: Based on each signal, obtain the abstract syntax tree corresponding to any time t, start from the root node and perform depth-first traversal. When the control mode corresponding to the first intermediate node is if, traverse the COND path first. If the next node is a leaf node, then from the matrix D v，tGet the corresponding value and return it. If the next node is the second intermediate node, the second intermediate node needs to calculate the new value according to the value fed back by the next node and the control method corresponding to the intermediate node and feed it back to the first intermediate node. The first intermediate node determines whether to traverse the TRUE path or the FALSE path according to the return value, traverses the corresponding path until the leaf node, and increases the control times corresponding to the traversed leaf node by one; if the control method corresponding to the intermediate node of the control method does not exist if, traverse all paths until the leaf node respectively, and increase the control times corresponding to the traversed leaf node by one;

[0069] Step S1033, repeat the above steps until the abstract syntax tree is traversed at each moment in all signal cycles to determine the control degree between each node.

[0070] Specifically, step 1031 first simulates the Verilog code to obtain VCD waveform data. The ICARUS Verilog tool can be used to compile and simulate the Verilog code with the Trojan horse. The random input model is used to write the testbench. After simulation, the VCD waveform file of the target circuit code is obtained. The file records the value information of all signals of the simulation circuit at all time points. For the same circuit, each signal may have different values ​​at different times. These data are organized into a matrix D v，t , V represents the node index, t represents the time, for example, D 2，100 =8 means that the value of signal 2 at time 100 is 8. v，t Used to query the value of the corresponding node during the analysis process of signal control degree analysis.

[0071] In this embodiment, in step 1031, the analysis of the control degree of each signal needs to be combined with the matrix form D v，t Perform a depth-first traversal of the abstract syntax tree corresponding to each signal at each moment. For example, assuming that this is the first round of traversal, the traversal root node is the syntax abstract tree at the first moment. If the traversal reaches a leaf node, it needs to be recorded in i k When traversing to the middle node, it is necessary to determine whether it is if. If the control mode is if, the path needs to be determined. Otherwise, all paths are traversed. If there are three paths, namely COND, TRUE, and FALSE. It is necessary to traverse the COND path first. During the traversal of COND, if a leaf node i is encountered, D is obtained from D. i，1 The value returned is D i，1Represents the value of node i at the first moment. If the next node encountered is still an intermediate node, the intermediate node needs to calculate a new value based on the value returned by the next node through its own corresponding control method and return to the previous intermediate node. Finally, the value calculated by the COND path is used to determine whether to traverse the TRUE path or the FALSE path next. In this way, k leaf nodes i can be traversed. 1 ,i 2 ,…i k , for each leaf node let (i.e. i k The control degree of node j is increased by 1), and then the value generated at the second moment of the same signal is traversed through the above steps. The above operation is continued. After traversing all the moments in a cycle, all the moments of the next signal are traversed, until all the moments of all signals are traversed. The specific traversal algorithm code is shown in Algorithm 3 in Table 3.

[0072] Table 3

[0073]

[0074] In a specific example, refer to Figure 4 As shown, the traversal flow diagram that determines the degree of control between signal nodes is shown. Figure 4 The traversal process when the leaf node sys_rst_l=1, cntr_resetH=0, bitCell_cntrH=1 is shown. The traversal starts from the root node bitCell_cntrH and reaches a Branch. The condition needs to be calculated. The traversal to the node sys_rst_l obtains the value of sys_rst_l as 1. The Unot (inverse) calculation is 0, so the False path needs to be taken. Return to Bracnch to select the False path and record sys_rst_l. Traverse from the False path to the second Branch, calculate the condition, come to the leaf node cntr_resetH to obtain the value of 0, return to Branch, and because the return value is 0, the False path is taken and cntr_resetH is recorded. Traverse to the Plus node, first traverse to the leaf node 'd1, and then traverse to the leaf node bitCell_cntrH, so you can add the edge (bitCell_cntrH, bitCell_cntrH), and add the edges (sys_rst_l, bitCell_cntrH), (cntr_resetH, bitCell_cntrH) according to the previously recorded signals.

[0075] In this embodiment, the control degree matrix C calculated by Algorithm 3 i，j is part of a complete data flow graph, such as Figure 5 , each node represents a signal, and the nodes are connected by directed edges, which represent one-way control, while the weight value on the edge represents the degree of control. The higher the value, the more times the control is applied. For example, C 1，2 =100 means that signal 1 controls signal 2 100 times.

[0076] Step 104: In the second data flow graph, the signal nodes containing the Trojan are marked based on the Verilog code to obtain training samples.

[0077] In this embodiment, this step mainly performs batch generation of hardware Trojans to meet the needs of a large number of data flow graphs in the data set. The complete data flow graph only contains one hardware Trojan. To realize the construction of the data set, different Trojans need to be generated. This embodiment obtains its trigger signal and the output signal it affects through analysis of the Trojan and stores it in the corresponding signal random pool in the form of code. Every time a new data flow graph needs to be generated, the two corresponding signal random pools will randomly take out the required Trojan trigger signal and output signal to replace the Trojan trigger signal and output signal in the original Verilog code to form a new Verilog code. For a complete data set, a data flow graph G = (V, E, F, C) is required as a feature, and a label set Y = {y 1 ,y 2 ,…y n}. n is the number of nodes, y i =1 means node i is a Trojan node, y i =0 represents that node i is a normal node. The selected Trojan trigger signal is recorded. The automatically generated Verilog code is passed through steps 101-104 to obtain a data flow graph with control information, and the recorded Trojan signal is used to annotate to obtain a label set Y.

[0078] Specifically, the complete data flow graph only contains one hardware Trojan. To build a data set, different Trojans need to be generated. Through the analysis of the Trojan, we know that the Trojan is composed of three parts of code, one is the input signal code, the second is the output signal code, and the third is the implementation logic code. Then, according to the specific structure of the circuit, the signals that can be used as Trojan input and output signals are stored as code files in the corresponding signal random pools respectively; when a new data flow graph needs to be generated, the code files of the required number of input signals or output signals will be randomly taken out from the two signal random pools to replace the input signals or output signals of the Trojan in the original Verilog code. The implementation logic of the Trojan does not change, and the new input and output signals are replaced with the new Verilog code.

[0079] In this embodiment, multiple data flow graphs are spliced ​​into a larger data flow graph as complete training data. In a data set composed of multiple such training data, each data flow graph is an unrelated subgraph in the large data set graph, and the indexes of the edges and nodes of each data flow graph are re-segmented and continuous with the previous data flow graph. For example, if the node index of the first data flow graph is from 0 to N, then the node index of the second data flow graph is from N+1 to 2N, and the node indexing method of the remaining data flow graphs is also analogous. Combining multiple data flow graphs into a large data set can facilitate parallelization to improve computing efficiency.

[0080] The method provided in this embodiment is based on the static structure analysis and random dynamic simulation of the Verilog hardware description code. Specifically, the Verilog hardware description code is constructed as a syntax abstract tree, the signal control method of the data flow graph is extracted from the syntax abstract tree, and a basic node and edge structure is generated. The control degree is analyzed in the dynamic structure using simulation data to form the edge weight of the data flow graph, and the Trojan nodes in the data flow graph are annotated to form training data, so as to automatically construct a graph data set with hardware Trojan trigger logic nodes, edge weight features and Trojan labels. The data set constructed by this method contains more comprehensive feature attributes, which can significantly improve the accuracy and recall rate of the trained neural network test.

[0081] The effectiveness and advantages of the present invention are illustrated below by means of specific cases.

[0082] This comparative case is aimed at building a dataset for hardware Trojan detection using graph neural networks. It introduces simulated dynamic data on the existing static circuit structure. Compared with datasets that do not use this method and only use static circuit structures without dynamic data, the graph it constructs has richer feature information. This method can meet the current training needs of graph neural networks. Table 1 shows the hardware Trojan test results on TrustHub, which shows that this method significantly improves the accuracy and recall rate of the test.

[0083]

[0084]

[0085] Device Embodiment

[0086] According to an embodiment of the present invention, a device for generating training samples of a graph neural network is provided, such as Figure 6 As shown, it is a block diagram of a device for generating training samples of a graph neural network provided in this embodiment. The device for generating training samples of a graph neural network according to an embodiment of the present invention includes:

[0087] The syntax abstract tree construction module 10 is used to extract each Verilog code based on the constructed Verilog code, determine each signal and construct each syntax abstract tree; wherein the root node of the syntax abstract tree is the signal itself, the leaf nodes are the signals or values ​​related to the root node, and the control mode is the intermediate node;

[0088] A first data flow graph generation module 20, used to determine the pointing and control mode between each node by depth-first traversal of each syntax abstract tree and generate a first data flow graph containing all nodes;

[0089] The second data flow graph generation module 30 is used to compile and simulate the Verilog code to obtain a VCD waveform file, determine the value of each signal at a time point according to the VCD waveform file, and determine the number of controls between each node as the control degree based on each syntax abstract tree, and use it as the edge weight value to update the first data flow graph to obtain the second data flow graph;

[0090] The training sample generating module 40 is used to mark the signal nodes containing the Trojans in the second data flow graph based on the Verilog code to obtain training samples.

[0091] In this embodiment, the first data flow graph generation module 20 is used to determine the control mode between each node by depth-first traversal of each syntax abstract tree, specifically including:

[0092] Based on any abstract syntax tree, start from the root node i and perform depth-first traversal. When traversing to the middle node, determine its corresponding control method to the array A until traversing to the leaf node j, and use i and j as the control method matrix F i，j The coordinates (i, j) of the control mode A are assigned to the feature matrix F i，j superior.

[0093] In this embodiment, the second data flow graph generating module 30 is specifically used for:

[0094] Step S1031: Store the value information of all signals recorded in the VCD waveform file at all time points as a matrix D v，t , V represents the node index, t represents the time;

[0095] Step S1032: Based on each signal, obtain the abstract syntax tree corresponding to any time t, start from the root node and perform depth-first traversal. When the control mode corresponding to the first intermediate node is if, traverse the COND path first. If the next node is a leaf node, then from the matrix D v，tGet the corresponding value and return it. If the next node is the second intermediate node, the second intermediate node needs to calculate the new value according to the value fed back by the next node and the control method corresponding to the intermediate node and feed it back to the first intermediate node. The first intermediate node determines whether to traverse the TRUE path or the FALSE path according to the return value, traverses the corresponding path until the leaf node, and increases the control times corresponding to the traversed leaf node by one; if the control method corresponding to the intermediate node of the control method does not exist if, traverse all paths until the leaf node respectively, and increase the control times corresponding to the traversed leaf node by one;

[0096] Step S1033, repeat the above steps until the abstract syntax tree is traversed at each moment in all signal cycles to determine the control degree between each node.

[0097] In this embodiment, the training set construction module 40 is used to obtain the Trojan horse and its trigger signal in the Verilog code based on the constructed multiple Verilog codes, and the output signal storage signal random pool affected by the Trojan horse;

[0098] Randomly obtain any Trojan trigger signal and an output signal from the signal random pool to form a new Verilog code containing the Trojan signal, so as to obtain more training samples to form a training set.

[0099] The device provided in this embodiment is based on the static structure analysis and random dynamic simulation of the Verilog hardware description code. Specifically, the syntax abstract tree construction module 10 constructs the Verilog hardware description code into a syntax abstract tree. The first data flow graph generation module 20 extracts the signal control method of the data flow graph from the syntax abstract tree, and generates a basic node and edge structure. The first data flow graph generation module 20 uses the simulation data to analyze the control degree in the dynamic structure, constructs the edge weight of the data flow graph, and annotates the Trojan nodes in the data flow graph to form training data, so as to automatically construct a graph data set with hardware Trojan trigger logic nodes, edge weight features and Trojan labels. The data set constructed by this method contains more comprehensive feature attributes, which can significantly improve the accuracy and recall rate of the trained neural network test.

[0100] The embodiment of the present invention is an apparatus embodiment corresponding to the above-mentioned method embodiment. The specific operations of the processing steps of each module can be understood by referring to the description of the method embodiment, which will not be repeated here.

[0101] like Figure 7As shown, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method for generating training samples of the graph neural network in the above-mentioned embodiment, or, when executed by a processor, implements the method for generating training samples of the graph neural network in the above-mentioned embodiment, and the computer program, when executed by the processor, implements the above-mentioned method.

[0102] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0103] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and the contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A method for generating training samples of a graph neural network, characterized in that: The following steps are involved: Based on the constructed Verilog code, extract each Verilog code, determine each signal and construct each syntax abstract tree; wherein the root node of the syntax abstract tree is the signal itself, the leaf nodes are the signals or values ​​related to the root node, and the control method is the intermediate node; Determine the pointing and control modes between nodes by depth-first traversing each syntax abstract tree and generate a first data flow graph containing all nodes; Compile and simulate the Verilog code to obtain a VCD waveform file, determine the value of each signal at each time point according to the VCD waveform file, and based on the syntax abstract tree corresponding to each time point, determine the number of controls between each node as the control degree, and use it as the edge weight value to update the first data flow graph to obtain the second data flow graph; In the second data flow graph, the signal nodes containing the Trojan are marked based on the Verilog code to obtain training samples.

2. The method for generating training samples of a graph neural network according to claim 1, characterized in that: The method of determining the control mode between nodes by depth-first traversal of each syntax abstract tree specifically includes: Based on any abstract syntax tree, start from the root node i and perform depth-first traversal. When traversing to the middle node, determine its corresponding control method to the array A until traversing to the leaf node j, and use i and j as the control method matrix F i , j The coordinates (i, j) of the control method are assigned to the feature matrix F i , j superior.

3. The method for generating training samples of a graph neural network according to claim 1, characterized in that: The method of compiling and simulating the Verilog code to obtain a VCD waveform file, determining the value of each signal at each time point according to the VCD waveform file, and determining the number of controls between each node as the control degree based on the syntax abstract tree corresponding to each time point specifically includes the following steps: The value information of all signals recorded in the VCD waveform file at all time points is stored as a matrix D v，t , V represents the node index, t represents the time; Based on each signal, obtain the abstract syntax tree corresponding to any time t, start from the root node and perform depth-first traversal. When the control mode corresponding to the first intermediate node is if, the COND path is traversed first. If the next node is a leaf node, then from the matrix D v，t Get the corresponding value from the matrix D. If the next node is the second intermediate node, the first intermediate node needs to be obtained according to the second intermediate node from the matrix D v，t Get the corresponding value in the calculation to obtain the new value. The first intermediate node determines whether to traverse the TRUE path or the FALSE path according to the return value or the new value. Traverse the corresponding path until the leaf node, and increase the control times corresponding to the traversed leaf node by one. If the control mode corresponding to the intermediate node of the control mode does not exist in if, traverse all paths until the leaf node, and increase the control times corresponding to the traversed leaf node by one. Repeat the above steps until the abstract syntax tree is traversed at each moment in all signal cycles to determine the degree of control between each node.

4. The method for generating training samples of a graph neural network according to claim 1, characterized in that: Also includes the steps: Based on the constructed multiple Verilog codes, the Trojans and their trigger signals in the Verilog codes are obtained, and the output signals affected by the Trojans are stored in the corresponding signal random pool; A Trojan trigger signal or output signal is randomly obtained from two signal random pools to replace the Trojan trigger signal or output signal in the original Verilog code to form a new Verilog code, so as to obtain more training samples to form a training set.

5. The method for generating training samples of a graph neural network according to claim 1, characterized in that: Also includes the steps: A unique index is configured for each signal for retrieval, and the indexes of the signals contained in the training samples in the training set are set continuously.

6. A device for generating training samples of a graph neural network, characterized in that: include: Syntax abstract tree construction module: used to extract each Verilog code based on the constructed Verilog code, determine each signal and construct each syntax abstract tree; the root node of the syntax abstract tree is the signal itself, the leaf nodes are the signals or values ​​related to the root node, and the control method is the intermediate node; A first data flow graph generation module is used to determine the pointing and control mode between each node by depth-first traversal of each syntax abstract tree and generate a first data flow graph containing all nodes; The second data flow graph generation module is used to compile and simulate the Verilog code to obtain a VCD waveform file, determine the value of each signal at a time point according to the VCD waveform file, and determine the number of controls between each node as the control degree based on each syntax abstract tree, and use it as the edge weight value to update the first data flow graph to obtain the second data flow graph; Training sample generation module: used to mark the signal nodes containing Trojans in the second data flow graph based on the Verilog code to obtain training samples.

7. The apparatus for generating training samples of a graph neural network according to claim 6, characterized in that: The first data flow graph generation module is used to determine the control mode between each node by depth-first traversal of each syntax abstract tree, specifically including: Based on any abstract syntax tree, start from the root node i and perform depth-first traversal. When traversing to the middle node, determine its corresponding control method to the array A until traversing to the leaf node j, and use i and j as the control method matrix F i，j The coordinates (i, j) of the control mode A are assigned to the feature matrix F i，j superior.

8. The apparatus for generating training samples of a graph neural network according to claim 6, characterized in that: The second data flow graph generating module is specifically used for: The value information of all signals recorded in the VCD waveform file at all time points is stored as a matrix D v，t , V represents the node index, t represents the time; Based on each signal, obtain the abstract syntax tree corresponding to any time t, start from the root node and perform depth-first traversal. When the control mode corresponding to the first intermediate node is if, the COND path is traversed first. If the next node is a leaf node, then from the matrix D v，t Get the corresponding value and return it. If the next node is the second intermediate node, the second intermediate node needs to calculate the new value according to the value fed back by the next node and the control method corresponding to the intermediate node and feed it back to the first intermediate node. The first intermediate node determines whether to traverse the TRUE path or the FALSE path according to the return value, traverses the corresponding path until the leaf node, and increases the control times corresponding to the traversed leaf node by one; if the control method corresponding to the intermediate node of the control method does not exist if, traverse all paths until the leaf node respectively, and increase the control times corresponding to the traversed leaf node by one; Repeat the above steps until the abstract syntax tree is traversed at each moment in all signal cycles to determine the degree of control between each node.

9. The apparatus for generating training samples of a graph neural network according to claim 6, characterized in that: It also includes a training set construction module, which is used for obtaining the Trojan horse and its trigger signal in the Verilog code based on the constructed multiple Verilog codes, and storing the output signal affected by the Trojan horse into the corresponding signal random pool; A Trojan trigger signal or output signal is randomly obtained from two signal random pools to replace the Trojan trigger signal or output signal in the original Verilog code to form a new Verilog code, so as to obtain more training samples to form a training set.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method for generating training samples of the graph neural network as described in any one of claims 1 to 5 are implemented.

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