Display device, driving method thereof and display system

Abstract

The invention provides a display device, a driving method thereof and a display system, the display device comprises a display panel and a time schedule controller electrically connected to the display panel, the time schedule controller is used for acquiring a display control signal, judging whether the display control signal is abnormal or not, and outputting a feedback signal when the display control signal is abnormal, and the time for polling the plurality of display devices is shortened.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device and a driving method thereof, and a display system. Background Art

[0002] With the development of the display industry, display devices can be seen everywhere in scenarios such as rail transit, such as dynamic map display screens, carriage advertising screens, high-speed rail seat screens, etc.

[0003] However, due to the large number of display devices in scenarios such as rail transit, it is currently time-consuming for personnel to inspect each display device one by one to confirm whether the display system is abnormal and determine whether it needs to be repaired. Summary of the invention

[0004] The object of the present invention is to provide a display device and a driving method thereof, and a display system, so as to improve the problem that it takes a long time to inspect display devices arranged at multiple different positions in the conventional art.

[0005] The present invention provides a display device, comprising:

[0006] Display panel;

[0007] A timing controller, electrically connected to the display panel, for obtaining a display control signal;

[0008] The timing controller is used to determine whether the display control signal is abnormal, and to output a feedback signal when the display control signal is abnormal.

[0009] In some embodiments, the display control signal includes a plurality of sub-display control signals, and the feedback signal includes a plurality of sub-feedback signals corresponding to the plurality of sub-display control signals;

[0010] The timing controller is used to determine whether the plurality of sub-display control signals are abnormal, and is used to output the corresponding sub-feedback signal when the sub-display control signal is abnormal.

[0011] In some embodiments, the plurality of sub-display control signals include:

[0012] A power signal, used to supply power to the timing controller;

[0013] The image signal is used for the timing controller to control the display panel to display an image.

[0014] In some embodiments, the display device further comprises:

[0015] The system chip is electrically connected to the timing controller and is used to output the image signal and the original power signal to the timing controller, wherein the original power signal is used to supply power to the timing controller.

[0016] In some embodiments, the timing controller includes:

[0017] a first register, wherein at least part of the information stored in the first register is set as first information by the timing controller when the image signal is abnormal, and the sub-feedback signal corresponding to the image signal includes the first information;

[0018] The system chip is used to generate an image abnormality signal according to the first information.

[0019] In some embodiments, the display device further comprises:

[0020] A power manager is electrically connected to the system chip and the timing controller. The power manager is used to obtain the original power signal from the system chip and to generate a first power signal transmitted to the timing controller based on the original power signal. The power signal includes the first power signal.

[0021] In some embodiments, the display device further comprises:

[0022] A gate driver, electrically connected to the power manager and a plurality of sub-pixels in the display panel, for generating a gate signal acting on the plurality of sub-pixels according to a second power signal;

[0023] The power manager is further configured to generate a second power signal transmitted to the gate driver according to the original power signal, and the power signal includes the second power signal.

[0024] In some embodiments, the timing controller includes:

[0025] a second register, wherein at least part of the information stored in the second register is set as second information by the timing controller when the power signal is abnormal, and the sub-feedback signal corresponding to the power signal includes the second information;

[0026] The system chip is used to generate a power abnormality signal according to the second information.

[0027] In some embodiments, the timing controller includes:

[0028] A pin, the potential of which is outside a preset potential range when the power signal is abnormal;

[0029] The timing controller is used for setting at least part of the information stored in the second register as the second information when the potential of the pin is outside the preset potential range.

[0030] The present invention also provides a display system, comprising:

[0031] A plurality of display devices as described above;

[0032] The central control device is used to receive the feedback signal output by each of the display devices.

[0033] The present invention also provides a method for driving a display device, comprising:

[0034] The timing controller obtains a display control signal;

[0035] The timing controller determines whether the display control signal is abnormal, and outputs a feedback signal when the display control signal is abnormal.

[0036] The present invention provides a display device and a driving method thereof, and a display system. The display device includes a display panel and a timing controller. The timing controller is electrically connected to the display panel and is used to obtain a display control signal. The timing controller is configured to determine whether the display control signal is abnormal and to output a feedback signal when the display control signal is abnormal. This shortens the time required for inspecting multiple display devices, avoids manual inspection, and reduces labor costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a diagram of the architecture of a display device provided by an embodiment of the present invention.

[0038] Figure 2 A block diagram of a timing controller provided by an embodiment of the present invention.

[0039] Figure 3 A block diagram of a display system provided by an embodiment of the present invention.

[0040] Figure 4 The present invention provides a flow chart of a method for driving a display device according to an embodiment of the present invention.

[0041] Figure 5 and Figure 6 The present invention provides a flowchart of a method for driving a display system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0043] In the description of the present invention, the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the said features. In addition, it should be noted that the drawings only provide structures that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the invention clear at a glance, rather than to indicate that the actual device is the same as the attached structure. Figure 1 The same is not a limitation of the actual device.

[0044] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] The present invention provides a display device, which may include but is not limited to the following embodiments and combinations of the following embodiments.

[0046] In some embodiments, Figure 1 As shown, the display device 100 includes: a display panel 10; a timing controller 20, electrically connected to the display panel 10, for obtaining a display control signal; wherein the timing controller 20 is used to determine whether the display control signal is abnormal, and to output a feedback signal when the display control signal is abnormal.

[0047] The display panel 10 may be, but is not limited to, an organic self-luminous display panel, an inorganic self-luminous direct display panel, or a liquid crystal display panel. The display device 100 may further include a gate driver 50 and a source driver 30. The gate driver 50 may be a gate drive circuit located on a substrate of the display panel 10 or a chip independently provided from the display panel 10. Figure 1 The source driver 30 is a chip independently provided from the display panel 10 .

[0048] Specifically, the display panel 10 may further include a plurality of gate lines electrically connected to the gate driver 50 and a plurality of data lines electrically connected to the source driver 30. The gate driver 50 generates a plurality of gate signals corresponding to the plurality of rows of sub-pixels, each gate line is electrically connected to a corresponding row of sub-pixels to transmit the corresponding gate signal to the corresponding row of sub-pixels, each gate signal includes a gate effective pulse for controlling the corresponding row of sub-pixels to be turned on, and the plurality of gate effective pulses are arranged sequentially on the time axis so that the corresponding plurality of rows of sub-pixels are turned on sequentially; each data line is electrically connected to a corresponding column of sub-pixels to transmit a corresponding data signal generated by the source driver 30 thereto, each data signal includes a plurality of data voltages corresponding to the plurality of sub-pixels in the column, and the plurality of data signals corresponding to the plurality of columns of sub-pixels are matched so that when each row of sub-pixels is turned on, the plurality of data voltages corresponding to the plurality of sub-pixels in the row can be outputted through the plurality of data lines respectively.

[0049] The display control signal can be understood as being used to generate at least one of the above-mentioned gate signal and data signal. Therefore, when the display control signal is abnormal, at least one of the gate signal and data signal generated therefrom is also abnormal. If the abnormal display control signal is not interfered with, the display screen will eventually be abnormal, or the timing controller 20 will control the display panel 10 to display a fixed screen. However, if the abnormal information of the display control signal is not fed back, it will take a long time to find the problem through manual inspection.

[0050] It can be understood that in this embodiment, the timing controller 20 is configured to determine whether the display control signal is abnormal, and output a feedback signal when the display control signal is abnormal, so as to facilitate the transmission of the abnormality of the display control signal in the display device 100 to the front end, thereby shortening the detection time of the display control signal, avoiding manual detection, and reducing labor costs.

[0051] Of course, when the display control signal is normal, the timing controller 20 does not output a feedback signal, but is used to generate a signal acting on the gate driver 50 and the source driver 30 according to the display control signal, thereby realizing that the gate driver 50 generates a gate signal and the source driver 30 generates at least one of a data signal, thereby controlling the display panel 10 to display an image.

[0052] Furthermore, the display control signal includes multiple sub-display control signals, and the feedback signal includes multiple sub-feedback signals corresponding to the multiple sub-display control signals; wherein the timing controller 20 is used to determine whether the multiple sub-display control signals are abnormal, and to output the corresponding sub-feedback signals when the sub-display control signals are abnormal.

[0053] That is, in this embodiment, the display control signal is further refined to include multiple sub-display control signals, and the timing controller 20 can be used to detect each sub-display control signal to determine whether each one is abnormal. Since the multiple sub-display control signals are different, when each one is abnormal, the timing controller 20 needs to output its corresponding sub-feedback signal, and the sub-feedback signal needs to characterize the type of the sub-display control signal and whether it is abnormal.

[0054] Specifically, the plurality of sub-display control signals include: a power signal Vp, which is used to supply power to the timing controller 20; and an image signal Vt, which is used for the timing controller 20 to control the display panel 10 to display an image, that is, the timing controller 20 is used to control the display panel 10 to display an image according to the image signal Vt. Among them, since the power signal Vp is used to supply power to the timing controller 20, the image signal Vt is used to control the display panel 10 to display an image. Therefore, when the power signal Vp is abnormal, the timing controller 20 will not be able to generate a correct signal to act on the gate driver 50 and the source driver 30, causing the gate signal and the data signal output by the gate driver 50 and the source driver 30 to be abnormal; when the image signal Vt is abnormal, the timing controller 20 will not be able to generate a correct signal to act on the source driver 30, causing the data signal output by the source driver 30 to be abnormal.

[0055] It can be understood that the timing controller 20 in this embodiment can output a corresponding sub-feedback signal when an abnormality in the power supply signal Vp is detected, and output a corresponding sub-feedback signal when an abnormality in the image signal Vt is detected, so that the abnormalities of both signals can be detected, thereby avoiding the generation of abnormal gate signals and data signals, and improving the reliability of abnormal detection of the display device 100.

[0056] In some embodiments, Figure 1 As shown, the display device 100 further includes: a system chip 40 (which may represent the front end of the timing controller 20), which is electrically connected to the timing controller 20 and is used to output the image signal Vt and the original power signal Vo to the timing controller 20, and the original power signal Vo is used to supply power to the timing controller 20. The system chip 40 may be, but is not limited to, a SOC (System on Chip). The image signal Vt may be transmitted via a LVDS (Low Voltage Differential Signaling) or a VBO (V-by-One) signal.

[0057] Specifically, LVDS does not require encoding, and the VBO signal uses 8B or 10B encoding, which is better compatible with other high-speed serials. Converting 8Bit data to 10Bit data can effectively solve DC balance. To process 1080P 30-bit color and 240Hz refresh rate signals, LVDS requires 48 pairs of signal lines, while VB0 only requires 8 pairs of signal lines, effectively reducing the cost of wires. LVDS DC coupling provides a direct connection path for the signal, so all components of the signal (including AC and DC) will be transmitted to the receiving end, and VBO uses AC coupling. AC coupling connects a capacitor in series between the signal sending end and the receiving end, so that the DC component of the signal is isolated, and the cut-off frequency depends on the size of the coupling capacitor. The low-frequency AC component of the signal will also be blocked and greatly attenuated, but the high-frequency AC component can still pass well, so high-speed serial signals generally use AC coupling.

[0058] Specifically, the timing controller 20 needs to use the original power signal Vo as the working voltage, and generates a control signal acting on the gate driver 50 and the source driver 30 according to the image signal Vt and the power signal Vp, and generates an image data signal acting on the source driver 30, and then the gate driver 50 generates a gate signal, and the source driver 30 generates a data signal, thereby driving the display panel 10 to display the picture.

[0059] In some embodiments, Figure 1 As shown, the display device 100 also includes: a power manager 60, which is electrically connected to the system chip 40 and the timing controller 20, and the power manager 60 is used to obtain the original power signal Vo from the system chip 40, and is also used to generate a first power signal Vp1 transmitted to the timing controller 20 according to the original power signal Vo, and the power signal Vp includes the first power signal Vp1.

[0060] The power manager 60 and the timing controller 20 may be integrated on the first circuit board 11, the system chip 40 and the circuit board 11 may be electrically connected via a first chip-on-chip film 12, the second circuit board 15 for carrying the source driver 30 and the first circuit board 11 may be electrically connected via a second chip-on-chip film 13, and the source driver 30 and the display panel 10 may be electrically connected via a third chip-on-chip film 14.

[0061] In combination with the above discussion, it can be seen that both the timing controller 20 and the power manager 60 need to obtain the original power signal Vo, and the power manager 60 needs to convert the original power signal Vo to generate multiple power signals Vp. The operating voltage of the timing controller 20 is the original power signal Vo, but it needs to generate signals for controlling the gate driver 50 and the source driver 30 based on the first power signal Vp1 and the image signal Vt.

[0062] Specifically, after the original power signal Vo supplies power to the timing controller 20, the timing controller 20 can generate an image data signal RSDS, a frame start signal STV, a frame clock signal CKV, a line start signal STH, and a line clock signal CKH based on the first power signal Vp1 and the image signal Vt. Among them, the color signal in the image signal Vt is used to generate the image data signal RSDS and output it to the source driver 30; the line and field synchronization signals in the image signal Vt are used to generate the line start signal STH and the line clock signal CKH and output them to the source driver 30 to convert the serial image data signal RSDS into a row of parallel pixel data signals, and at least after the gamma correction voltage is assigned, it is loaded as the above-mentioned data signal to the display panel 10; the line and field synchronization signals in the image signal Vt are also used to generate the frame start signal STV and the frame clock signal CKV and output them to the gate driver 50 so that it generates a plurality of gate effective pulses shifted from top to bottom row by row to act on the display panel 10, so as to display the pixel signals sent by the source driver 30 row by row.

[0063] Furthermore, the operation of each of the gate driver 50 and the source driver 30 also requires a power signal Vp. For example, the source driver 30 also needs to generate a data signal based on the above-mentioned first power signal Vp1. For example, the gate driver 50 can generate a gate signal based on the "second power signal Vp2 generated by the power manager 60 according to the original power signal Vo".

[0064] In some embodiments, Figure 2 As shown in Table 1, the timing controller 20 includes: a first register 201, at least part of the information stored in the first register 201 is set as the first information by the timing controller 20 when the image signal Vt is abnormal, and the sub-feedback signal corresponding to the image signal Vt includes the first information; wherein the system chip 40 is used to generate an image abnormality signal according to the first information.

[0065] Table 1

[0066]

[0067] It can be understood that the timing controller 20 of this embodiment sets the information stored in the first register 201 therein to include the first information when the image signal Vt is abnormal. When the system chip 40 reads that the information stored in the first register 201 includes the first information, it can output an image abnormality signal to characterize that the type of the sub-display control signal is the image signal Vt, and then transmit to the front end that the type of the abnormal sub-display control signal of the display device 100 is the image signal Vt.

[0068] Among them, the communication related to the above-mentioned feedback signal can be carried out through but not limited to the I2 C interface in the interface of the timing controller 20. The I2 C interface can be used for the communication of three signals: the read-write signal WP, the clock signal SCL, and the data signal SDA. When the read-write signal WP is at a corresponding high potential, the timing controller 20 and the system chip 40 can communicate, and when it is at a corresponding low potential, the timing controller 20 and the system chip 40 cannot communicate.

[0069] Specifically, as shown in Table 1, the communication related to the above feedback signal may include the following steps:

[0070] (1) The system chip 40 controls the read / write signal WP to a corresponding high level so that the timing controller 20 and the system chip 40 can communicate;

[0071] (2) The system chip 40 sends an addressing signal (e.g., 5-byte data “A8 C0 00 91F4”) to perform corresponding register addressing in the timing controller 20 (e.g., find the first register 201 through the address of the first register 201);

[0072] (3) The timing controller 20 sends the information stored in the corresponding register to the system chip 40 (for example, sends at least part of the information stored in the first register 201);

[0073] (4) The system chip 40 determines whether the corresponding sub-display control signal is abnormal based on the information stored in the register (for example, when the information stored in the first register 201 includes the first information, the image signal is determined to be abnormal).

[0074] It should be noted that the example of the transmission of 5 bytes of data between the timing controller 20 and the system chip 40 is used here, but it is not limited to this. Here, the first byte of the 5 bytes of data is "A8" to indicate that the data is written by the system chip 40 to the timing controller 20, and "A9" to indicate that the data is read from the timing controller 20 by the system chip 40, but it is not limited to this. Here, the example of the system chip 40 reading 4 bytes of data stored in the register and the last byte is valid data is used, but it is not limited to this.

[0075] For example, in the above step (2), the first byte of "A8 C0 00 91F4" is "A8", indicating that the system chip 40 writes the data to the timing controller 20 (here, addressing); in the above step (3), the data sent by the timing controller 20 to the system chip 40 may include "A9 00 00 02 21" or "A979 00 02 0A" as the corresponding sub-feedback signal, and the first byte of both is "A9", indicating that the system chip 40 reads from the timing controller 20 (here, reading at least part of the information stored in the first register 201). The former can be considered not to be the first information because the last byte is not "0A", and the latter can be considered to be the first information because the last byte is "0A".

[0076] Through the above steps (1) to (4), the system chip 40 can send a corresponding abnormal signal to the front end when the sub-display control signal is abnormal (for example, when the information stored in the first register 201 includes the first information, an image abnormality signal is sent to the front end), and does not communicate with the front end when it is normal.

[0077] Among them, Figure 1 As shown, the main control pin master of the timing controller 20 communicates with the power manager 60, the main control pin master can be used to transmit the clock signal and manage the selection of the slave control pin Slave, the slave control pin Slave of the timing controller 20 communicates with the system chip 40, and the FLT pin of the timing controller 20 (i.e., the second pin 002 below) communicates with the power manager 60.

[0078] In some embodiments, Figure 2 As shown in Table 1, the timing controller 20 includes: a second register 202, at least part of the information stored in the second register 202 is set as second information by the timing controller 20 when the power signal Vp is abnormal, and the sub-feedback signal corresponding to the power signal Vp includes the second information; wherein the system chip 40 is used to generate a power abnormality signal according to the second information.

[0079] Similarly, when the power signal Vp is abnormal, the timing controller 20 of the present embodiment sets the information stored in the second register 202 therein to include the second information. When the system chip 40 reads that the information stored in the second register 202 includes the second information, it can output a power abnormality signal to characterize that the type of the sub-display control signal is the power signal Vp, and then transmit to the front end that the type of the abnormal sub-display control signal of the display device 100 is the power signal Vp.

[0080] As shown in Table 1, the communication related to the feedback signal may also include the steps (1) to (4). The step (2) is that the system chip 40 sends the addressing signal of the second register 202, for example, 5 bytes of data "A8C0 00 9B 90". The step (3) is that the timing controller 20 sends at least part of the information stored in the second register 202 to the system chip 40, for example, outputting 5 bytes of data "A9 00 00 00 55" or "A9 00 00 00AA". The step (4) is that the system chip 40 determines whether the power signal Vp is abnormal based on whether the information stored in the second register 202 includes the second information. For example, the last byte of "A9 00 00 00 55" is not "AA", so it can be considered that it is not the second information. Since the last byte of "A9 00 00 00AA" is "AA", it can be considered that it is the second information.

[0081] Similarly, through the above steps (1) to (4), the system chip 40 can send a corresponding abnormal signal to the front end when the sub-display control signal is abnormal (for example, when the information stored in the second register 202 includes the second information, a power abnormality signal is sent to the front end), and does not communicate with the front end when it is normal.

[0082] Furthermore, since the power signal Vp includes the first power signal Vp1 and the second power signal Vp2, the second information may also include the first sub-information corresponding to the abnormality of the first power signal Vp1 and the second sub-information corresponding to the abnormality of the second power signal Vp2. That is, the information stored in the second register 202 is set to include the first sub-information when the first power signal Vp1 is abnormal, and is set to include the second sub-information when the second power signal Vp2 is abnormal. Table 1 only illustrates the first sub-information. For example, when the last byte of the second information is "A0", the second information can be considered to be the second sub-information. At this time, only when the last byte of the 4 bytes of the information stored in the second register 202 read by the system chip 40 is not "AA" or "A0", it indicates that the power signal Vp is normal.

[0083] Furthermore, the second information may also include third sub-information indicating that both the first power signal Vp1 and the second power signal Vp2 are abnormal. For example, when the last byte of the second information is "A1", the second information may be considered as the third sub-information.

[0084] Correspondingly, the power supply abnormality signal may also include a first sub-power supply abnormality signal corresponding to the first sub-information, a second sub-power supply abnormality signal corresponding to the second sub-information, and a third sub-power supply abnormality signal corresponding to the third sub-information.

[0085] In some embodiments, in combination Figure 1 and Figure 2 As shown, the timing controller 20 includes: a pin, the potential of which is outside the preset potential range when the power signal Vp is abnormal; wherein the timing controller 20 is used to set at least part of the information stored in the second register 202 to the second information when the potential of the pin is outside the preset potential range. That is, the pin can load a judgment signal or be used to output a judgment signal, and the potential of the judgment signal can be outside the preset potential range when the power signal Vp is abnormal, and then the timing controller 20 can set the information stored in the second register 202 to include the second information, so that the system chip 40 can identify whether the power signal Vp is abnormal.

[0086] In combination with the above discussion, it can be known that the above pins may include a first pin 001 for indicating whether the first power signal Vp1 is abnormal, and a second pin 002 for indicating whether the second power signal Vp2 is abnormal.

[0087] Among them, the abnormality of the first power signal Vp1 is generally caused by the abnormal output of the power manager 60. A detection circuit can be set between the terminal for outputting the first power signal Vp1 in the power manager 60 and the first pin 001 of the timing controller 20. The detection circuit can control the potential of the first pin 001 to be outside the preset potential range when the first power signal Vp1 is abnormal.

[0088] Among them, the abnormality of the second power signal Vp2 is generally caused by the abnormal output of the power manager 60, the abnormality of the internal circuit of the gate driver 50, or the abnormality of the circuit connected to the gate driver 50 (the wiring connected within the plane when the gate driver 50 is an in-plane gate driving circuit). Since the abnormality at this time will cause over-temperature, over-current or over-voltage protection of the display device 100, the timing controller 20 generally integrates relevant circuits to determine whether over-temperature, over-current or over-voltage protection occurs, that is, it can determine whether the second power signal Vp2 is abnormal, and the timing controller 20 will control the potential of the second pin 002 to be outside the preset potential range when over-temperature, over-current or over-voltage protection occurs, so there is no need to set a circuit for controlling the potential of the second pin 002 outside the timing controller 20.

[0089] The present invention also provides a display system, such as Figure 3As shown, the display system 200 may include a plurality of display devices 100 as described above; a central control device 300 (which may represent the front end of a plurality of system chips 40) is used to receive the feedback signal output by each of the display devices 100. Specifically, the central control device 300 may be electrically connected to the system chip 40 of each display device 100, and if at least one corresponding sub-display control signal is abnormal, the system chip 40 may send a corresponding abnormal signal and an address signal (indicating the corresponding display device 100) to the central control device 300.

[0090] It can be understood that the central control device 300 in the present invention can quickly locate the abnormal display device 100 and the type of its abnormal sub-display control signal based on at least one abnormal signal and the corresponding address signal it receives, thereby reducing the time for detecting multiple display control signals in the display system 200, avoiding manual inspections, and reducing labor costs.

[0091] The present invention also provides a method for driving a display device, such as Figure 4 As shown, including but not limited to the following steps:

[0092] S1, the timing controller obtains a display control signal.

[0093] Among them, the timing controller 20 can obtain a display control signal from the system chip 40, and the display control signal is used for the timing controller 20 to work, and the timing controller 20 is used to generate a signal acting on the source driver 30 and the gate driver 50, so that the source driver 30 generates a data signal, and the gate driver 50 generates a gate signal, thereby driving the display panel 10 to display an image.

[0094] S2, the timing controller determines whether the display control signal is abnormal, and outputs a feedback signal when the display control signal is abnormal.

[0095] It can be understood that in this embodiment, the timing controller 20 is configured to determine whether the display control signal is abnormal, and a feedback signal is output when the display control signal is abnormal, thereby preventing the abnormal display control signal from acting on the timing controller 202 and causing at least one of the gate signal and the data signal to be abnormal. In addition, the feedback signal is transmitted to the front end so that the front end can understand that the display control signal in the display device 100 is abnormal, thereby shortening the detection time of the display control signal, avoiding manual detection, and reducing labor costs.

[0096] In combination with the above discussion on the display device 100 and the display system 200 , the present invention may further provide a method for driving the display system.

[0097] For the image signal Vt, Figure 5As shown, it may include but is not limited to the following steps and combinations of the following steps:

[0098] S101, the timing controller determines whether the image signal is abnormal when the original power signal is normal.

[0099] Combined with the above discussion, it can be seen that since the timing controller 20 needs to use the original power signal Vo as the working voltage, it is necessary to determine whether the image signal Vt is abnormal only when the original power signal Vo is on. Otherwise, the timing controller 20 cannot work and cannot generate a corresponding signal regardless of whether the image signal Vt is normal.

[0100] If abnormal, execute:

[0101] S102: The timing controller sends first information to the system chip.

[0102] As can be seen from the above discussion, the information stored in the first register is set by the timing controller 20 to include the first information when the image signal Vt is abnormal, so the sub-feedback information sent by the timing controller 20 to the system chip 40 includes the first information.

[0103] S103, the system chip sends an image abnormality signal to the central control device.

[0104] As can be seen from the above discussion, when the system chip 40 recognizes the first information, it can output an image abnormality signal to the central control device 300 to indicate that the abnormal sub-display control signal is an image signal Vt.

[0105] If abnormal, end.

[0106] For the power signal Vp, if Figure 6 As shown, it may include but is not limited to the following steps and combinations of the following steps:

[0107] S201, the timing controller determines whether the power supply signal is abnormal according to the potential of the pin.

[0108] Combined with the above discussion, it can be seen that since the potential of at least one of the first pin 001 and the second pin 002 of the timing controller 20 will be outside the preset potential range when the power signal Vp is determined to be abnormal, the timing controller can determine whether the power signal Vp is abnormal based on the potential of the pin.

[0109] If abnormal, execute:

[0110] S202, the timing controller determines whether the power supply signal is abnormal according to the potential of the pin.

[0111] In combination with the above discussion, it can be seen that the information stored in the second register is set by the timing controller 20 to include the second information (the first sub-information, the second sub-information or the third sub-information) when the power signal Vp is abnormal, that is, the timing controller 20 can send the corresponding sub-information to the system chip 40 as sub-feedback information according to the specific situation of the power signal Vp abnormality.

[0112] S203, the system chip sends a power abnormality signal to the central control device.

[0113] In combination with the above discussion, it can be seen that when the system chip 40 recognizes the second information (any sub-information in it), it can output an image abnormality signal (the corresponding sub-image abnormality signal in it) to the central control device 300 to indicate which power signal of the power signal Vp is the abnormal sub-display control signal.

[0114] If abnormal, end.

[0115] The display device and its driving method, as well as the display system provided by the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that: include: Display panel; A timing controller, electrically connected to the display panel, for obtaining a display control signal; The timing controller is used to determine whether the display control signal is abnormal, and to output a feedback signal when the display control signal is abnormal.

2. The display device according to claim 1, wherein: The display control signal includes a plurality of sub-display control signals, and the feedback signal includes a plurality of sub-feedback signals corresponding to the plurality of sub-display control signals; The timing controller is used to determine whether the plurality of sub-display control signals are abnormal, and is used to output the corresponding sub-feedback signal when the sub-display control signal is abnormal.

3. The display device according to claim 2, wherein: The plurality of sub-display control signals include: A power signal, used to supply power to the timing controller; The image signal is used for the timing controller to control the display panel to display an image.

4. The display device according to claim 3, characterized in that Also includes: The system chip is electrically connected to the timing controller and is used to output the image signal and the original power signal to the timing controller, wherein the original power signal is used to supply power to the timing controller.

5. The display device according to claim 4, characterized in that The timing controller comprises: a first register, wherein at least part of the information stored in the first register is set as first information by the timing controller when the image signal is abnormal, and the sub-feedback signal corresponding to the image signal includes the first information; The system chip is used to generate an image abnormality signal according to the first information.

6. The display device according to claim 4, characterized in that Also includes: A power manager is electrically connected to the system chip and the timing controller. The power manager is used to obtain the original power signal from the system chip and to generate a first power signal transmitted to the timing controller based on the original power signal. The power signal includes the first power signal.

7. The display device according to claim 6, characterized in that Also includes: A gate driver, electrically connected to the power manager and a plurality of sub-pixels in the display panel, for generating a gate signal acting on the plurality of sub-pixels according to a second power signal; The power manager is further configured to generate a second power signal transmitted to the gate driver according to the original power signal, and the power signal includes the second power signal.

8. The display device according to claim 6 or 7, characterized in that: The timing controller comprises: a second register, wherein at least part of the information stored in the second register is set as second information by the timing controller when the power signal is abnormal, and the sub-feedback signal corresponding to the power signal includes the second information; The system chip is used to generate a power abnormality signal according to the second information.

9. The display device according to claim 8, wherein: The timing controller comprises: A pin, the potential of which is outside a preset potential range when the power signal is abnormal; The timing controller is used for setting at least part of the information stored in the second register as the second information when the potential of the pin is outside the preset potential range.

10. A display system, characterized in that: include: A plurality of display devices according to any one of claims 1 to 9; The central control device is used to receive the feedback signal output by each of the display devices.

11. A method for driving a display device, characterized in that: include: The timing controller obtains a display control signal; The timing controller determines whether the display control signal is abnormal, and outputs a feedback signal when the display control signal is abnormal.

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