Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: providing a substrate; forming an isolation groove in the substrate; in the first reaction cavity, an isolation sub-dielectric layer is formed in the isolation groove, and the isolation sub-dielectric layer covers the isolation groove in a shape-preserving mode; after the isolation sub-dielectric layer is formed, removing a part of the isolation sub-dielectric layer at the top of the side wall of the isolation groove in the second reaction cavity; the step of forming the isolation sub dielectric layer in the isolation groove and the step of removing the part of the isolation sub dielectric layer at the top of the side wall of the isolation groove are repeatedly executed until the isolation groove is completely filled with the formed isolation sub dielectric layer, and the step of forming the isolation sub dielectric layer in the isolation groove and removing the part of the isolation sub dielectric layer at the top of the side wall of the isolation groove are repeated until the isolation groove is completely filled with the formed isolation sub dielectric layer. And taking the plurality of isolation sub dielectric layers which completely fill the isolation grooves as isolation dielectric layers. According to the semiconductor structure formed by the semiconductor structure forming method provided by the embodiment of the invention, the performance of a device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the production of wafers, the isolation trenches are generally filled with an isolation dielectric layer. The isolation dielectric layer is used to prevent electromagnetic interference and noise caused by potential differences, currents, etc. between different circuits, thereby ensuring the normal operation of the device. In addition, the isolation dielectric layer can also prevent short circuits and failures between circuits, improving the reliability and safety of the device.

[0003] However, in the prior art, the device performance of the semiconductor structure obtained after forming the isolation dielectric layer needs to be improved. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a semiconductor structure and a method for forming the same to improve device performance.

[0005] To solve the above problems, an embodiment of the present application provides a method for forming a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming an isolation trench in the substrate;

[0008] In the first reaction chamber, forming an isolator dielectric layer in the isolation trench, wherein the isolator dielectric layer conformally covers the isolation trench;

[0009] After forming the isolator dielectric layer, in the second reaction chamber, removing a portion of the isolator dielectric layer on the top of the isolation trench sidewall;

[0010] Repeat the steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer at the top of the isolation trench sidewall until the isolation trench is completely filled with the formed isolation sub-dielectric layer, wherein the multiple isolation sub-dielectric layers that completely fill the isolation trench are the isolation dielectric layer.

[0011] Optionally, the step of forming an isolation sub-dielectric layer in the isolation groove is specifically: forming the isolation sub-dielectric layer under a preset electric field, wherein the electric field power of the preset electric field is less than a first preset value, so that the ion density in the formed isolation sub-dielectric layer is less than a second preset value.

[0012] Optionally, the first preset value is 1800-2000W, and the second preset value is 1500-1700kg / m 3 .

[0013] Optionally, in the step of forming the isolation sub-dielectric layer in the isolation trench, a high density plasma process HDP is used to form the isolation sub-dielectric layer.

[0014] Optionally, the reaction gases used in the high-density plasma process HDP include O2, SiH4, SiH4-TOP, H2 and He, the flow rate of the reaction gas O2 is 70-110sccm, the flow rate of the reaction gas SiH4 is 30-60sccm, the flow rate of the reaction gas SiH4-TOP is 10-20sccm, the flow rate of the reaction gas H2 is 110-150sccm, and the flow rate of the reaction gas He is 200-400sccm.

[0015] Optionally, the thickness of the isolator dielectric layer is

[0016] Optionally, in the step of removing a portion of the isolator dielectric layer at the top of the isolation trench sidewall, a SiCoNi etching process is used to remove a portion of the isolator dielectric layer at the top of the isolation trench sidewall.

[0017] Optionally, the reaction gases used in the SiCoNi etching process include NH3 and NF3, the flow rate of the reaction gas NH3 is 120-160sccm, the flow rate of the reaction gas NF3 is 50-90sccm, the effective power is 20-60W, and the etching rate is

[0018] Optionally, the thickness of the part of the isolator dielectric layer removed from the top of the isolation trench sidewall is

[0019]

[0020] Optionally, the steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer on the top of the isolation trench sidewall are performed once as one cycle, wherein the steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer on the top of the isolation trench sidewall are repeated, specifically, for three cycles.

[0021] Optionally, after the step of repeatedly performing the steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer at the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation sub-dielectric layer, the method further includes:

[0022] Depositing a sacrificial layer, wherein the sacrificial layer completely covers the isolation dielectric layer;

[0023] The sacrificial layer and the isolation dielectric layer are planarized.

[0024] To solve the above problems, an embodiment of the present application further provides a semiconductor structure, which is formed based on the method for forming the semiconductor structure as described above.

[0025] Compared with the prior art, the technical solution of the embodiment of the present application has the following advantages:

[0026] An embodiment of the present application provides a semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming an isolation trench in the substrate; forming an isolation dielectric layer in the isolation trench in a first reaction chamber, the isolation dielectric layer conformally covering the isolation trench; after forming the isolation dielectric layer, removing a portion of the isolation dielectric layer at the top of the isolation trench sidewall in a second reaction chamber; repeating the steps of forming the isolation dielectric layer in the isolation trench and removing a portion of the isolation dielectric layer at the top of the isolation trench sidewall until the isolation trench is completely filled with the formed isolation dielectric layer, wherein the multiple isolation dielectric layers that completely fill the isolation trench are the isolation dielectric layers.

[0027] It can be seen that a method for forming a semiconductor structure provided in an embodiment of the present application deposits the insulator dielectric layer in a first reaction chamber; and etches part of the insulator dielectric layer on the top of the isolation groove side wall in a second reaction chamber, so that the etching is not affected by the electric field in the first reaction chamber, and ions entering the deposited insulator dielectric layer during etching are avoided, which affects the electrons in the insulator dielectric layer, thereby reducing the possibility of electron migration in the device, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0029] Figure 1 is a flow chart of a method for forming a semiconductor structure provided in an embodiment of the present application;

[0030] Figure 2-Figure 6 is a structural schematic diagram corresponding to the method for forming a semiconductor structure provided in an embodiment of the present application;

[0031] Figure 7 is another optional flow chart of the method for forming a semiconductor structure provided in an embodiment of the present application;

[0032] Figure 8-Figure 9It is an optional structural schematic diagram corresponding to the method for forming a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0034] As described in the background art, in the prior art, the device performance of the semiconductor structure obtained after forming the isolation dielectric layer needs to be improved.

[0035] In the existing scheme for forming a semiconductor structure, the isolation trench located in the reaction chamber generally adopts multiple deposition-etching cycles to achieve complete filling. In the deposition process, etching will be carried out while deposition is carried out. Due to the reduction of the line width, the depth-to-width ratio of the isolation trench is getting larger and larger. During the deposition process, the top of the isolation trench is easily closed, resulting in the formation of holes in the lower part of the isolation trench. Therefore, an electric field is applied in the vertical direction during the etching process to accelerate the bombardment of the top by the ionized ions, thereby inhibiting the deposition and closure of the top of the isolation trench. For specific process parameters, see Table 1, which is an example table of process parameters of the prior art.

[0036] Table 1

[0037]

[0038] The Chinese names corresponding to the English names in the table are as follows:

[0039] DEP: deposition; ETCH: etching; TOP RF: top RF of reaction chamber; SIDE RF: edge RF of reaction chamber; BIASRF: vertical bias RF; Dep rate: deposition rate; ETCH rate: etching rate; SiH4-TOP: SiH4 gas is introduced from the top of the reaction chamber; He-TOP: He gas is introduced from the top of the reaction chamber.

[0040] The inventors analyzed that the vertical direction sets a relatively high energy deposition and sputtering ratio. The higher the energy, the smaller the deposition and sputtering ratio, resulting in higher sputtering. Higher sputtering will allow some ions to pass through the surface of the sediment and remain in the sediment below. Since NF3 is used to etch the sidewalls of the top of the isolation trench during the etching process, NF3 is ionized and accelerated by the vertical electric field. During the etching, some F elements will be buried in the sediment, that is: SiO2+NF3→SIF4+N xO, because the F element is very active and easy to precipitate, if this precipitation phenomenon occurs during the operation of the chip, it is easy to cause electron migration and affect the electrical properties of the chip.

[0041] In view of this, an embodiment of the present application provides a semiconductor structure and a method for forming the same, the method for forming the semiconductor structure comprising: providing a substrate; forming an isolation trench in the substrate; forming an isolation sub-dielectric layer in the isolation trench in a first reaction chamber, the isolation sub-dielectric layer conformally covering the isolation trench; after forming the isolation sub-dielectric layer, removing a portion of the isolation sub-dielectric layer on the top of the isolation trench sidewall in a second reaction chamber; repeating the steps of forming the isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer on the top of the isolation trench sidewall until the isolation trench is completely filled with the formed isolation sub-dielectric layer, wherein the multiple isolation sub-dielectric layers that completely fill the isolation trench are the isolation dielectric layers.

[0042] It can be seen that a method for forming a semiconductor structure provided in an embodiment of the present application deposits the insulator dielectric layer in a first reaction chamber; and etches part of the insulator dielectric layer on the top of the isolation groove side wall in a second reaction chamber, so that the etching is not affected by the electric field in the first reaction chamber, and ions entering the deposited insulator dielectric layer during etching are avoided, which affects the electrons in the insulator dielectric layer, thereby reducing the possibility of electron migration in the device, thereby improving the performance of the device.

[0043] In the following, in combination with the embodiments of the present application, a method for forming a semiconductor structure provided in the embodiments of the present application is described in detail.

[0044] refer to Figure 1 , Figure 1 A flow chart of a method for forming a semiconductor structure provided in an embodiment of the present application. Figure 1 It can be seen that the method for forming the semiconductor structure provided in this embodiment includes:

[0045] Step S1: providing a substrate;

[0046] Step S2: forming an isolation trench in the substrate;

[0047] Step S3: forming an isolation sub-dielectric layer in the isolation trench in the first reaction chamber;

[0048] Wherein, the isolation sub-dielectric layer conformally covers the isolation trench.

[0049] Step S4: in the second reaction chamber, removing a portion of the isolation sub-dielectric layer on the top of the isolation trench sidewall;

[0050] Step S5: determining whether the isolation trench is completely filled.

[0051] Specifically, if the isolation trench is not completely filled, repeat steps S3 and S4; if the isolation trench is completely filled, end. It can be understood that step S5 is to repeat the steps of forming an isolation sub-dielectric layer in the isolation trench and removing part of the isolation sub-dielectric layer on the top of the isolation trench sidewall until the isolation trench is completely filled with the formed isolation sub-dielectric layer, wherein the multiple isolation sub-dielectric layers that completely fill the isolation trench are the isolation dielectric layer.

[0052] Combine the following Figure 2-Figure 6 The method for forming the semiconductor structure provided in the embodiment of the present application is described in detail.

[0053] refer to Figure 2 , executing step S1, providing a substrate 100;

[0054] In the embodiment of the present application, the substrate 100 is a silicon substrate. In other embodiments, the substrate 100 may also be a germanium silicon substrate, a III-V group element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure, or may be a diamond substrate or other semiconductor material substrates known to those skilled in the art. The present invention does not make any specific limitation to this.

[0055] refer to Figure 3 , executing step S2, forming an isolation trench 200 in the substrate 100;

[0056] The isolation trenches can be implemented by etching process, wherein the etching process can be, for example, wet etching, dry etching or a combination of wet etching and dry etching. The number, shape and depth of the isolation trenches 200 can be adjusted according to specific needs, and the present invention does not make specific limitations on this.

[0057] refer to Figure 4 , executing step S3, forming an isolation sub-dielectric layer 300 in the isolation trench 200 in the first reaction chamber;

[0058] The isolator dielectric layer conformally covers the isolation trench, and the material of the isolator dielectric layer may be one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0059] It should be noted that step S3 specifically includes: forming the isolation sub-dielectric layer under a preset electric field, wherein the electric field power of the preset electric field is less than a first preset value, so that the ion density in the formed isolation sub-dielectric layer is less than a second preset value.

[0060] The electric field power of the preset electric field is less than the first preset value, so that the ion density in the formed isolation sub-medium layer is less than the second preset value. The first preset value is 1800-2000W; the second preset value is 1500-1700kg / m 3 .

[0061] By setting the electric field power of the preset electric field to be smaller than the first preset value, the ion density in the formed insulator dielectric layer is made smaller than the second preset value. Therefore, based on the smaller electric field strength, the number of ions accelerated into the deposited insulator dielectric layer is reduced, and the influence of ions in the insulator dielectric layer on electrons in the insulator dielectric layer is avoided, thereby reducing the possibility of electron migration in the device and improving the performance of the device.

[0062] In a specific embodiment, the isolator dielectric layer 300 is formed by a high density plasma process HDP. The thickness of the formed isolator dielectric layer is in the range of In the embodiment of the present application, the thickness of the isolator dielectric layer is set to

[0063] Among them, the reaction gases used in the high-density plasma process HDP include O2, SiH4, SiH4-TOP, H2 and He, the flow rate of the reaction gas O2 is 70-110sccm, the flow rate of the reaction gas SiH4 is 30-60sccm, the flow rate of the reaction gas SiH4-TOP is 10-20sccm, the flow rate of the reaction gas H2 is 110-150sccm, and the flow rate of the reaction gas He is 200-400sccm.

[0064] refer to Figure 5 , executing step S4, in the second reaction chamber, removing a portion of the isolation sub-dielectric layer 300 on the top of the sidewall of the isolation trench 200;

[0065] It should be noted that the thickness of the part of the isolator dielectric layer removed from the top of the isolation trench sidewall is in the range of In the embodiment of the present application, the thickness of the removed isolator dielectric layer is set to

[0066] In a specific embodiment, a SiCoNi etching process is used in the second reaction chamber to remove a portion of the isolation sub-dielectric layer 300 at the top of the isolation trench sidewall. The reaction gases used in the SiCoNi etching process include NH3 and NF3, the flow rate range of the reaction gas NH3 is 120-160sccm, the flow rate range of the reaction gas NF3 is 50-90sccm, the effective power is 20-60W, and the etching rate range is

[0067] The reaction gases NF3 and NH3 react chemically with the oxide on the surface of the semiconductor structure, thereby etching the insulator dielectric layer 300.

[0068] That is: SiO2+NF3+NH3→(NH4)2SiF6.

[0069] The (NH4)2SiF6 generated on the surface of the semiconductor structure is decomposed into gaseous SiF4, NH3 and HF by high temperature and removed, that is: (NH4)2SiF6→SiF4(g)+NH3(g)+HF(g).

[0070] Since (NH4)2SiF6 is decomposed into gaseous SiF4 and NH3, the residue of F element is avoided and the quality of the grown insulator dielectric layer is improved.

[0071] By depositing the insulator dielectric layer in the first reaction chamber and etching part of the insulator dielectric layer on the top of the isolation groove side wall in the second reaction chamber, the etching is not affected by the electric field in the first reaction chamber, and the ions entering the deposited insulator dielectric layer during etching are avoided to affect the electrons in the insulator dielectric layer, thereby reducing the possibility of electron migration in the device, thereby improving the performance of the device.

[0072] The process parameters of the above HDP deposition process and SiCoNi etching process are shown in Table 1. For specific process parameters, please refer to Table 2, which is an example table of process parameters of this application.

[0073] Table 2

[0074]

[0075] The Chinese names corresponding to the English names in the table are as follows:

[0076] DEP: deposition; ETCH: etching; TOP RF: top RF of reaction chamber; SIDE RF: edge RF of reaction chamber; BIASRF: vertical bias RF; Dep rate: deposition rate; HF POWER: high frequency RF power; ETCH rate: etching rate; SiH4-TOP: SiH4 gas is introduced from the top of the reaction chamber.

[0077] refer to Figure 6, execute step S5 to determine whether the isolation trench 200 is completely filled. If the isolation trench 200 is not completely filled, repeat steps S3 and S4; if the isolation trench 200 is completely filled, end. It can be understood that when step S5 determines that the isolation trench is not completely filled, the steps of forming an isolation sub-dielectric layer in the isolation trench and removing part of the isolation sub-dielectric layer on the top of the isolation trench sidewall are repeated until the isolation trench is completely filled with the formed isolation sub-dielectric layer, wherein the multiple isolation sub-dielectric layers 300 that completely fill the isolation trench 200 are the isolation dielectric layer 310.

[0078] In a specific embodiment, the steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer on the top of the isolation trench sidewall are performed once as one cycle, wherein the steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer on the top of the isolation trench sidewall are repeated for three cycles.

[0079] refer to Figure 7 , Figure 7 Another optional flow chart of the method for forming a semiconductor structure provided in an embodiment of the present application.

[0080] refer to Figure 7 It can be seen that after the step of repeatedly performing the steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer at the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation sub-dielectric layer, the step further includes:

[0081] Step S6: depositing a sacrificial layer, wherein the sacrificial layer completely covers the isolation dielectric layer;

[0082] Specifically, the sacrificial layer may be formed by using a deposition, spin coating or other process, and the sacrificial layer is used to provide a buffer for subsequent planarization.

[0083] refer to Figure 8 After the isolation trench 200 is completely filled with the formed isolation sub-dielectric layer, the multiple isolation sub-dielectric layers that completely fill the isolation trench 200 are the isolation dielectric layer 310. A sacrificial layer 400 is deposited, and the sacrificial layer 400 completely covers the isolation dielectric layer 310.

[0084] Step S7: planarizing the sacrificial layer and the isolation dielectric layer.

[0085] In step S7, a planarization process such as a chemical mechanical polishing process may be used to polish the sacrificial layer and the isolation dielectric layer.

[0086] refer to Fig. 9 , planarizing the sacrificial layer and the isolation dielectric layer.

[0087] It can be seen that a method for forming a semiconductor structure provided in an embodiment of the present application forms an isolator dielectric layer in the isolation groove in a first reaction chamber, and the isolator dielectric layer conformally covers the isolation groove; after the isolator dielectric layer is formed, a portion of the isolator dielectric layer on the top of the isolation groove side wall is removed in a second reaction chamber; the isolator dielectric layer is deposited in the first reaction chamber; and a portion of the isolator dielectric layer on the top of the isolation groove side wall is etched in the second reaction chamber, so that the etching is not affected by the electric field in the first reaction chamber, thereby avoiding the entry of ions into the deposited isolator dielectric layer during etching and the influence on the electrons in the isolator dielectric layer, thereby reducing the possibility of electron migration in the device, thereby improving the performance of the device.

[0088] In order to solve the aforementioned problem, an embodiment of the present application further provides a semiconductor structure, which is formed based on the method for forming the semiconductor structure as described above.

[0089] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0090] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming an isolation trench in the substrate; In the first reaction chamber, forming an isolator dielectric layer in the isolation trench, wherein the isolator dielectric layer conformally covers the isolation trench; After forming the isolator dielectric layer, in the second reaction chamber, removing a portion of the isolator dielectric layer on the top of the isolation trench sidewall; Repeat the steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer at the top of the isolation trench sidewall until the isolation trench is completely filled with the formed isolation sub-dielectric layer, wherein the multiple isolation sub-dielectric layers that completely fill the isolation trench are the isolation dielectric layer.

2. The method according to claim 1, characterized in that The step of forming an isolation sub-dielectric layer in the isolation groove is specifically: forming the isolation sub-dielectric layer under a preset electric field, wherein the electric field power of the preset electric field is less than a first preset value, so that the ion density in the formed isolation sub-dielectric layer is less than a second preset value.

3. The method according to claim 2, characterized in that The first preset value is 1800-2000W, and the second preset value is 1500-1700kg / m 3 .

4. The method according to claim 1, characterized in that In the step of forming the isolation sub-dielectric layer in the isolation trench, the isolation sub-dielectric layer is formed by adopting a high density plasma process HDP.

5. The method according to claim 4, characterized in that The reaction gases used in the high-density plasma process HDP include O2, SiH4, SiH4-TOP, H2 and He. The flow rate of the reaction gas O2 is 70-110sccm, the flow rate of the reaction gas SiH4 is 30-60sccm, the flow rate of the reaction gas SiH4-TOP is 10-20sccm, the flow rate of the reaction gas H2 is 110-150sccm, and the flow rate of the reaction gas He is 200-400sccm.

6. The method according to claim 4, characterized in that The thickness of the isolator dielectric layer is 7. The method according to claim 1, characterized in that In the step of removing a portion of the isolator dielectric layer on the top of the isolation trench sidewall, a SiCoNi etching process is used to remove a portion of the isolator dielectric layer on the top of the isolation trench sidewall.

8. The method according to claim 7, characterized in that The reaction gases used in the SiCoNi etching process include NH3 and NF3. The flow rate of the reaction gas NH3 is 120-160 sccm, the flow rate of the reaction gas NF3 is 50-90 sccm, the effective power is 20-60 W, and the etching rate is 9. The method according to claim 7, characterized in that The thickness of the part of the isolator dielectric layer removed from the top of the isolation trench sidewall is 10. The method according to claim 1, characterized in that The steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer on the top of the isolation trench sidewall are performed once as one cycle, wherein the steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer on the top of the isolation trench sidewall are repeated, specifically, for three cycles.

11. The method according to claim 1, characterized in that After the step of repeatedly performing the steps of forming an isolation sub-dielectric layer in the isolation trench and removing a portion of the isolation sub-dielectric layer at the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation sub-dielectric layer, the method further includes: Depositing a sacrificial layer, wherein the sacrificial layer completely covers the isolation dielectric layer; The sacrificial layer and the isolation dielectric layer are planarized.

12. A semiconductor structure, characterized in that: The semiconductor structure is formed based on the method for forming a semiconductor structure according to any one of claims 1 to 11.

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