Method for improving manufacturing yield of chip in semiconductor device

Abstract

The invention discloses a method for improving the manufacturing yield of a chip in a semiconductor device. According to the method, the key size of the dummy pattern in the photomask is optimized, the sharp corner effect after HDP DEP is improved, and the number of scratch sources in the STI CMP process is reduced, so that the number of micro scratches is reduced, and the yield of wafers is improved. According to the invention, by reducing tiny scratches of the chip, the chip defect and failure probability caused by scratches are reduced, so that the product yield of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a method for improving chip manufacturing yield in a semiconductor device. Background Art

[0002] In semiconductor manufacturing technology, isolation technology is the key to achieving electrical isolation between devices. With the development of technology, shallow trench isolation (STI) has become the mainstream isolation technology, replacing the earlier LOCOS (Local Oxidation of Silicon) technology.

[0003] STI technology mainly covers the following key steps: Shallow trench etching: High-precision etching operations are performed on pure silicon wafers to form shallow trenches. This process requires precise control of parameters such as etching depth, width and shape to meet the requirements of subsequent processes. Too shallow etching depth may lead to poor isolation effect, while too deep etching depth may affect the overall structural integrity of the silicon wafer. For example, in advanced semiconductor manufacturing processes, the depth of shallow trenches is usually controlled within the nanometer precision range to ensure that while forming the isolation structure, other properties of the silicon wafer are not damaged.

[0004] Silicon dioxide deposition: Silicon dioxide is deposited in the etched trenches to construct isolation structures. The deposition quality of silicon dioxide directly affects the isolation performance, requiring the deposition process to be uniform and dense without holes or defects. Process parameters such as temperature, pressure, and gas flow during the deposition process need to be strictly controlled. For example, through chemical vapor deposition (CVD) technology, a uniform silicon dioxide film can be accurately grown in the trenches, and its thickness is usually between a few hundred nanometers and a few microns depending on the specific device design requirements.

[0005] CMP planarization: Chemical mechanical polishing technology is used to planarize the surface of the silicon wafer after deposition, so that the surface of the silicon wafer reaches a high degree of flatness and smoothness to meet the requirements of subsequent photolithography, thin film deposition and other processes. During the CMP process, the surface of the silicon wafer interacts with the polishing pad and polishing liquid, and the excess material is removed through the synergistic effect of chemical reaction and mechanical polishing. However, this process is prone to problems such as chip scratches, which affects the product yield.

[0006] In the CMP process, chip scratches seriously affect the chip manufacturing yield and product quality. Scratches are divided into macro scratches and micro scratches. Micro scratches are mainly caused by the friction between the sharp corners formed on the surface after HDP DEP (high-density plasma deposition) and the chip surface. In STI technology, after the trench is filled with high-density plasma silicon oxide (HDP-OX), sharp corners will be formed on the surface of the active area, especially in the pattern-dense area (such as the dummy pattern surface). During STI-CMP grinding, these sharp corners may scratch the surface of the wafer. Due to the continuous grinding process, the large sharp corners that are knocked off remain between the wafer and the grinding pad and cannot be removed, becoming a scratch source, which makes it easy to form scratches during the CMP process. Therefore, reducing or eliminating chip scratches during the CMP process, especially micro scratches, is crucial to improving the efficiency of semiconductor manufacturing processes, product yields, and final product performance and reliability. This is also a major challenge facing existing STI technology. Summary of the invention

[0007] The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art and provide a method for improving the chip manufacturing yield in a semiconductor device.

[0008] The present invention is implemented in this way, providing a method for improving the chip manufacturing yield in a semiconductor device, by optimizing the chip micro-scratch rate by adjusting the critical dimension change amount of a dummy pattern in a photomask.

[0009] Preferably, the change amount of the critical dimension of the filling pattern in the mask is equal to the critical dimension of the filling pattern in the original mask multiplied by the critical dimension reduction factor.

[0010] Preferably, the critical dimension reduction factor is equal to the reduced mask size divided by the original mask size.

[0011] Preferably, the critical dimension reduction factor is 100% or 90%.

[0012] Preferably, the method is suitable for semiconductor devices with shallow trench isolation, and more preferably, the trench is filled with high-density plasma oxide (HDP-OX).

[0013] The beneficial effects of the present invention are: The present invention optimizes the critical size of the dummy pattern in the mask, improves the sharp corner effect after HDP DEP, and reduces the scratch source in the STI CMP process, thereby reducing the number of micro scratches and improving the yield of the wafer, thereby solving the problem of improving the chip manufacturing yield in semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 It is a 55nm STI process flow.

[0016] Figure 2 This is the dummy appearance after HDP DEP.

[0017] Figure 3 Schematic diagram of the surface corners of a semiconductor device during the CMP process when the size of the dummy pattern is 3.5*3.0 nm, where (a) is an electron microscope image of 500nm and (b) is an electron microscope image of 200nm.

[0018] Figure 4 Schematic diagram of the surface corners of a semiconductor device during the CMP process when the size of the dummy pattern is 3.888*3.333 nm, where (a) is a 500nm electron microscope image and (b) is a 200nm electron microscope image.

[0019] Figure 5 Comparison of the number of scratches on dummy wafers of different sizes. The horizontal axis is the coordinates of the test points on wafers of different batches at different scanning times, and the vertical axis is the number of scratches. DETAILED DESCRIPTION

[0020] Wafer scratches often occur during the STI-CMP process grinding of semiconductor devices. Reduce or eliminate chip scratches during the CMP process, especially minor scratches. Chip scratches not only reduce the yield, but may also cause a series of potential problems. In terms of the electrical performance of the chip, scratches may damage the active area or metal connections, leading to problems such as increased local resistance, current leakage or signal transmission interruption. From the perspective of chip reliability, scratches may become stress concentration points, which may easily cause crack propagation during subsequent processes or chip use, leading to chip failure. In addition, scratches may also affect the bonding performance between the chip and the packaging material, reduce the packaging reliability, and thus affect the service life and stability of the entire semiconductor device.

[0021] The main steps of STI technology include etching shallow trenches on pure silicon wafers, depositing silicon dioxide, and finally using chemical mechanical polishing (CMP) technology to planarize the surface. Figure 1 shown.

[0022] In STI technology, trenches are usually filled with high-density plasma oxide (HDP-OX). After filling, sharp corners will be formed on the surface of the active area, especially in the pattern-dense area, especially on the surface of the filling pattern dummy pattern, such as Figure 2 shown.

[0023] Therefore, the present invention provides a method for improving the chip manufacturing yield in semiconductor devices, which is optimized by adjusting the critical dimension change of the filling pattern (dummy pattern) in the mask, and is committed to solving the problem of fine scratches faced by chips in the chemical mechanical polishing (CMP) process during the semiconductor device manufacturing process. By innovatively adjusting the critical dimension change of the filling pattern (dummy pattern) in the mask, the chip manufacturing process is optimized, thereby improving the yield and reliability of semiconductor products, which is of key significance in the continuous development of semiconductor manufacturing technology.

[0024] In the semiconductor manufacturing process, the determination of the size of the original mask dummy pattern is a rigorous process based on industry experience. It is set according to the requirements of a specific process node and fully draws on the mature experience of Semiconductor Manufacturing International Corporation (SMIC) in similar processes. Specifically, its length is precisely set to 3.888 microns and its width is 3.333 microns. These size parameters are considered to be options that can meet the chip layout and functional requirements while taking into account manufacturing feasibility in the initial process design. However, through in-depth statistics and detailed analysis of a large number of long-term tape-out defect data, it is found that when a dummy pattern of this size is used for chip manufacturing, the number of scratches on the entire wafer is always maintained at a high level, with an average of about 85. Because wafer scratches will directly lead to a decrease in chip yield, which in turn affects production costs and product quality. In order to explore the root cause of the scratch problem, the inventor of this case further conducted a comprehensive failure analysis (FA) on the scratch type, location distribution, and correlation with the dummy pattern. For example, a detailed inspection of the scratched chip using a high-resolution optical microscope and a scanning electron microscope (SEM) revealed that the tiny scratches were mainly concentrated in the area associated with the dummy pattern. This preliminarily indicated that the dummy pattern may play an important role in the chip scratch mechanism, and clarified the direction for subsequent research and improvement work.

[0025] In order to gain a deeper understanding of the microstructural characteristics of the dummy pattern during chip manufacturing and its potential impact on chip scratches, advanced material analysis technology was used to conduct fine section analysis of the dummy after high-density plasma deposition (HDP DEP). Through observations with high-resolution scanning electron microscopes (SEM) and atomic force microscopes (AFM), it was clearly found that the dummy after HDP DEP showed a distinct sharp-angle structure, and the height of the sharp corners was accurately measured to be 221.4 nanometers. From the perspective of the principles of material mechanics and surface physics, this sharp-angle structure poses potential risks in the chip manufacturing process. According to the stress concentration theory, local stress concentration will occur at the sharp corners. In the subsequent chemical mechanical polishing (CMP) and other processes of the chip, when subjected to external forces, these stress concentration areas are more likely to cause material rupture and wear, thereby causing chip scratches. Further theoretical research and experimental data show that there is a close relationship between the sharp-angle effect and size. The present invention proposes to reduce the critical size of the dummy pattern in the mask, and simulates the stress distribution of sharp corners of different sizes during the CMP process through finite element analysis (FEA). It can be seen intuitively that as the size of the sharp corner decreases, the area of ​​the stress concentration region and the stress peak both show a significant downward trend, which provides a solid theoretical basis for optimizing the chip manufacturing process by adjusting the size of the dummy pattern in the future.

[0026] The present invention optimizes the chip manufacturing process by regulating the critical dimension change of the dummy pattern in the mask. The mask plays a key template role in semiconductor manufacturing and determines the shape and size of various patterns on the chip. Although the dummy pattern does not directly participate in the electrical function of the chip, it has an important influence on the physical and chemical processes in the manufacturing process. For example, the change in its size will affect the material distribution and stress conditions in the deposition, etching and other process processes.

[0027] The change in the critical dimension of the fill pattern in the mask is calculated as the critical dimension of the fill pattern in the original mask multiplied by the critical dimension reduction factor. The critical dimension reduction factor is a key parameter, which is equal to the reduced mask size divided by the original mask size.

[0028] In the process of semiconductor manufacturing process optimization, the critical dimension reduction factor is a key design parameter, which is defined as the ratio of the reduced mask size to the original mask size. The reasonable selection of this factor is crucial for the precise control of the critical dimensions of the dummy pattern, which directly affects multiple performance indicators in the chip manufacturing process. According to the dummy design rules widely followed by the industry, after a lot of experimental verification and simulation analysis, the dummy size shrink factor can be set to 100% and 90%. Taking 90% as an example, when this shrink factor is applied, the size of the original mask dummy will be precisely adjusted accordingly. For the dummy pattern with an original length of 3.888 microns and a width of 3.333 microns, the new length is calculated to be 3.888×90% = 3.499 microns, and the new width is 3.333×90% = 2.997 microns.

[0029] In order to verify the actual effect of this size adjustment, a rigorous comparative test was conducted during the chip manufacturing process. After HDP DEP was performed on a dummy pattern of the original size (3.888×3.333 microns), the height of the surface corners was measured to be 221.4 nanometers by high-precision measuring equipment (such as SEM and AFM). Figure 4 Middle (a) - Figure 4 When the dummy pattern size was adjusted to 3.5×3 μm according to a 90% shrink factor, the surface corner height was significantly reduced to 187 nm. Figure 3 Middle (a) - Figure 3 This significant change shows that the sharp corner effect after HDP DEP can be effectively improved by properly adjusting the size of the dummy pattern.

[0030] The chip scratches were further investigated. In order to verify the actual effect of the size adjustment, strict comparative tests were carried out during the chip manufacturing process. After HDP DEP was performed using the original size (3.888×3.333 microns) dummy pattern, the surface sharp corner height was measured to be 221.4 nanometers using high-precision measuring equipment (such as SEM and AFM); after the dummy pattern size was adjusted to 3.5×3 microns according to a 90% shrink factor, it was found that the sharp corner height was significantly reduced to 187 nanometers. The chip scratches were further investigated. Under the same chip manufacturing conditions, when the original size dummy pattern was used, the average number of SIN RM micro-scratches reached 85, which seriously affected the wafer yield; using the adjusted 3.5×3 micron size dummy pattern, after statistical analysis of multiple batches of wafers, the number of SIN RM micro-scratches was significantly reduced to 17. Figure 5 This significant improvement fully proves that by accurately controlling the dummy size shrink factor and optimizing the key size of the dummy pattern, it is possible to effectively reduce micro scratches on the chip, improve the wafer yield, and provide a practical solution for improving the semiconductor manufacturing process. At the same time, the electrical performance of the chip was tested, such as measuring the resistance, capacitance and other parameters of the chip under dummy patterns of different sizes. It was found that the consistency of electrical performance was improved after the size adjustment, which further verified the effectiveness of this method.

[0031] Table 1 FA angle data of different dummy sizes (Unit: nm)

[0032] “Center inline THK” is used to reflect the thickness of the area on the center line.

[0033] In the actual implementation of the present invention to improve the chip manufacturing yield in semiconductor devices by reducing the micro scratches on the chip, the systematicness and complexity of the semiconductor manufacturing process are fully considered, and other related process parameters are deeply optimized. Take the chemical mechanical polishing (CMP) process as an example, which is a key process link involving the interaction of multiple factors. In order to further improve the polishing effect and reduce the risk of scratches, the researchers carried out a series of detailed process optimization work.

[0034] In terms of polishing fluid, by screening different chemical components and optimizing the ratio, its composition is adjusted, such as adding specific oxidants or complexing agents to enhance the chemical reaction activity during the polishing process and promote the uniformity of material removal. At the same time, the concentration of the polishing fluid is precisely controlled to ensure the best balance between chemical reaction and mechanical action. In addition, the flow rate of the polishing fluid is optimized. According to factors such as the rotation speed of the polishing pad, the size of the wafer, and the polishing pressure, the optimal flow rate range is determined through fluid mechanics simulation and experimental verification, so that the polishing fluid can be evenly distributed on the wafer surface, and the debris generated during the polishing process is promptly removed to avoid secondary scratches.

[0035] The polishing pad is also optimized in multiple dimensions. Through material science research, the polishing pad material with appropriate hardness and elastic modulus is selected, and its hardness distribution is precisely controlled to ensure that sufficient mechanical grinding force is provided to remove materials during the grinding process, while avoiding excessive scratches on the wafer surface due to improper hardness. At the same time, the roughness of the polishing pad is optimized, and the surface of the polishing pad is microstructured using surface engineering technology to match its surface texture with the material removal mechanism of the wafer surface, thereby improving grinding efficiency and surface quality.

[0036] In order to achieve continuous improvement, various key data are regularly collected and comprehensively analyzed during the chip manufacturing process, including detailed statistics on the number of scratches (distinguishing scratches of different types and severity), accurate calculation of wafer yield (using advanced defect detection equipment and statistical analysis methods), and accurate measurement of chip electrical properties (such as resistance measurement through four-probe, capacitance-voltage (C-V) test, etc.). Based on the results of in-depth data analysis, statistical process control (SPC) and other methods are used to determine whether the process is in a stable state. Once abnormal fluctuations or trends are found, the root cause analysis (RCA) process is initiated in a timely manner to determine whether the problem is caused by factors such as process parameter changes, equipment performance drift, or material property fluctuations. Then, process parameters are adjusted in a targeted manner, such as grinding pressure and grinding time in the CMP process, or manufacturing methods are improved, such as optimizing the mask manufacturing process and improving temperature control in the deposition process. Through this continuous cycle of improvement process, it is ensured that the chip manufacturing process is always kept in the best state, and product quality and production efficiency are continuously improved to meet the needs of the rapid development of the semiconductor industry.

[0037] The method for improving the yield of semiconductor device products provided by the present invention directly adopts the above-mentioned method for reducing micro scratches on chips. By reducing micro scratches on chips, the probability of chip defects and failures caused by scratches is reduced, thereby improving the yield of semiconductor device products. In the semiconductor manufacturing process, yield is a key indicator that is directly related to production costs and product quality. For example, in large-scale integrated circuit manufacturing, even a small improvement in yield can bring significant economic benefits, while ensuring that the product meets market demand in terms of performance and reliability.

[0038] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for improving chip manufacturing yield in a semiconductor device, characterized in that: The method optimizes the chip micro-scratch rate by regulating the critical dimension change amount of the filling pattern in the mask.

2. A method for improving chip manufacturing yield in a semiconductor device according to claim 1, characterized in that: The change amount of the critical dimension of the filling pattern in the mask is equal to the critical dimension of the filling pattern in the original mask multiplied by the critical dimension reduction factor.

3. A method for improving chip manufacturing yield in a semiconductor device according to claim 2, characterized in that: The critical dimension reduction factor is equal to the reduced mask size divided by the original mask size.

4. A method for improving chip manufacturing yield in a semiconductor device according to claim 2 or 3, characterized in that: The critical dimension reduction factor is 100% or 90%.

5. A method for improving chip manufacturing yield in a semiconductor device according to claim 1, characterized in that: The semiconductor device has shallow trench isolation.

6. A method for improving chip manufacturing yield in a semiconductor device according to claim 5, characterized in that: The trench is filled with silicon oxide using high-density plasma.

Images