Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof, and the method comprises the steps: forming a recessed region in the top surface of an isolation structure through employing the grinding process of forming the isolation structure, forming a protection layer in the recessed region for protecting the isolation structure, and employing the protection layer for protecting the isolation structure to remove a hard mask layer through etching. The height difference of the isolation structures in different areas caused by etching the isolation structures in the process of removing the hard mask layer is avoided; the epitaxial layer is formed on the top surface of the substrate in an epitaxial manner after the hard mask layer is removed, and the substrate between the epitaxial layer and the isolation structure is jointly used as the active region, so that the top surface of the active region is flush with the top surface of the isolation structure, the height of the active region is adjusted, and the step height of the isolation structure and the active region is eliminated; and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] The shallow trench isolation (STI) structure is used to isolate active areas between active areas to prevent leakage and other situations. The shallow trench isolation structure is crucial to the performance and yield of the final semiconductor structure. The manufacturing process of the STI structure causes the shallow trench isolation structure to have a step height, that is, the height of the STI structure is higher than the surface of the semiconductor substrate. The step height of the STI structure has a significant impact on the performance of the semiconductor structure.

[0003] In particular, the pattern density of STI structures in different regions is different. During the manufacturing process of STI structures, the step heights of STI structures in regions with different pattern densities may be different, which may affect the performance of semiconductor structures. As the critical dimensions of semiconductor structures continue to shrink, it is increasingly difficult to control the step heights of STI structures in regions with different pattern densities, and the step height differences of STI structures in regions with different pattern densities have an increasingly greater impact on the performance of semiconductor structures. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof to address the problem that the manufacturing process of the shallow trench isolation structure in the prior art causes differences in the step heights of the shallow trench isolation structures in different pattern density areas, which affects the performance of the semiconductor structure.

[0005] In a first aspect, the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0006] Providing an initial structure, the initial structure comprising a substrate and an isolation structure formed in the substrate, the top surface of the substrate being covered by a hard mask layer, the top surface of the isolation structure being higher than the top surface of the substrate, and the top surface of the isolation structure being recessed relative to the hard mask layer;

[0007] forming a protective layer to cover the top surface of the isolation structure and fill the recessed area of ​​the isolation structure;

[0008] Etching and removing the hard mask layer to expose the top surface of the substrate;

[0009] An epitaxial layer is epitaxially formed on the top surface of the substrate, the epitaxial layer is used as an active region, and the top surface of the active region is flush with the top surface of the protective layer.

[0010] Optionally, forming a protection layer to cover the top surface of the isolation structure and fill a recessed area of ​​the isolation structure includes:

[0011] forming a protective material layer, wherein the protective material layer covers a top surface of the isolation structure, a top surface of the hard mask layer, and fills a recess at the top of the isolation structure;

[0012] The protective material layer is ground to expose the top surface of the hard mask layer, and the protective material layer at the recessed portion of the top of the isolation structure is ground to remain to form the protective layer.

[0013] Optionally, the material of the protective layer includes at least one of silicon oxycarbide, silicon carbonitride or silicon oxynitride.

[0014] Optionally, an oxide layer is formed on the top surface of the substrate, and the oxide layer is disposed between the substrate and the hard mask layer;

[0015] After the hard mask layer is removed by etching, the oxide layer is removed by etching to expose the top surface of the substrate.

[0016] Optionally, provide an initial structure, including:

[0017] Providing an initial substrate, forming the hard mask layer on a top surface of the initial substrate, wherein the hard mask layer defines a pattern of the isolation structure;

[0018] Etching the initial substrate according to the hard mask layer to form an isolation trench in the initial substrate, and etching the remaining initial substrate to form the substrate;

[0019] forming an isolation layer, wherein the isolation layer fills the isolation trench and covers a top surface of the hard mask layer;

[0020] The isolation layer on the hard mask layer is removed by grinding, and the isolation layer remaining in the isolation trench forms the isolation structure.

[0021] Optionally, the manufacturing method further comprises:

[0022] A pad oxide layer is formed, wherein the pad oxide layer at least covers a top surface of the active region.

[0023] Optionally, the substrate includes a first region and a second region, and the isolation structure in the first region has a different size from the isolation structure in the second region;

[0024] After the epitaxial layer is formed by epitaxial growth, the top surfaces of the first region and the second region are flush.

[0025] In a second aspect, the present disclosure provides a semiconductor structure, comprising:

[0026] substrate;

[0027] An isolation structure is arranged in the substrate to divide the substrate into active areas arranged at intervals, and a top surface of the isolation structure has a concave area;

[0028] A protective layer, covering the top surface of the isolation structure and filling a recessed area of ​​the isolation structure;

[0029] An epitaxial layer is arranged on the top surface of the substrate, the epitaxial layer and the substrate between the isolation structure serve together as the active area, and the top surface of the active area is flush with the top surface of the protective layer.

[0030] Optionally, the material of the protective layer includes at least one of silicon oxycarbide, silicon carbonitride or silicon oxynitride.

[0031] Optionally, the substrate includes a first region and a second region, the isolation structure in the first region and the isolation structure in the second region have different sizes; and the top surfaces of the first region and the second region are flush.

[0032] The semiconductor structure and the manufacturing method thereof disclosed in the present invention utilize a recessed area formed on the top surface of the isolation structure during the grinding process of forming the isolation structure, form a protective layer in the recessed area to protect the isolation structure, and utilize the protective layer to protect the isolation structure to etch and remove the hard mask layer, thereby preventing the isolation structure from being etched during the process of removing the hard mask layer, resulting in height differences in the isolation structures in different areas. After removing the hard mask layer, the present invention forms an epitaxial layer on the top surface of the substrate by epitaxial growth, and the substrate between the epitaxial layer and the isolation structure serves as an active area together, so that the top surface of the active area is flush with the top surface of the isolation structure, thereby achieving adjustment of the height of the active area, eliminating the step height between the isolation structure and the active area, and facilitating improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a process flow chart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0035] Figure 2 is a schematic diagram of a structure after a hard mask layer is formed on an initial substrate provided in an embodiment;

[0036] Figure 3 is a schematic diagram of a structure after an isolation trench is formed in an initial substrate provided in an embodiment;

[0037] Figure 4 A schematic diagram of a structure after an isolation layer is formed provided in an embodiment;

[0038] Figure 5 A schematic diagram of an initial structure provided in an embodiment;

[0039] Figure 6 A schematic diagram of a structure after a protective material layer is formed provided in an embodiment;

[0040] Figure 7 A schematic diagram of a structure after a protective layer is formed provided in an embodiment;

[0041] Figure 8 A schematic diagram of a structure after etching and removing the hard mask layer provided in an embodiment;

[0042] Fig. 9 is a schematic diagram of a structure after etching to expose the top surface of the substrate provided in an embodiment;

[0043] Fig.10 A schematic diagram of a structure after forming an epitaxial layer provided in an embodiment;

[0044] Fig.11 It is a schematic diagram of the structure after forming a pad oxide layer provided in one embodiment.

[0045] Description of reference numerals:

[0046] 100, initial structure; 10, substrate; 11, active area; 101, initial substrate; 102, isolation trench; 103, oxide layer; 20, isolation structure; 120, first isolation structure; 220, second isolation structure; 21, isolation layer; 30, hard mask layer; 40, protective layer; 41, protective material layer; 60, epitaxial layer; 70, pad oxide layer; A1, first region; A2, second region. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used in the specification of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0049] In the related art, the manufacturing method of the shallow trench isolation structure is: forming a hard mask layer on a substrate, etching the substrate according to the hard mask layer to form a groove in the substrate, and then filling the trench with an isolation material to form a shallow trench isolation structure. Then, the hard mask layer is removed by etching. After removing the hard mask layer, the top surface of the shallow trench isolation structure is higher than the top surface of the substrate. In order to eliminate or reduce the step height of the shallow trench isolation structure, it is necessary to perform a back-etching step on the shallow trench isolation structure. However, the graphic density of the shallow trench isolation structure in different regions is different. After back-etching the shallow trench isolation structure, the height difference between the shallow trench isolation structure and the substrate in different regions may be different, affecting the performance of the semiconductor structure. The process of back-etching the shallow trench isolation structure may etch the substrate and form a notch in the side wall of the active area of ​​the substrate.

[0050] Furthermore, filling the trench with isolation material to form a shallow trench isolation structure requires grinding to remove the isolation material on the hard mask layer. The grinding process may cause the top surface of the shallow trench isolation structure to sag, affecting the execution of subsequent device manufacturing processes.

[0051] In view of this, the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein a recessed area is formed on the top surface of the isolation structure during the grinding process of forming the isolation structure, a protective layer is formed in the recessed area to protect the isolation structure, and the hard mask layer is etched away by the protective layer to protect the isolation structure, thereby preventing the isolation structure from being etched into during the process of removing the hard mask layer, resulting in height differences in the isolation structures in different areas; the present disclosure forms an epitaxial layer on the top surface of the substrate after removing the hard mask layer, and the substrate between the epitaxial layer and the isolation structure serves as an active area together, so that the top surface of the active area is flush with the top surface of the isolation structure, thereby achieving adjustment of the height of the active area, eliminating the step height between the isolation structure and the active area, and facilitating improving the performance of the semiconductor structure.

[0052] According to an exemplary embodiment, the present disclosure provides a method for manufacturing a semiconductor structure, please refer to Figure 1 As shown, the method for manufacturing a semiconductor structure includes the following steps:

[0053] Step S10: providing an initial structure, the initial structure comprising a substrate and an isolation structure formed in the substrate, the top surface of the substrate being covered by a hard mask layer, the top surface of the isolation structure being higher than the top surface of the substrate, and the top surface of the isolation structure being recessed relative to the hard mask layer.

[0054] Step S20: forming a protection layer to cover the top surface of the isolation structure and fill the recessed area of ​​the isolation structure.

[0055] Step S30: etching and removing the hard mask layer to expose the top surface of the substrate.

[0056] Step S40: forming an epitaxial layer on the top surface of the substrate by epitaxy, the epitaxial layer is used as an active region, and the top surface of the active region is flush with the top surface of the protective layer.

[0057] Figure 2-Figure 11 Schematic diagrams showing various stages of a method for manufacturing a semiconductor structure of some embodiments of this example are shown below. Figure 2-Figure 11 The manufacturing methods of the semiconductor structures of some embodiments of this example are introduced.

[0058] In step S10, referring to Figure 5 As shown, combined Figure 2-Figure 4 The initial structure 100 includes a substrate 10 and an isolation structure 20, wherein the isolation structure 20 extends from the top surface of the substrate 10 to the bottom surface of the substrate 10. A hard mask layer 30 for making the isolation structure 20 is formed on the top surface of the substrate 10, wherein the top surface of the isolation structure 20 is higher than the top surface of the substrate 10, and the top surface of the isolation structure 20 is recessed relative to the hard mask layer 30. The recessed top surface of the isolation structure 20 is formed during the grinding process of making the isolation structure 20.

[0059] It can be understood that the depths of the isolation structures 20 in different regions of the substrate 10 that are recessed relative to the hard mask layer 30 are not completely the same. Different pattern densities or sizes of the isolation structures 20 in different regions may affect the manufacturing process of the isolation structures 20, resulting in different recessed depths of the top surfaces of the isolation structures 20 in different regions, and even different heights of the top surfaces of the isolation structures 20 in different regions.

[0060] Among them, the substrate 10 is made of semiconductor material, and the semiconductor material can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials with semiconductor properties, such as III-V group compounds such as gallium arsenide.

[0061] The material of the hard mask layer 30 may include a carbon material. Alternatively, the hard mask layer 30 may also be other suitable materials that can be removed in wet etching. The hard mask layer 30 may include a single layer or a multi-layer structure.

[0062] The isolation structure 20 may include a single-layer or multi-layer isolation layer 21. For example, the isolation structure 20 may include silicon oxide.

[0063] In some embodiments, step S20 forms a protection layer 40 to cover the top surface of the isolation structure 20 and fill the recessed area of ​​the isolation structure 20, including the following steps:

[0064] Step S21 : forming a protection material layer 41 , wherein the protection material layer 41 covers the top surface of the isolation structure 20 , the top surface of the hard mask layer 30 , and fills the recess at the top of the isolation structure 20 .

[0065] Reference Figure 6The protective material layer 41 may be deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the protective material layer 41 covers the top surface of the isolation structure 20 and the top surface of the hard mask layer 30 and fills the recess at the top of the isolation structure 20 .

[0066] Step S22 : grinding the protective material layer 41 to expose the top surface of the hard mask layer 30 , and grinding the protective material layer 41 remaining in the recessed portion at the top of the isolation structure 20 to form a protective layer 40 .

[0067] Reference Figure 7 The top surface of the hard mask layer 30 is used as the grinding end point, and the protective material layer 41 is ground by a chemical mechanical polishing (CMP) process. The grinding rate of the protective material layer 41 is close to that of the hard mask layer 30. After the protective material layer 41 on the top surface of the hard mask layer 30 is removed by grinding, the protective material layer 41 located in the recess at the top of the isolation structure 20 forms a protective layer 40, and the top surface of the protective layer 40 is basically flush with the top surface of the hard mask 30.

[0068] In some embodiments, the material of the protection layer 40 includes at least one of silicon oxycarbide, silicon carbonitride, or silicon oxynitride.

[0069] In this embodiment, the material of the protection layer 40 includes silicon oxycarbide.

[0070] The top surface of the protection layer 40 is flat, and the top surface of the protection layer 40 is flush with the top surface of the hard mask layer 30. In this way, the protection layer 40 fills the recessed area at the top of the isolation structure 20, and the protection layer 40 can not only protect the isolation structure 20, but also eliminate the height difference of the isolation structure 20 in different areas.

[0071] In step S30, referring to Figure 8 , Fig. 9 , the hard mask layer 30 can be etched by a wet process, and the top surface of the substrate 10 is exposed after the hard mask layer 30 is removed. The etching solution used in the wet process has a high etching selectivity ratio between the hard mask layer 30 and the substrate 10 and the isolation structure 20, so that after the hard mask layer 30 is removed, the top surface of the substrate 10 in different regions and the isolation structure 20 have the same step height.

[0072] In step S40, referring to Fig.10The epitaxial layer 60 can be epitaxially formed on the top surface of the substrate 10 by molecular beam epitaxy (MBE), vapor phase epitaxy (VPE) or metal-organic chemical vapor deposition (MOCVD). The material of the epitaxial layer 60 includes a semiconductor material, and the lattice direction of the epitaxial layer 60 is the same as the crystal direction of the substrate 10. The epitaxial layer 60 and the substrate 10 between the isolation structure 20 are used together as an active region 11, and the active region 11 is used to form a semiconductor device.

[0073] The material of the epitaxial layer 60 can be the same semiconductor material as the substrate 10, or can be different from the substrate 10 according to the device manufacturing requirements. For example, the material composition, conductivity type, and resistivity of the epitaxial layer 60 are different from those of the substrate 10.

[0074] In one example, the epitaxial layer 60 is made of the same material as the substrate 10. The substrate 10 is a silicon substrate, and the epitaxial layer 60 is made of single crystal silicon. This helps to reduce the lattice mismatch at the contact interface between the epitaxial layer 60 and the substrate 10, and improve the quality of the epitaxial layer 60 and the performance of the device.

[0075] In another example, the epitaxial layer 60 is made of a different material from the substrate 10. The substrate 10 is a silicon substrate, and the epitaxial layer 60 is made of silicon germanium. In this example, it can be applied to manufacturing a PMOS device, epitaxial silicon germanium is formed to form the epitaxial layer 60, and the epitaxial layer 60 serves as the source and / or drain of the PMOS, thereby improving the stress of the PMOS and improving the device performance.

[0076] The manufacturing method of the semiconductor structure of the present embodiment forms a protective layer 40 in a recessed area on the top surface of the isolation structure 20 to protect the isolation structure 20 with the protective layer 40, and at the same time eliminates the height difference of the isolation structure 20 through the protective layer 40, so that the top surfaces of the protective layer 40 on the isolation structure 20 in each area are located in the same plane. After removing the hard mask layer 30, an epitaxial layer 60 is epitaxially formed on the top surface of the substrate 10 as the active area 11, so that the top surface of the active area 11 and the top surface of the protective layer 40 are located in the same plane, and the step height between the active area 11 and the isolation structure 20 is eliminated, which is beneficial to improving the performance of the semiconductor structure.

[0077] In some embodiments, step S10 provides an initial structure 100, including:

[0078] Reference Figure 2Step S11: providing an initial substrate 101, forming a hard mask layer 30 on the top surface of the initial substrate 101, and defining the pattern of the isolation structure 20 on the hard mask layer 30. Forming the hard mask layer 30 on the top surface of the initial substrate 101, patterning the hard mask layer 30, exposing a portion of the top surface of the initial substrate 101, and defining the pattern of the isolation structure 20 on the hard mask layer 30.

[0079] Reference Figure 3 , step S12 : etching the initial substrate 101 according to the hard mask layer 30 , forming an isolation trench 102 in the initial substrate 101 , and etching the retained initial substrate 101 to form a substrate 10 .

[0080] Reference Figure 4 Step S13: forming an isolation layer 21, the isolation layer 21 fills the isolation trench 102 and covers the top surface of the hard mask layer 30. In this embodiment, one or more isolation layers 21 may be deposited by ALD or CVD.

[0081] Reference Figure 5 , step S14: grinding and removing the isolation layer 21 on the hard mask layer 30, and the isolation layer 21 remaining in the isolation groove 102 forms an isolation structure 20. In this embodiment, the top surface of the hard mask layer 30 is used as the grinding end point, and the isolation layer 21 is ground by CMP to remove the isolation layer 21 on the top surface of the hard mask layer 30. Since the grinding resistance of the isolation layer 21 is lower than that of the hard mask layer 30, after the grinding stops, the top surface of the isolation layer 21 is recessed relative to the hard mask layer 30.

[0082] In some embodiments, the critical dimensions and pattern densities of the isolation trenches 102 in different regions of the substrate 10 are different. When the isolation layer 21 is polished, affected by the loading effect, the critical dimensions of the isolation trenches 102 are small and the pattern density is large in the region, and the top surface of the isolation structure 20 is recessed deeper.

[0083] In some embodiments, reference Figure 2 An oxide layer 103 may be formed on the top surface of the initial substrate 101 . The oxide layer 103 may be formed by a deposition process or a thermal oxidation process. The oxide layer 103 may also be formed by natural oxidation of the initial substrate 101 .

[0084] In some of these examples, reference Figure 5 , a hard mask layer 30 is formed on the top surface of the oxide layer 103, an oxide layer 103 is formed on the top surface of the substrate 10 of the initial structure 100, and the oxide layer 103 is disposed between the substrate 10 and the hard mask layer 30; Figure 8 , Fig. 9 After the hard mask layer 30 is removed by etching, the oxide layer 103 is removed by etching to expose the top surface of the substrate 10 .

[0085] In other examples, after the oxide layer 103 on the top surface of the initial substrate 101 is etched away, a hard mask layer 30 directly in contact with the initial substrate 101 is formed on the top surface of the initial substrate 101. In this example, a first isolation layer, a second isolation layer, and a third isolation layer may be sequentially deposited in the isolation trench 102 to form an isolation structure 20, wherein the materials of the first isolation layer and the third isolation layer may include silicon oxide, and the material of the second isolation layer may include silicon nitride. The isolation structure 20 is an oxide-nitride-oxide (ONO) stack, which is beneficial to improving the isolation effect of the isolation structure 20 and optimizing the device performance. In this example, after the hard mask layer 30 is etched away, it is not necessary to perform the step of etching away the oxide layer 103, so as to avoid damaging the first isolation layer by etching away the oxide layer 103, avoid forming a notch on the side wall of the isolation structure 20, ensure the structural integrity of the isolation structure 20, and ensure that the isolation structure 20 has a good isolation effect.

[0086] In some embodiments, the manufacturing method further comprises: referring to Fig.11 As shown, step S50: forming a liner oxide layer 70, the liner oxide layer 70 at least covers the top surface of the active region 11. The liner oxide layer 70 can be formed on the top surface of the epitaxial layer 60 by a thermal oxidation process; or, the liner oxide layer 70 can be formed by ALD deposition, and the liner oxide layer 70 covers the top surface of the active region 11 and the top surface of the protective layer 40.

[0087] Illustratively, the material of the pad oxide layer 70 includes silicon oxide.

[0088] In some embodiments, reference Figure 2-Figure 11 As shown, the substrate 10 includes a first region A1 and a second region A2. The isolation structure 20 in the first region A1 and the isolation structure 20 in the second region A2 have different sizes. After the epitaxial layer 60 is formed by epitaxial growth, the top surfaces of the first region A1 and the second region A2 are flush.

[0089] In this embodiment, when the initial structure 100 is formed, a first isolation structure 120 is formed in the first area A1 of the substrate 10, and a second isolation structure 220 is formed in the second area A2 of the substrate 10. The critical dimension of the second isolation structure 220 is greater than the critical dimension of the first isolation structure 120, and the graphic density of the first isolation structure 120 in the first area A1 is greater than the graphic density of the second isolation structure 220 in the second area A2.

[0090] Reference Figure 4 , Figure 5In the process of forming the first isolation structure 120 and the second isolation structure 220, the isolation layer 21 on the hard mask layer 30 is removed by grinding. Affected by the critical dimensions and graphic density of the first isolation structure 120 and the second isolation structure 220, the grinding rate of the first isolation structure 120 in the first area A1 is greater than the grinding rate of the second isolation structure 220 in the second area A2. After the grinding stops, the height of the top surface of the first isolation structure 120 is lower than the height of the top surface of the second isolation structure 220 in the second area A2, and the depth of the depression of the top surface of the first isolation structure 120 is greater than the depth of the depression of the top surface of the second isolation structure 220.

[0091] Reference Figure 7 After the protective layer 40 is formed, the protective layer 40 covers the top surface of the first isolation structure 120 and fills the concave area on the top surface of the first isolation structure 120. The protective layer 40 also covers the top surface of the second isolation structure 220 and fills the concave area on the top surface of the second isolation structure 220. The top surface height of the protective layer 40 on the first isolation structure 120 is flush with the top surface height of the protective layer 40 on the top surface of the second isolation structure 220, eliminating the height of the first isolation structure 120 and the second isolation structure 220. The problem of different step heights between the isolation structure 20 and the active area 11 in the first area A1 and the second area A2 is avoided, and the situation in which the step height difference of the isolation structure 20 in different pattern density areas affects the performance of the semiconductor structure is avoided.

[0092] In some embodiments, an oxide layer 103 is formed on the top surface of the substrate 10 of the initial structure 100; after the hard mask layer 30 is etched and removed, the oxide layer 103 is etched and removed. In the step of etching the oxide layer 103, the etching rate of the first area A1 may be greater than the etching rate of the second area A2, resulting in that after the oxide layer 103 is etched and removed, the top surface of the substrate 10 in the first area A1 is lower than the top surface of the substrate 10 in the second area A2. In this embodiment, when the epitaxial layer 60 is formed by epitaxy, the duration of the epitaxial production is controlled so that the top surface of the epitaxial layer 60 is higher than the top surface of the protective layer 40, and then the epitaxial layer 60 is ground to grind the top surface of the epitaxial layer 60 to be flush with the top surface of the protective layer 40, so as to avoid the problem of different step heights between the isolation structure 20 and the active area 11 in the first area A1 and the second area A2, and ensure that the step heights between the isolation structure 20 in the first area A1 and the isolation structure 20 in the second area A2 and the top surface of the active area 11 are zero.

[0093] According to an exemplary embodiment, the present disclosure provides a semiconductor structure, referring to Fig.11As shown, the semiconductor structure includes a substrate 10, an isolation structure 20, a protective layer 40 and an epitaxial layer 60; the isolation structure 20 is arranged in the substrate 10, and the substrate 10 is divided into active areas 11 arranged at intervals, and the top surface of the isolation structure 20 has a concave area; the protective layer 40 covers the top surface of the isolation structure 20 and fills the concave area of ​​the isolation structure 20; the epitaxial layer 60 is arranged on the top surface of the substrate 10, and the substrate 10 between the epitaxial layer 60 and the isolation structure 20 serves as the active area 11, and the top surface of the active area 11 is flush with the top surface of the protective layer 40. The semiconductor structure of this embodiment uses the protective layer 40 on the isolation structure 20 and the epitaxial layer 60 of the active area 11 to adjust the step height between the isolation structure 20 and the active area 11, so that the top surface of the active area 11 is flush with the top surface of the isolation structure 20, thereby adjusting the height of the active area 11, eliminating the step height between the isolation structure 20 and the active area 11, and is conducive to improving the performance of the semiconductor structure.

[0094] In some embodiments, reference Fig.11 As shown, the material of the epitaxial layer 60 includes semiconductor material, and the lattice direction of the epitaxial layer 60 is the same as the crystal direction of the substrate 10. The epitaxial layer 60 and the substrate 10 between the isolation structure 20 serve as an active region 11, and the active region 11 is used to form a semiconductor device.

[0095] The material of the epitaxial layer 60 can be the same semiconductor material as the substrate 10, or can be different from the substrate 10 according to the device manufacturing requirements. For example, the material composition, conductivity type, and resistivity of the epitaxial layer 60 are different from those of the substrate 10.

[0096] In one example, referring to Fig.11 As shown, the epitaxial layer 60 is made of the same material as the substrate 10. The substrate 10 is a silicon substrate, and the epitaxial layer 60 is made of single crystal silicon. This helps to reduce the lattice mismatch at the contact interface between the epitaxial layer 60 and the substrate 10, and improve the quality of the epitaxial layer 60 and the performance of the device.

[0097] In another example, the epitaxial layer 60 is made of a different material from the substrate 10. The substrate 10 is a silicon substrate, and the epitaxial layer 60 is made of silicon germanium. In this example, it can be applied to manufacturing a PMOS device, epitaxial silicon germanium is formed to form the epitaxial layer 60, and the epitaxial layer 60 serves as the source and / or drain of the PMOS, thereby improving the stress of the PMOS and improving the device performance.

[0098] In some embodiments, reference Fig.11 As shown, the material of the protection layer 40 includes at least one of silicon oxycarbide, silicon carbonitride or silicon oxynitride.

[0099] In some embodiments, reference Fig.11As shown, the semiconductor structure further includes a pad oxide layer 70 , and the pad oxide layer 70 at least covers the top surface of the active region 11 .

[0100] In some embodiments, reference Fig.11 As shown, the substrate 10 includes a first area A1 and a second area A2. The isolation structure 20 in the first area A1 and the isolation structure 20 in the second area A2 have different sizes. The top surfaces of the first area A1 and the second area A2 are flush.

[0101] In some embodiments, reference Fig.11 As shown, the critical dimension of the second isolation structure 220 is greater than the critical dimension of the first isolation structure 120, and the pattern density of the first isolation structure 120 in the first area A1 is greater than the pattern density of the second isolation structure 220 in the second area A2. The height of the top surface of the first isolation structure 120 is lower than the height of the top surface of the second isolation structure 220 in the second area A2, and the depth of the depression of the top surface of the first isolation structure 120 is greater than the depth of the depression of the top surface of the second isolation structure 220. The top surface height of the protective layer 40 on the first isolation structure 120 is flush with the top surface height of the protective layer 40 on the top surface of the second isolation structure 220, eliminating the height difference between the first isolation structure 120 and the second isolation structure 220. The problem of different step heights between the isolation structure 20 and the active area 11 in the first area A1 and the second area A2 is avoided, and the situation in which the step height difference of the isolation structure 20 in different pattern density areas affects the performance of the semiconductor structure is avoided.

[0102] The semiconductor structure of this embodiment can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM) or other types of memory.

[0103] In some embodiments, an electronic device is provided, including the semiconductor structure of the above embodiment or the semiconductor structure manufactured by the method for manufacturing the semiconductor structure of the above embodiment. The electronic device may be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0104] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing an initial structure, the initial structure comprising a substrate and an isolation structure formed in the substrate, the top surface of the substrate being covered by a hard mask layer, the top surface of the isolation structure being higher than the top surface of the substrate, and the top surface of the isolation structure being recessed relative to the hard mask layer; forming a protective layer to cover the top surface of the isolation structure and fill the recessed area of ​​the isolation structure; Etching and removing the hard mask layer to expose the top surface of the substrate; An epitaxial layer is epitaxially formed on the top surface of the substrate, the epitaxial layer is used as an active region, and the top surface of the active region is flush with the top surface of the protective layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming a protection layer to cover the top surface of the isolation structure and fill the recessed area of ​​the isolation structure, comprising: forming a protective material layer, wherein the protective material layer covers a top surface of the isolation structure, a top surface of the hard mask layer, and fills a recess at the top of the isolation structure; The protective material layer is ground to expose the top surface of the hard mask layer, and the protective material layer at the recessed portion of the top of the isolation structure is ground to remain to form the protective layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The material of the protective layer includes at least one of silicon oxycarbide, silicon carbonitride or silicon oxynitride.

4. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: An oxide layer is formed on the top surface of the substrate, and the oxide layer is arranged between the substrate and the hard mask layer; After the hard mask layer is removed by etching, the oxide layer is removed by etching to expose the top surface of the substrate.

5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: Provide an initial structure, including: Providing an initial substrate, forming the hard mask layer on a top surface of the initial substrate, wherein the hard mask layer defines a pattern of the isolation structure; Etching the initial substrate according to the hard mask layer to form an isolation trench in the initial substrate, and etching the remaining initial substrate to form the substrate; forming an isolation layer, wherein the isolation layer fills the isolation trench and covers a top surface of the hard mask layer; The isolation layer on the hard mask layer is removed by grinding, and the isolation layer remaining in the isolation trench forms the isolation structure.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The production method further comprises: A pad oxide layer is formed, wherein the pad oxide layer at least covers a top surface of the active region.

7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The substrate comprises a first region and a second region, wherein the isolation structure in the first region has a different size from the isolation structure in the second region; After the epitaxial layer is formed by epitaxial growth, the top surfaces of the first region and the second region are flush.

8. A semiconductor structure, characterized in that: include: substrate; An isolation structure is arranged in the substrate to divide the substrate into active areas arranged at intervals, and a top surface of the isolation structure has a concave area; A protective layer, covering the top surface of the isolation structure and filling a recessed area of ​​the isolation structure; An epitaxial layer is arranged on the top surface of the substrate, the epitaxial layer and the substrate between the isolation structure serve together as the active area, and the top surface of the active area is flush with the top surface of the protective layer.

9. The semiconductor structure according to claim 8, characterized in that: The material of the protective layer includes at least one of silicon oxycarbide, silicon carbonitride or silicon oxynitride.

10. The semiconductor structure according to claim 8, characterized in that The substrate includes a first region and a second region. The isolation structure in the first region has a different size from the isolation structure in the second region. The top surfaces of the first region and the second region are flush.

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