A zero-crossing detection circuit and a zero-crossing detection method for a DC-DC converter

Abstract

The present invention discloses a zero-crossing detection circuit and a zero-crossing detection method for a DC-DC converter, the circuit comprising a zero-crossing detection comparison circuit, a sampling and holding and level shifting circuit, and a voltage difference quantization integration circuit; the zero-crossing detection comparison circuit determines whether the inductor current is zero-crossing by comparing the inductor voltage and the power supply ground and outputs a zero-crossing detection signal, the sampling and holding and level shifting circuit generates a short clock pulse for sampling the inductor voltage according to the zero-crossing detection, and performs level shifting on the inductor voltage and the power supply ground; the voltage difference quantization integration circuit uses the inductor voltage and the power supply ground after the level shifting to charge or discharge the third capacitor, and the obtained capacitor voltage is fed back to the zero-crossing detection comparison circuit to control the speed of the zero-crossing detection comparison in the next cycle. The present invention uses a feedback loop to control the gate-controlled resistor size in the zero-crossing detection comparison circuit to change the current and thus correct the position of the zero-crossing voltage, so as to achieve the purpose of correcting the premature or late closure of the zero-crossing detection.

Description

Technical Field

[0001] The invention relates to zero-crossing detection, in particular to a zero-crossing detection circuit and a zero-crossing detection method of a DC-DC converter. Background Art

[0002] The inductor-based DC-DC converter uses the energy storage characteristics of the inductor to perform high-frequency switching through a controllable switch (MOSFET, etc.) to store the input electrical energy in the inductor. When the switch is disconnected, the electrical energy is released to the load to provide energy. It needs to work in a high-efficiency and low-power mode to transmit energy. The DC-DC converter used in energy harvesting generally has a low load current and usually works in the discontinuous conduction mode DCM. In this mode, a zero-crossing detection circuit is required during the discharge period to detect whether the inductor current is discharged to zero, and then disconnect the rectifier tube to prevent reverse leakage. At the same time, due to the wide power range of the input energy in the environment, it is necessary to adjust the inductor discharge time over a wide range, which is of great significance for improving conversion efficiency.

[0003] Commonly used zero-crossing detection is divided into two implementation methods: analog and digital. Digital zero-crossing detection includes a dynamic comparator and a counter that controls the change of pulse width. Although it can achieve ultra-low power consumption, it can only change the fixed step of pulse width according to the comparison result. The adjustment range is not large, and the adjustment speed is slow. It needs to be adjusted to the precise zero-crossing point multiple times. In this way, each adjustment will lose some energy, resulting in a decrease in system efficiency. The zero-crossing comparator implemented in analog mode can accurately compare the zero-crossing point, but the comparator needs to achieve high precision at the cost of power consumption. Due to the offset of the comparator and the large deviation of the comparator with the process in the open-loop situation, there will still be errors in the zero-crossing point. If a circuit with offset correction is added, such as a chopper circuit to compensate for the offset voltage of the comparator, it will have a positive impact on the accuracy of the comparator, but the introduction of the adjustment circuit will increase the power consumption a lot and increase the design complexity of the circuit. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide a zero-crossing detection circuit and a zero-crossing detection method for a DC-DC converter, especially zero-crossing detection for a DC-DC converter based on inductance, which uses a feedback loop to control the size of a gate-controlled resistor in a zero-crossing detection comparison circuit to change the current and thereby correct the position of the zero-crossing voltage, thereby achieving the purpose of correcting the premature or late shutdown of the zero-crossing detection, solving the problems of small adjustable range and slow speed of existing digital trimming, and avoiding the complexity brought about by designing an offset calibration circuit for the comparator.

[0005] Technical solution: The zero-crossing detection circuit of the DC-DC converter of the present invention comprises a zero-crossing detection comparison circuit, a sampling and holding and level shifting circuit, and a voltage difference quantization integration circuit;

[0006] The zero-crossing detection comparison circuit is connected to the inductor voltage of the DC-DC converter, determines whether the inductor current crosses zero by comparing the inductor voltage and the power supply ground, and outputs a zero-crossing detection signal ZCD_OUT;

[0007] The sampling, holding and level shifting circuit generates a short clock pulse according to the zero-crossing detection signal ZCD_OUT for sampling the inductor voltage and the power ground, and performs level shifting on the inductor voltage and the power ground;

[0008] The voltage difference quantization integration circuit uses the level-shifted inductor voltage and the ground potential to charge or discharge the third capacitor C3, and the obtained capacitor voltage is fed back to the zero-crossing detection comparison circuit to control the size of the gate-controlled resistor, thereby controlling the speed of the zero-crossing detection comparison in the next cycle; the gate-controlled resistor is the equivalent resistance of the circuit controlled by the capacitor voltage.

[0009] Furthermore, the DC-DC converter operates in a discontinuous conduction mode, and when the first group of switch tubes is closed, the inductor is charged; when the second group of switch tubes is closed, the inductor is discharged.

[0010] Furthermore, in the inductor discharge stage of the DC-DC converter, the inductor voltage and the power ground are compared. When the inductor voltage is greater than the power ground, a zero-crossing detection signal ZCD_OUT is output, and the DC-DC converter controls the switch tube to disconnect to complete the inductor discharge, thereby ending the zero-crossing detection of this cycle.

[0011] Furthermore, when the switch tube is closed too late, the inductor voltage increases, C3 in the voltage difference quantization integration circuit discharges, the capacitor voltage decreases, the gate control resistor value increases, and the zero-crossing detection comparison speed in the next cycle is accelerated;

[0012] When the switch tube is closed too early, the inductor voltage drops, C3 in the voltage difference quantization integration circuit is charged, the capacitor voltage increases, the gate-controlled resistor value decreases, and the zero-crossing detection comparison speed in the next cycle slows down.

[0013] Further, the zero-crossing detection comparison circuit includes a first P-type field effect transistor M1, a second P-type field effect transistor M2, a third P-type field effect transistor M3, a fourth P-type field effect transistor M4, a fifth P-type field effect transistor M5, a sixth N-type field effect transistor M6, a seventh N-type field effect transistor M7, an eighth N-type field effect transistor M8, a ninth N-type field effect transistor M9, a tenth N-type field effect transistor M10, an eleventh N-type field effect transistor M11, a twelfth P-type field effect transistor M12, and a first inverter A1, a second inverter A2, and a third inverter A3;

[0014] Wherein, the gate end of M1 is connected to the external input signal EN, the source end of M1 is connected to the power supply voltage VDD, and the drain end of M1 is connected to the drain end of M2 and the external reference current;

[0015] The gate terminal of M2 is connected to the gate terminal of M3 and the drain terminal of M2, and the source terminal of M2 is connected to the power supply voltage VDD;

[0016] The gate terminal of M3 is connected to the gate terminal of M2, the source terminal of M3 is connected to the power supply voltage VDD, and the drain terminal of M3 is connected to the drain terminal of M7;

[0017] The gate terminal of M4 is connected to the gate terminal of M5, the source terminal of M4 is connected to the power supply voltage VDD, and the drain terminal of M4 is connected to the drain terminal of M6;

[0018] The gate terminal of M5 is connected to the gate terminal of M4, the source terminal of M4 is connected to the power supply voltage VDD, the drain terminal of M4 is connected to the drain terminal of M10, and is also connected to the input of the inverter A1;

[0019] The gate terminal of M6 is connected to the gate terminal of M7, the source terminal of M6 is connected to the drain terminal of M8, and the drain terminal of M6 is connected to the drain terminal of M4;

[0020] The gate terminal of M7 is connected to the gate terminal of M6 and the drain terminal of M7, and the source terminal of M7 is connected to the drain terminal of M9;

[0021] The gate terminal of M8 is connected to the capacitor voltage, the source terminal of M8 is connected to the power ground GND, and the drain terminal of M8 is connected to the source terminal of M6;

[0022] The gate terminal of M9 is connected to the capacitor voltage, the source terminal of M9 is connected to the inductor voltage, and the drain terminal of M9 is connected to the source terminal of M7;

[0023] The gate end of M10 is connected to the gate end of M11, the source end of M10 is connected to the drain end of M9, and the drain end of M10 is connected to the drain end of M5;

[0024] The gate end of M11 is connected to the gate end of M10 and the drain end of M11, the source end of M11 is connected to the drain end of M8, and the drain end of M11 is connected to the drain end of M12;

[0025] The input end of A1 is connected to the drain end of M5, and the output end of A1 is connected to the input end of A2;

[0026] The input end of A2 is connected to the output end of A1, the output end of A2 is connected to the input end of A3, and the output end of A2 is the zero-crossing detection signal ZCD_OUT;

[0027] The input end of A3 is connected to the output end of A2, and the output end of A3 is connected to the sampling, holding and level shifting circuit.

[0028] Further, the sampling and holding and level shifting circuit includes a sampling and holding circuit, a thirteenth P-type field effect transistor M13, a fourteenth P-type field effect transistor M14, a fifteenth P-type field effect transistor M15, a sixteenth P-type field effect transistor M16, a seventeenth P-type field effect transistor M17, an eighteenth P-type field effect transistor M18, a nineteenth P-type field effect transistor M19, a twentieth P-type field effect transistor M20, a first capacitor C1 and a second capacitor C2;

[0029] Wherein, the gate end of M13 is connected to the gate end of M12, the source end of M13 is connected to the power supply voltage VDD, and the drain end of M13 is connected to the source end of M15;

[0030] The gate terminal of M14 is connected to the gate terminal of M13, the source terminal of M14 is connected to the power supply voltage VDD, and the drain terminal of M14 is connected to the source terminal of M16;

[0031] The gate end of M15 is connected to the gate end of M16, the source end of M15 is connected to the drain end of M13, and the drain end of M15 is connected to the source end of M17; the drain end output of M15 is the inductor voltage after level shifting;

[0032] The gate end of M16 is connected to the output end of the third inverter A3, the source end of M16 is connected to the drain end of M14, and the drain end of M16 is connected to the source end of M18; the drain end output of M16 is the power ground after level shifting;

[0033] The gate end of M17 is connected to the gate end of M18, the source end of M17 is connected to the drain end of M15, and the drain end of M17 is connected to the source end of M19;

[0034] The gate terminal of M18 is connected to the output terminal of the third inverter A3, the source terminal of M18 is connected to the drain terminal of M16, and the drain terminal of M18 is connected to the source terminal of M20;

[0035] The gate end of M19 is connected to the output end of the sample and hold circuit, the source end of M19 is connected to the drain end of M17, and the drain end of M19 is connected to the power ground GND;

[0036] The gate terminal of M20 is connected to the power ground GND, the source terminal of M20 is connected to the drain terminal of M18, and the drain terminal of M20 is connected to the power ground GND;

[0037] The upper plate of C1 is connected to the drain of M15, and the lower plate of C1 is connected to the power ground GND;

[0038] The upper plate of C2 is connected to the drain of M16, and the lower plate of C2 is connected to the power ground GND;

[0039] An input terminal of the sample and hold circuit is connected to the output terminal of the second inverter A2, the inductor voltage and the power ground.

[0040] Further, the voltage difference quantization integration circuit includes a twenty-first P-type field effect transistor M21, a twenty-second P-type field effect transistor M22, a twenty-third P-type field effect transistor M23, a twenty-fourth N-type field effect transistor M24, a twenty-fifth N-type field effect transistor M25, a twenty-sixth N-type field effect transistor M26, a twenty-seventh N-type field effect transistor M27, a twenty-eighth P-type field effect transistor M28, a twenty-ninth P-type field effect transistor M29 and a third capacitor C3;

[0041] Wherein, the gate terminal of M21 is connected to the gate terminal of M14, the source terminal of M21 is connected to the power supply voltage VDD, and the drain terminal of M21 is connected to the source terminal of M22;

[0042] The gate terminal of M22 is connected to the level-shifted inductor voltage, the source terminal of M22 is connected to the drain terminal of M21, and the drain terminal of M22 is connected to the drain terminal of M24;

[0043] The gate terminal of M23 is connected to the power ground after level shifting, the source terminal of M23 is connected to the drain terminal of M21, and the drain terminal of M23 is connected to the drain terminal of M25;

[0044] The gate terminal of M24 is connected to the gate terminal of M26 and the drain terminal of M24, and the source terminal of M24 is connected to the power ground GND;

[0045] The gate end of M25 is connected to the gate end of M27 and the drain end of M25, and the source end of M25 is connected to the power ground GND;

[0046] The gate end of M26 is connected to the gate end of M24, the source end of M26 is connected to the power ground GND, and the drain end of M26 is connected to the drain end of M28;

[0047] The gate end of M27 is connected to the gate end of M25, the source end of M27 is connected to the power ground GND, and the drain end of M27 is connected to the drain end of M29;

[0048] The gate terminal of M28 is connected to the gate terminal of M29 and the drain terminal of M28, and the source terminal of M28 is connected to the power supply voltage VDD;

[0049] The gate terminal of M29 is connected to the gate terminal of M28, the source terminal of M29 is connected to the power supply voltage VDD, and the drain terminal of M29 is connected to the drain terminal of M27;

[0050] The upper plate of C3 is connected to the drain terminal of M27, and the lower plate of C3 is connected to the power ground GND; the voltage of the upper plate of C3 is the capacitor voltage.

[0051] The zero-crossing detection method of the DC-DC converter of the present invention comprises the following steps:

[0052] The inductor voltage of the DC-DC converter is input to the zero-crossing detection comparison circuit in the zero-crossing detection circuit, and the zero-crossing detection comparison circuit determines whether the inductor current crosses zero by comparing the inductor voltage and the power supply ground and outputs a zero-crossing detection signal ZCD_OUT;

[0053] The sampling, holding and level shifting circuit in the zero-crossing detection circuit generates a short clock pulse according to the zero-crossing detection signal ZCD_OUT for sampling the inductor voltage and the power ground, and performs level shifting on the inductor voltage and the power ground;

[0054] The voltage difference quantization integration circuit in the zero-crossing detection circuit uses the level-shifted inductor voltage and the power ground to charge or discharge the third capacitor C3, and the obtained capacitor voltage is fed back to the zero-crossing detection comparison circuit to control the size of the gate-controlled resistor, thereby controlling the speed of the zero-crossing detection comparison in the next cycle; the gate-controlled resistor is the equivalent resistance of the circuit controlled by the capacitor voltage.

[0055] The DC-DC converter of the present invention utilizes the zero-crossing detection circuit to perform zero-crossing detection on the DC-DC converter.

[0056] The terminal equipment described in the present invention includes the zero-crossing detection circuit of the DC-DC converter described above.

[0057] Beneficial effects: Compared with the prior art, the advantages of the present invention are: (1) The present invention changes the current by introducing a feedback loop to control the gate-controlled resistor size in the zero-crossing detection comparison circuit, thereby correcting the position of the zero-crossing voltage, thereby achieving the purpose of correcting the premature or late closing of the zero-crossing detection, and solving the problem of small adjustable range and slow speed of the existing digital adjustment. (2) Since the existence of the comparator offset voltage will cause a certain deviation in the zero-crossing point, a chopper circuit will be added to adjust the offset voltage of the comparator, which requires the introduction of an external clock and increases the complexity of the circuit. However, the present invention adopts the idea of ​​voltage difference quantization and does not involve external clock adjustment, thus avoiding increasing the complexity of circuit design. (3) The overall zero-crossing detection circuit of the present invention consumes 4.5nA. At a power supply voltage of 0.8V, the overall power consumption is 3.84nW. Compared with other structures that change the bias current by detecting the zero-crossing point, the current only increases at the moment of flipping, while the static current does not increase. It is suitable for ultra-low power consumption IoT sensor device application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is the overall principle block diagram of the present invention.

[0059] Figure 2 It is a zero-crossing detection circuit diagram of the present invention.

[0060] Figure 3 1 is a key waveform analysis diagram of the zero-crossing detection circuit in an embodiment of the present invention.

[0061] Figure 4 This is a simulation diagram of the correction result of premature shutdown of the zero-crossing detection circuit in an embodiment of the present invention.

[0062] Figure 5 This is a simulation diagram of the correction result of the zero-crossing detection circuit being closed too late in an embodiment of the present invention. DETAILED DESCRIPTION

[0063] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0064] For an inductor-based DC-DC converter, this embodiment takes BUCK-BOOST as an example to illustrate the zero-crossing detection circuit of the present invention. Figure 1 Shown is the overall principle block diagram of this embodiment.

[0065] When operating in discontinuous conduction mode (DCM), when switches S1 and S4 are closed and S2 and S3 are open, the inductor is charged; when S2 and S3 are closed and S1 and S4 are open, the inductor discharges the load. During the discharge period, the inductor current under light load will be negative to satisfy the average value of the inductor current equal to the load current. If S2 and S3 are not disconnected in time, the current will flow back to the ground through the inductor, which will generate additional power consumption and reduce the overall efficiency. This situation needs to be avoided during the design, so a zero-crossing detection circuit is added to detect whether the inductor current is discharged to zero during the discharge period to turn off the switch tube. The implementation method is to compare the potential VLX at the left end of the inductor and the power ground during the discharge period. When VLX is greater than the power ground, the ZCD_OUT signal is generated and given to the logic and drive module, and the switch tubes S2 and S3 are disconnected, waiting for the next cycle to close the switch tubes S1 and S4 again.

[0066] The zero-crossing detection circuit includes a zero-crossing detection comparison circuit, a sampling and holding and level shifting circuit, and a voltage difference quantization integration circuit. In the discharge stage of the DC-DC converter inductor, the voltage VLX at the left end of the inductor and the power ground are compared. After zero crossing, a ZCD_OUT signal is generated to enable the sampling and holding circuit to sample the two voltages of VLX and the power ground. Since the potential of VLX is less than 0 in the discharge stage, it is difficult for the negative voltage to make the MOS tube in the voltage difference quantization integration circuit work normally. Therefore, the ZCD_OUT signal is used to enable the level shifting circuit to raise the level of the two sampled levels through the source follower of the PMOS input to obtain VLX_LS and VGND_LS, and store them on capacitors C1 and C2. The voltage after level shifting is then converted into current through the voltage difference quantization integrator to charge or discharge the capacitor C3. The obtained voltage VG is then fed back to the zero-crossing detection comparison circuit to change the size of the gate-controlled resistor R, thereby changing the comparison speed of ZCD_OUT in the next cycle.

[0067] Among them, since the MOS tube working in the linear region can be used as a resistor, according to the current formula of the MOS tube in the linear region, the voltage at the gate end of the MOS tube can be changed to obtain resistors of different resistance values. The gate-controlled resistor R is an equivalent resistor controlled by the voltage VG. The source follower is an amplifier structure with a gate input, a source output, and a shared drain. The source follower with a PMOS tube input can raise the voltage at the gate input by a threshold voltage VTH.

[0068] like Figure 2 The zero-crossing detection circuit diagram of the present invention is shown below. Figure 2 The zero-crossing detection comparison circuit, sampling and holding and level shifting circuit, and voltage difference quantization integration circuit are introduced in detail. Figure 2 M19, M13, M15, and M17 constitute a group of source followers, and M20, M14, M16, and M18 constitute a group of source followers.

[0069] (1) Zero-crossing detection comparison circuit

[0070] The zero-crossing detection comparison circuit includes a first P-type field effect transistor M1, a second P-type field effect transistor M2, a third P-type field effect transistor M3, a fourth P-type field effect transistor M4, a fifth P-type field effect transistor M5, a sixth N-type field effect transistor M6, a seventh N-type field effect transistor M7, an eighth N-type field effect transistor M8, a ninth N-type field effect transistor M9, a tenth N-type field effect transistor M10, an eleventh N-type field effect transistor M11, a twelfth P-type field effect transistor M12, and a first inverter A1, a second inverter A2, and a third inverter A3.

[0071] Wherein, the gate end of M1 is connected to the external input signal EN, the source end of M1 is connected to the power supply voltage VDD, and the drain end of M1 is connected to the drain end of M2 and the external reference current IREF; the external input signal EN is an enable signal for the overall zero-crossing detection circuit to start working; the external reference current IREF is used to provide current to the entire circuit;

[0072] The gate terminal of M2 is connected to the gate terminal of M3 and the drain terminal of M2, and the source terminal of M2 is connected to the power supply voltage VDD;

[0073] The gate terminal of M3 is connected to the gate terminal of M2, the source terminal of M3 is connected to the power supply voltage VDD, and the drain terminal of M3 is connected to the drain terminal of M7;

[0074] The gate terminal of M4 is connected to the gate terminal of M5, the source terminal of M4 is connected to the power supply voltage VDD, and the drain terminal of M4 is connected to the drain terminal of M6;

[0075] The gate terminal of M5 is connected to the gate terminal of M4, the source terminal of M4 is connected to the power supply voltage VDD, the drain terminal of M4 is connected to the drain terminal of M10, and is also connected to the input of the inverter A1;

[0076] The gate terminal of M6 is connected to the gate terminal of M7, the source terminal of M6 is connected to the drain terminal of M8, and the drain terminal of M6 is connected to the drain terminal of M4;

[0077] The gate terminal of M7 is connected to the gate terminal of M6 and the drain terminal of M7, and the source terminal of M7 is connected to the drain terminal of M9;

[0078] The gate terminal of M8 is connected to the upper feedback voltage VG of the third capacitor C3 in the voltage difference quantization integration circuit, the source terminal of M8 is connected to the power ground GND, and the drain terminal of M8 is connected to the source terminal of M6;

[0079] The gate terminal of M9 is connected to the upper feedback voltage VG of the third capacitor C3 in the voltage difference quantization integration circuit, the source terminal of M9 is connected to the inductor voltage, and the drain terminal of M9 is connected to the source terminal of M7;

[0080] The gate end of M10 is connected to the gate end of M11, the source end of M10 is connected to the drain end of M9, and the drain end of M10 is connected to the drain end of M5;

[0081] The gate end of M11 is connected to the gate end of M10 and the drain end of M11, the source end of M11 is connected to the drain end of M8, and the drain end of M11 is connected to the drain end of M12;

[0082] The input end of A1 is connected to the drain end of M5, and the output end of A1 is connected to the input end of A2;

[0083] The input end of A2 is connected to the output end of A1, the output end of A2 is connected to the input end of A3, the output end of A2 is the zero-crossing detection signal ZCD_OUT, and the output end of A2 is also connected to the sample & hold circuit (sample and hold circuit) in the sample, hold and level shift circuit;

[0084] The input end of A3 is connected to the output end of A2, and the output end of A3 is connected to the sampling, holding and level shifting circuit.

[0085] (2) Sample-hold and level-shift circuit

[0086] The sampling, holding and level shifting circuit includes a sampling and holding circuit, a thirteenth P-type field effect transistor M13, a fourteenth P-type field effect transistor M14, a fifteenth P-type field effect transistor M15, a sixteenth P-type field effect transistor M16, a seventeenth P-type field effect transistor M17, an eighteenth P-type field effect transistor M18, a nineteenth P-type field effect transistor M19, a twentieth P-type field effect transistor M20, a first capacitor C1 and a second capacitor C2.

[0087] Wherein, the gate end of M13 is connected to the gate end of M12, the source end of M13 is connected to the power supply voltage VDD, and the drain end of M13 is connected to the source end of M15;

[0088] The gate terminal of M14 is connected to the gate terminal of M13, the source terminal of M14 is connected to the power supply voltage VDD, and the drain terminal of M14 is connected to the source terminal of M16;

[0089] The gate end of M15 is connected to the gate end of M16, the source end of M15 is connected to the drain end of M13, and the drain end of M15 is connected to the source end of M17;

[0090] The gate terminal of M16 is connected to the output terminal of the third inverter A3, the source terminal of M16 is connected to the drain terminal of M14, and the drain terminal of M16 is connected to the source terminal of M18;

[0091] The gate end of M17 is connected to the gate end of M18, the source end of M17 is connected to the drain end of M15, and the drain end of M17 is connected to the source end of M19;

[0092] The gate terminal of M18 is connected to the output terminal of the third inverter A3, the source terminal of M18 is connected to the drain terminal of M16, and the drain terminal of M18 is connected to the source terminal of M20;

[0093] The gate end of M19 is connected to the output end of the sample and hold circuit, the source end of M19 is connected to the drain end of M17, and the drain end of M19 is connected to the power ground GND;

[0094] The gate terminal of M20 is connected to the power ground GND, the source terminal of M20 is connected to the drain terminal of M18, and the drain terminal of M20 is connected to the power ground GND;

[0095] The upper plate of C1 is connected to the drain of M15, and the lower plate of C1 is connected to the power ground GND;

[0096] The upper plate of C2 is connected to the drain of M16, and the lower plate of C2 is connected to the power ground GND;

[0097] The input end of the sampling and holding circuit is connected to the output end of the second inverter A2, the inductor voltage and the power ground; the sampling and holding circuit includes a clock generating circuit and a sampling and holding circuit. The clock generating circuit generates a short clock pulse required by the sampling and holding circuit to sample the inductor voltage VLX and the power ground GND after the zero-crossing detection circuit signal ZCD becomes a high level.

[0098] (3) Voltage difference quantization integration circuit

[0099] The voltage difference quantization integration circuit includes a twenty-first P-type field effect transistor M21, a twenty-second P-type field effect transistor M22, a twenty-third P-type field effect transistor M23, a twenty-fourth N-type field effect transistor M24, a twenty-fifth N-type field effect transistor M25, a twenty-sixth N-type field effect transistor M26, a twenty-seventh N-type field effect transistor M27, a twenty-eighth P-type field effect transistor M28, a twenty-ninth P-type field effect transistor M29 and a third capacitor C3.

[0100] Wherein, the gate terminal of M21 is connected to the gate terminal of M14, the source terminal of M21 is connected to the power supply voltage VDD, and the drain terminal of M21 is connected to the source terminal of M22;

[0101] The gate end of M22 is connected to the drain end of M15, the source end of M22 is connected to the drain end of M21, and the drain end of M22 is connected to the drain end of M24;

[0102] The gate end of M23 is connected to the drain end of M16, the source end of M23 is connected to the drain end of M21, and the drain end of M23 is connected to the drain end of M25;

[0103] The gate terminal of M24 is connected to the gate terminal of M26 and the drain terminal of M24, and the source terminal of M24 is connected to the power ground GND;

[0104] The gate end of M25 is connected to the gate end of M27 and the drain end of M25, and the source end of M25 is connected to the power ground GND;

[0105] The gate end of M26 is connected to the gate end of M24, the source end of M26 is connected to the power ground GND, and the drain end of M26 is connected to the drain end of M28;

[0106] The gate end of M27 is connected to the gate end of M25, the source end of M27 is connected to the power ground GND, and the drain end of M27 is connected to the drain end of M29;

[0107] The gate terminal of M28 is connected to the gate terminal of M29 and the drain terminal of M28, and the source terminal of M28 is connected to the power supply voltage VDD;

[0108] The gate terminal of M29 is connected to the gate terminal of M28, the source terminal of M29 is connected to the power supply voltage VDD, and the drain terminal of M29 is connected to the drain terminal of M27;

[0109] The upper plate of C3 is connected to the drain terminal of M27, and the lower plate of C3 is connected to the power ground GND; the voltage of the upper plate of C3 is the capacitor voltage.

[0110] like Figure 3 The following is a schematic diagram of the key waveforms of zero-crossing detection when the DC-DC converter is working. The vertical axis represents voltage, and the horizontal axis represents time. VLX is the voltage at the left end of the inductor, and S1 / S4 represents Figure 1Middle switch control signal, high effective, S2 / S3_late and S2 / S3_early represent Figure 1 The control signal of the middle switch tube is turned off early and late, ZCD_OUT represents the zero-crossing detection output signal, VG1 and VG2 represent the voltage waveform of the zero-crossing detection circuit when it is turned off too late and too early, respectively. It can be seen from the figure that the situation when it is turned off too early or too late is obtained. When it is turned off too late, it is hoped that the VG1 voltage will gradually decrease to speed up the comparison speed of the next cycle; when it is turned off too early, it is hoped that the VG2 voltage will gradually increase to slow down the comparison speed of the next cycle.

[0111] like Figure 4 , Figure 5 As shown in the figure, based on the 180nm CMOS process platform and verified by Cadence software simulation, when the power supply voltage is 0.8V, the temperature is 27℃ and the process angle is TT, the simulation diagram of the zero-crossing detection output shows that when it is closed too early, the ZCD output of the previous cycle is compared in advance by 14us. At this time, the VG voltage is 650mV. After the feedback loop, the VG voltage in the next cycle increases to 664mV, and the output flip is reduced to 5.6us; when it is closed too late, the ZCD output of the previous cycle lags by 14.5us. At this time, the VG voltage is 649mV. After the feedback loop, the VG voltage in the next cycle is reduced to 639mV, and the output flip is reduced to 5us.

Claims

1. A zero-crossing detection circuit for a DC-DC converter, characterized in that: It includes a zero-crossing detection comparison circuit, a sampling and holding and level shifting circuit, and a voltage difference quantization integration circuit; The zero-crossing detection comparison circuit is connected to the inductor voltage of the DC-DC converter, and determines whether the inductor current crosses zero by comparing the inductor voltage and the power supply ground, and outputs a zero-crossing detection signal ZCD_OUT; The sampling, holding and level shifting circuit generates a short clock pulse according to the zero-crossing detection signal ZCD_OUT for sampling the inductor voltage and the power ground, and performs level shifting on the inductor voltage and the power ground; The voltage difference quantization integration circuit uses the level-shifted inductor voltage and the ground potential to charge or discharge the third capacitor C3, and the obtained capacitor voltage is fed back to the zero-crossing detection comparison circuit to control the size of the gate-controlled resistor, thereby controlling the speed of the zero-crossing detection comparison in the next cycle; the gate-controlled resistor is the equivalent resistance of the circuit controlled by the capacitor voltage; The DC-DC converter operates in a discontinuous conduction mode, and when the first set of switch tubes is closed, the inductor is charged; when the second set of switch tubes is closed, the inductor is discharged; In the inductor discharge stage of the DC-DC converter, the inductor voltage is compared with the power ground. When the inductor voltage is greater than the power ground, a zero-crossing detection signal ZCD_OUT is output. The DC-DC converter controls the switch tube to disconnect to complete the inductor discharge and end the zero-crossing detection of this cycle. When the switch is closed too late, the inductor voltage increases, C3 in the voltage difference quantization integration circuit discharges, the capacitor voltage decreases, the gate control resistor value increases, and the zero-crossing detection comparison speed in the next cycle is accelerated; When the switch tube is closed too early, the inductor voltage drops, C3 in the voltage difference quantization integration circuit is charged, the capacitor voltage increases, the gate-controlled resistor value decreases, and the zero-crossing detection comparison speed in the next cycle slows down.

2. The zero-crossing detection circuit of the DC-DC converter according to claim 1, characterized in that: The zero-crossing detection comparison circuit includes a first P-type field effect transistor M1, a second P-type field effect transistor M2, a third P-type field effect transistor M3, a fourth P-type field effect transistor M4, a fifth P-type field effect transistor M5, a sixth N-type field effect transistor M6, a seventh N-type field effect transistor M7, an eighth N-type field effect transistor M8, a ninth N-type field effect transistor M9, a tenth N-type field effect transistor M10, an eleventh N-type field effect transistor M11, a twelfth P-type field effect transistor M12, and a first inverter A1, a second inverter A2, and a third inverter A3; Wherein, the gate end of M1 is connected to the external input signal EN, the source end of M1 is connected to the power supply voltage VDD, and the drain end of M1 is connected to the drain end of M2 and the external reference current; The gate terminal of M2 is connected to the gate terminal of M3 and the drain terminal of M2, and the source terminal of M2 is connected to the power supply voltage VDD; The gate terminal of M3 is connected to the gate terminal of M2, the source terminal of M3 is connected to the power supply voltage VDD, and the drain terminal of M3 is connected to the drain terminal of M7; The gate terminal of M4 is connected to the gate terminal of M5, the source terminal of M4 is connected to the power supply voltage VDD, and the drain terminal of M4 is connected to the drain terminal of M6; The gate terminal of M5 is connected to the gate terminal of M4, the source terminal of M4 is connected to the power supply voltage VDD, the drain terminal of M4 is connected to the drain terminal of M10, and is also connected to the input of the inverter A1; The gate terminal of M6 is connected to the gate terminal of M7, the source terminal of M6 is connected to the drain terminal of M8, and the drain terminal of M6 is connected to the drain terminal of M4; The gate terminal of M7 is connected to the gate terminal of M6 and the drain terminal of M7, and the source terminal of M7 is connected to the drain terminal of M9; The gate terminal of M8 is connected to the capacitor voltage, the source terminal of M8 is connected to the power ground GND, and the drain terminal of M8 is connected to the source terminal of M6; The gate terminal of M9 is connected to the capacitor voltage, the source terminal of M9 is connected to the inductor voltage, and the drain terminal of M9 is connected to the source terminal of M7; The gate end of M10 is connected to the gate end of M11, the source end of M10 is connected to the drain end of M9, and the drain end of M10 is connected to the drain end of M5; The gate end of M11 is connected to the gate end of M10 and the drain end of M11, the source end of M11 is connected to the drain end of M8, and the drain end of M11 is connected to the drain end of M12; The input end of A1 is connected to the drain end of M5, and the output end of A1 is connected to the input end of A2; The input end of A2 is connected to the output end of A1, the output end of A2 is connected to the input end of A3, and the output end of A2 is the zero-crossing detection signal ZCD_OUT; The input end of A3 is connected to the output end of A2, and the output end of A3 is connected to the sampling, holding and level shifting circuit.

3. The zero-crossing detection circuit of the DC-DC converter according to claim 2, characterized in that: The sampling and holding and level shifting circuit includes a sampling and holding circuit, a thirteenth P-type field effect transistor M13, a fourteenth P-type field effect transistor M14, a fifteenth P-type field effect transistor M15, a sixteenth P-type field effect transistor M16, a seventeenth P-type field effect transistor M17, an eighteenth P-type field effect transistor M18, a nineteenth P-type field effect transistor M19, a twentieth P-type field effect transistor M20, a first capacitor C1 and a second capacitor C2; Wherein, the gate end of M13 is connected to the gate end of M12, the source end of M13 is connected to the power supply voltage VDD, and the drain end of M13 is connected to the source end of M15; The gate terminal of M14 is connected to the gate terminal of M13, the source terminal of M14 is connected to the power supply voltage VDD, and the drain terminal of M14 is connected to the source terminal of M16; The gate end of M15 is connected to the gate end of M16, the source end of M15 is connected to the drain end of M13, and the drain end of M15 is connected to the source end of M17; the drain end output of M15 is the inductor voltage after level shifting; The gate end of M16 is connected to the output end of the third inverter A3, the source end of M16 is connected to the drain end of M14, and the drain end of M16 is connected to the source end of M18; the drain end output of M16 is the power ground after level shifting; The gate end of M17 is connected to the gate end of M18, the source end of M17 is connected to the drain end of M15, and the drain end of M17 is connected to the source end of M19; The gate terminal of M18 is connected to the output terminal of the third inverter A3, the source terminal of M18 is connected to the drain terminal of M16, and the drain terminal of M18 is connected to the source terminal of M20; The gate end of M19 is connected to the output end of the sample and hold circuit, the source end of M19 is connected to the drain end of M17, and the drain end of M19 is connected to the power ground GND; The gate terminal of M20 is connected to the power ground GND, the source terminal of M20 is connected to the drain terminal of M18, and the drain terminal of M20 is connected to the power ground GND; The upper plate of C1 is connected to the drain of M15, and the lower plate of C1 is connected to the power ground GND; The upper plate of C2 is connected to the drain of M16, and the lower plate of C2 is connected to the power ground GND; An input terminal of the sample and hold circuit is connected to the output terminal of the second inverter A2, the inductor voltage and the power ground.

4. The zero-crossing detection circuit of the DC-DC converter according to claim 1, characterized in that: The voltage difference quantization integration circuit includes a twenty-first P-type field effect transistor M21, a twenty-second P-type field effect transistor M22, a twenty-third P-type field effect transistor M23, a twenty-fourth N-type field effect transistor M24, a twenty-fifth N-type field effect transistor M25, a twenty-sixth N-type field effect transistor M26, a twenty-seventh N-type field effect transistor M27, a twenty-eighth P-type field effect transistor M28, a twenty-ninth P-type field effect transistor M29 and a third capacitor C3; Wherein, the gate terminal of M21 is connected to the gate terminal of M14, the source terminal of M21 is connected to the power supply voltage VDD, and the drain terminal of M21 is connected to the source terminal of M22; The gate terminal of M22 is connected to the level-shifted inductor voltage, the source terminal of M22 is connected to the drain terminal of M21, and the drain terminal of M22 is connected to the drain terminal of M24; The gate terminal of M23 is connected to the power ground after level shifting, the source terminal of M23 is connected to the drain terminal of M21, and the drain terminal of M23 is connected to the drain terminal of M25; The gate terminal of M24 is connected to the gate terminal of M26 and the drain terminal of M24, and the source terminal of M24 is connected to the power ground GND; The gate end of M25 is connected to the gate end of M27 and the drain end of M25, and the source end of M25 is connected to the power ground GND; The gate end of M26 is connected to the gate end of M24, the source end of M26 is connected to the power ground GND, and the drain end of M26 is connected to the drain end of M28; The gate end of M27 is connected to the gate end of M25, the source end of M27 is connected to the power ground GND, and the drain end of M27 is connected to the drain end of M29; The gate terminal of M28 is connected to the gate terminal of M29 and the drain terminal of M28, and the source terminal of M28 is connected to the power supply voltage VDD; The gate terminal of M29 is connected to the gate terminal of M28, the source terminal of M29 is connected to the power supply voltage VDD, and the drain terminal of M29 is connected to the drain terminal of M27; The upper plate of C3 is connected to the drain terminal of M27, and the lower plate of C3 is connected to the power ground GND; the voltage of the upper plate of C3 is the capacitor voltage.

5. A zero-crossing detection method for a DC-DC converter based on the zero-crossing detection circuit according to any one of claims 1 to 4, characterized in that: The steps include: The inductor voltage of the DC-DC converter is input to the zero-crossing detection comparison circuit in the zero-crossing detection circuit, and the zero-crossing detection comparison circuit determines whether the inductor current crosses zero by comparing the inductor voltage and the power supply ground and outputs a zero-crossing detection signal ZCD_OUT; The sampling, holding and level shifting circuit in the zero-crossing detection circuit generates a short clock pulse according to the zero-crossing detection signal ZCD_OUT for sampling the inductor voltage and the power ground, and performs level shifting on the inductor voltage and the power ground; The voltage difference quantization integration circuit in the zero-crossing detection circuit uses the level-shifted inductor voltage and the power ground to charge or discharge the third capacitor C3, and the obtained capacitor voltage is fed back to the zero-crossing detection comparison circuit to control the size of the gate-controlled resistor, thereby controlling the speed of the zero-crossing detection comparison in the next cycle; the gate-controlled resistor is the equivalent resistance of the circuit controlled by the capacitor voltage.

6. A DC-DC converter, characterized in that: The zero-crossing detection circuit according to any one of claims 1 to 4 is used to perform zero-crossing detection on a DC-DC converter.

7. A terminal device, characterized in that: A zero-crossing detection circuit comprising a DC-DC converter as claimed in any one of claims 1 to 4.

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