High-voltage integrated circuit

Abstract

The invention relates to the technical field of high-voltage integrated circuits, and provides a high-voltage integrated circuit. Comprising a plurality of RC filters, a plurality of Schmidt circuits, a plurality of filter circuits, a plurality of level switching circuits, a dead zone interlocking circuit, a bootstrap circuit, a pulse circuit, a time delay circuit, an AND gate, a driving output circuit, a temperature protection circuit, an undervoltage protection circuit, an overcurrent protection circuit, a fault logic control circuit and a fault output circuit. The bootstrap circuit comprises a double-level bootstrap power supply circuit, a level shift circuit, an RS trigger circuit and an output buffer circuit, the input end of the double-level bootstrap power supply circuit is connected with a power supply, the output end of the double-level bootstrap power supply circuit is sequentially connected with the level shift circuit, the RS trigger circuit and the output buffer circuit, and the output end of the output buffer circuit is connected to the input end of the dead zone generation circuit. According to the high-voltage integrated circuit, the applicability, the reliability and the market competitiveness of the HVIC chip can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage integrated circuits, and in particular to a high-voltage integrated circuit. Background Art

[0002] High voltage integrated circuit, or HVIC, is an integrated circuit product that converts MCU signals into driving IGBT or MOS signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage level, high voltage level, pulse generation circuit, delay circuit, filter circuit, overcurrent protection circuit, overheat protection circuit, undervoltage protection circuit, bootstrap circuit and other circuits. The single pulse GEN circuit in the high-side drive circuit of the existing HVIC generates pulses at the rising and falling edges of the HIN signal to drive DMOS. The pulse width is generally several hundred nanoseconds, so that HIN corresponds to HO.

[0003] The traditional high-voltage integrated circuit high-voltage side power supply is floating, and the voltage will increase with the increase of the bus voltage (VBUS). The voltage drop between the high-voltage side floating power supply and the floating ground needs to remain unchanged, and the potential of the high-voltage side floating ground will vary between zero and VBUS. Therefore, the high-voltage side power supply of the chip needs to adopt an isolated power supply solution, and the high-voltage side power supply of the chip needs to have a certain ability to resist voltage transients. At present, the bootstrap power supply method is the most commonly used power supply method for the high-voltage side of high-voltage integrated circuits, such as Figure 1 As shown. When the low-voltage side power tube Q2 is turned on, the potential of VS is pulled to zero potential. At this time, VCC supplies power to the bootstrap capacitor through the bootstrap diode Dboot. When charging stops, the voltage on Cboot is approximately equal to the voltage of VCC. When the low-voltage side power tube is turned off and the high-voltage side power tube is turned on, the potential of the Vs end will be quickly pulled to VBUS due to the opening of Q1. Since the voltage across the capacitor cannot change suddenly, the voltage of VCCA is approximately equal to (VBUS+VCC) at this time. At this time, the capacitor acts as a power supply for the high-voltage area circuit of the battery. When the lower tube Q2 is turned on in the next cycle, Cboot will be charged again to meet the power supply requirements when the high-voltage side power tube is turned on in the next cycle, and so on. Therefore, the bootstrap power supply method can meet the continuous power supply of the high-voltage side circuit. The gates of some power devices are extremely fragile, and excessive gate voltage can easily cause excessive leakage or even permanent damage to the power devices. However, significantly reducing the gate drive voltage cannot give full play to the excellent characteristics of the power devices. Therefore, it is necessary to design a voltage clamping circuit separately for the output voltage of the driver chip to ensure that the gate of the power device is not broken down. The traditional high-voltage side power clamp circuit has poor ability to resist VS negative bias, and the overall circuit reliability is poor. Summary of the invention

[0004] The present invention provides a high-voltage integrated circuit, aiming to solve the problem of poor reliability of the existing high-voltage integrated circuit.

[0005] An embodiment of the present invention provides a high-voltage integrated circuit, including: multiple RC filters, multiple Schmitt circuits, multiple filter circuits, multiple level conversion circuits, a dead zone interlocking circuit, a bootstrap circuit, a pulse circuit, a delay circuit, an AND gate, a drive output circuit, a temperature protection circuit, an undervoltage protection circuit, an overcurrent protection circuit, a fault logic control circuit, and a fault output circuit;

[0006] The plurality of RC filters are used to access the driving signal, and sequentially pass through the plurality of Schmitt circuits, the plurality of filter circuits, the plurality of level conversion circuits and the dead zone interlocking circuit, output a pulse signal through the dead zone interlocking circuit, and output the pulse signal to the driving output circuit through the pulse circuit; the pulse signal sequentially passes through the delay circuit and the AND gate to output the pulse signal;

[0007] The input end of the undervoltage protection circuit is connected to the input end of the bootstrap circuit and is used to connect to the power supply, and the output end of the bootstrap circuit is connected to the drive output circuit; the output end of the undervoltage protection circuit is connected to the input end of the fault logic control circuit, and the output end of the fault logic control circuit is respectively connected to the input end of the AND gate and the input end of the pulse circuit; the output end of the fault logic control circuit is used to output a fault signal through the fault output circuit; the input end of the overcurrent protection circuit is connected to the output ends of the plurality of level conversion circuits, and the output end of the overcurrent protection circuit is connected to the input end of the fault logic control circuit;

[0008] The bootstrap circuit comprises: a dual-level bootstrap power supply circuit, a level shift circuit, an RS trigger circuit and an output buffer circuit;

[0009] The input end of the dual-level bootstrap power supply circuit is connected to the power supply, the output end of the dual-level bootstrap power supply circuit is connected to the level shift circuit, the RS trigger circuit and the output buffer circuit in sequence, and the output end of the output buffer circuit is connected to the input end of the dead zone generating circuit.

[0010] Preferably, the dual-level bootstrap power supply circuit comprises: a control switch, an undervoltage detection circuit, a first bootstrap diode simulation circuit and a second bootstrap diode simulation circuit;

[0011] The input end of the undervoltage detection circuit and the source of the control switch are respectively used to connect to the power supply, the output end of the undervoltage protection circuit is connected to the level shift circuit and grounded, the drain of the control switch is connected to the input end of the first bootstrap diode simulation circuit, and the gate of the control switch is used to connect to the undervoltage detection circuit; the output end of the first bootstrap diode simulation circuit is connected to the input end of the level shift circuit, the input end of the second bootstrap diode simulation circuit is used to connect to the power supply, and the output end of the second bootstrap diode simulation circuit is connected to the input end of the level shift circuit.

[0012] Preferably, the undervoltage detection circuit comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, an inverter, a first diode, a first MOS transistor, a second MOS transistor and a third MOS transistor;

[0013] The first end of the third resistor is respectively connected to the source of the third MOS tube, the source of the second MOS tube and the first end of the second resistor and is connected to the power supply; the second end of the third resistor is respectively connected to the first end of the fourth resistor and the gate of the first MOS tube, and the second end of the fourth resistor is grounded; the source of the first MOS tube is respectively connected to the drain of the second MOS tube, the second end of the second resistor and the first end of the first resistor, the second end of the first resistor is connected to the positive electrode of the first diode, and the negative electrode of the first diode is connected to the input end of the level shift circuit; the gate of the second MOS tube is connected to the source of the second MOS tube; the drain of the first MOS tube is respectively connected to the drain of the third MOS tube and the input end of the inverter, and the drain of the third MOS tube is connected to the gate of the third MOS tube; the output end of the inverter is connected to the gate of the control switch.

[0014] Preferably, the first bootstrap diode simulation circuit comprises: a first bootstrap diode simulator, a fifth resistor, a fourth MOS transistor and a MOS transistor JFET1;

[0015] The drain of the first bootstrap diode simulator is connected to the drain of the control switch, the source of the first bootstrap diode simulator is respectively connected to the first end of the fifth resistor and the drain of the MOS tube JFET1, the gate of the first bootstrap diode simulator is respectively connected to the second end of the fifth resistor and the drain of the fourth MOS tube, the source of the MOS tube JFET1 is connected to the input end of the level shift circuit, and the gate of the MOS tube JFET1 is grounded; the source of the fourth MOS tube is grounded, and the gate of the fourth MOS tube is used to connect to the LIN port.

[0016] Preferably, the second bootstrap diode simulation circuit comprises: a second bootstrap diode simulator, a sixth resistor, a fifth MOS transistor and a MOS transistor JFET2;

[0017] The drain of the second bootstrap diode simulator is connected to the power supply, the source of the second bootstrap diode simulator is respectively connected to the first end of the sixth resistor and the drain of the MOS tube JFET2, the gate of the second bootstrap diode simulator is respectively connected to the second end of the sixth resistor and the drain of the fifth MOS tube, the source of the MOS tube JFET2 is connected to the input end of the level shift circuit, and the gate of the MOS tube JFET2 is grounded; the source of the fifth MOS tube is grounded, and the gate of the fifth MOS tube is connected to the gate of the fourth MOS tube.

[0018] Preferably, the level shift circuit includes: a triode, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube and a seventeenth MOS tube;

[0019] The base of the transistor is connected to the source of the MOS tube JFET1, the collector of the transistor is connected to the power supply voltage, and the emitter of the transistor is respectively connected to the source of the MOS tube JFET2, the source of the sixth MOS tube, the source of the seventh MOS tube, the source of the eighth MOS tube, the source of the ninth MOS tube, the source of the tenth MOS tube and the source of the eleventh MOS tube; the gate of the sixth MOS tube is respectively connected to the gate of the seventh MOS tube and the gate of the eighth MOS tube, and the gate of the ninth MOS tube is respectively connected to the gate of the tenth MOS tube and the gate of the eleventh MOS tube; the drain of the sixth MOS tube is connected to the drain of the sixteenth MOS tube, the drain of the seventh MOS tube is connected to the drain of the twelfth MOS tube, and the drain of the eighth MOS tube is connected to the drain of the fourteenth MOS tube;

[0020] The drain of the ninth MOS tube is connected to the drain of the seventeenth MOS tube, the drain of the tenth MOS tube is respectively connected to the drain and gate of the thirteenth MOS tube, and the drain of the eleventh MOS tube is respectively connected to the drain and gate of the fifteenth MOS tube;

[0021] The source of the twelfth MOS tube is respectively connected to the source of the thirteenth MOS tube, the source of the fourteenth MOS tube and the source of the fifteenth MOS tube and is grounded; the gate of the twelfth MOS tube is connected to the gate of the thirteenth MOS tube, the gate of the fourteenth MOS tube is connected to the gate of the fifteenth MOS tube; the source of the twelfth MOS tube is connected to the cathode of the first diode;

[0022] The source of the sixteenth MOS tube is connected to the source of the seventeenth MOS tube, the gate of the sixteenth MOS tube is used to connect to the SET port, and the gate of the seventeenth MOS tube is used to connect to the RESET port.

[0023] Preferably, the first end of the RS trigger circuit is connected to the source of the eleventh MOS tube, and the second end of the RS trigger circuit is connected to the source of the fifteenth MOS tube and is grounded.

[0024] Preferably, the output buffer circuit includes: a first capacitor and a first transistor, the two ends of the first capacitor are respectively connected to the two ends of the RS trigger circuit, the source of the first transistor is grounded, the gate of the first transistor is connected to the RS trigger circuit, and the drain of the first transistor is used to connect to the bus voltage.

[0025] Compared with the prior art, the beneficial effect of the present invention lies in that a plurality of RC filters are used to access the driving signal, and the signal passes through a plurality of Schmitt circuits, a plurality of filter circuits, a plurality of level conversion circuits and a dead zone interlocking circuit in sequence, a pulse signal is output through the dead zone interlocking circuit, and a pulse signal is output to the driving output circuit through the pulse circuit; the pulse signal passes through the delay circuit and the AND gate in sequence to output the pulse signal; the input end of the undervoltage protection circuit is connected to the input end of the bootstrap circuit and is used to connect the power supply, and the output end of the bootstrap circuit is connected to the driving output circuit; the output end of the undervoltage protection circuit is connected to the input end of the fault logic control circuit, and the output end of the fault logic control circuit is respectively connected to the input end of the AND gate and the input end of the pulse circuit; the output end of the fault logic control circuit is used to output a fault signal through the fault output circuit; the input end of the overcurrent protection circuit is connected to the output ends of a plurality of level conversion circuits, and the output end of the overcurrent protection circuit is connected to the input end of the fault logic control circuit; the input end of the dual-level bootstrap power supply circuit of the bootstrap circuit is connected to the power supply, and the output end of the dual-level bootstrap power supply circuit is sequentially connected to the level shift circuit, the RS trigger circuit and the output buffer circuit, and the output end of the output buffer circuit is connected to the input end of the dead zone generating circuit. In this way, by integrating the dual-level bootstrap gate clamp protection bootstrap circuit HVIC, the bootstrap circuit function is realized by the dual-level circuit, and the gate clamp technology of the dual-level bootstrap circuit is used to realize voltage clamping, which greatly improves the VS negative bias capability of the chip, thereby improving the applicability, reliability and market competitiveness of the HVIC chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0027] Figure 1 This is the circuit diagram of the traditional bootstrap power supply method;

[0028] Figure 2 is a circuit diagram of a high voltage integrated circuit provided by an embodiment of the present invention;

[0029] Figure 3 yes Figure 2 Local zoom Figure 1 ;

[0030] Figure 4 yes Figure 2 Local zoom Figure 2 ;

[0031] Figure 5 is a circuit diagram of a bootstrap circuit provided by an embodiment of the present invention;

[0032] Figure 6is a circuit diagram of a dual-level bootstrap power supply circuit provided by an embodiment of the present invention;

[0033] Figure 7 is a circuit diagram of a level shift circuit provided by an embodiment of the present invention;

[0034] Figure 8 It is a waveform diagram of a high-voltage integrated circuit provided by an embodiment of the present invention.

[0035] In the figure, 100, high voltage integrated circuit, 1, RC filter, 2, Schmitt circuit, 3, bootstrap circuit, 31, dual-level bootstrap power supply circuit, 311, undervoltage detection circuit, 312, first bootstrap diode simulation circuit, 313, second bootstrap diode simulation circuit, 32, level shift circuit, 33, RS trigger circuit, 34, output buffer circuit, 4, filter circuit, 5, level conversion circuit, 6, dead zone interlock circuit, 7, fault output circuit, 8, pulse circuit, 9, delay circuit, 10, AND gate, 11, drive output circuit, 12, temperature protection circuit, 13, undervoltage protection circuit, 14, overcurrent protection circuit, 15, fault logic control circuit. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0037] Combined with Figure 2-Figure 8 As shown, an embodiment of the present invention provides a high-voltage integrated circuit 100, including: multiple RC filters 1, multiple Schmitt circuits 2, multiple filter circuits 4, multiple level conversion circuits 5, a dead zone interlock circuit 6, a bootstrap circuit 3, a pulse circuit 8, a delay circuit 9, an AND gate 10, a drive output circuit 11, a temperature protection circuit 12, an undervoltage protection circuit 13, an overcurrent protection circuit 14, a fault logic control circuit 15 and a fault output circuit 7;

[0038] The plurality of RC filters 1 are used to access the driving signal, and sequentially pass through the plurality of Schmitt circuits 2, the plurality of filter circuits 4, the plurality of level conversion circuits 5 and the dead zone interlocking circuit 6, output a pulse signal through the dead zone interlocking circuit 6, and output the pulse signal to the driving output circuit 11 through the pulse circuit 8; the pulse signal sequentially passes through the delay circuit 9 and the AND gate 10 to output the pulse signal;

[0039] The input end of the undervoltage protection circuit 13 is connected to the input end of the bootstrap circuit 3 and is used to connect to the power supply, and the output end of the bootstrap circuit 3 is connected to the drive output circuit 11; the output end of the undervoltage protection circuit 13 is connected to the input end of the fault logic control circuit 15, and the output end of the fault logic control circuit 15 is respectively connected to the input end of the AND gate 10 and the input end of the pulse circuit 8; the output end of the fault logic control circuit 15 is used to output a fault signal through the fault output circuit 7; the input end of the overcurrent protection circuit 14 is connected to the output ends of multiple level conversion circuits 5, and the output end of the overcurrent protection circuit 14 is connected to the input end of the fault logic control circuit 15.

[0040] Specifically, HIN and LIN input drive signals pass through RC filter 1, Schmitt circuit 2, filter, level conversion circuit 5, and dead zone interlock circuit 6 to output HINa pulse signal. Pulse circuit 8 outputs ON_PLUSE / SET and OFF_PLUSE / RESET short pulse signals through the rising edge and falling edge of the HINa pulse signal respectively to drive UVWQ1 and UVWQ2 high-voltage LDMOS. The high-voltage LDMOS is turned on and off to trigger the RS trigger to output the pulse signal, which controls HO to output the drive pulse signal; the LINa pulse signal is output, which passes through the RC delay circuit 9 and the AND gate 10 to control LO to output the drive pulse signal.

[0041] The outputs of the drive signals HO and LO are protected by the undervoltage protection circuit 13, the temperature protection circuit 12, the current protection circuit (ITRIP protection circuit) and the fault logic control circuit 15. The bootstrap circuit 3 provides the bootstrap voltage to HO. The fault output circuit 7 outputs a fault signal.

[0042] In this embodiment, the bootstrap circuit 3 includes: a dual-level bootstrap power supply circuit 31, a level shift circuit 32, an RS trigger circuit 33 and an output buffer circuit 34;

[0043] The input end of the dual-level bootstrap power supply circuit 31 is connected to the VCC, and the output end of the dual-level bootstrap power supply circuit 31 is connected to the level shift circuit 32, the RS trigger circuit 33 and the output buffer circuit 34 in sequence, and the output end of the output buffer circuit 34 is connected to the input end of the dead zone generating circuit 4. By integrating the dual-level bootstrap gate clamp protection bootstrap circuit HVIC, the bootstrap circuit function is realized by the dual-level circuit, and the gate clamping technology of the dual-level bootstrap circuit is used to realize the voltage clamping, which greatly improves the VS negative bias capability of the chip, so as to improve the applicability, reliability and market competitiveness of the HVIC chip. Through the dual-level bootstrap circuit design, CADENCE's VIRTUOSO is used for layout design and MMSIM is used for DRC and LVS error checking; the dual-level bootstrap circuit is integrated into the HVIC, and the circuit function simulation of the complete HVIC circuit and MMSIM are used for DRC and LVS error checking.

[0044] In this embodiment, the dual-level bootstrap power supply circuit 31 includes: a control switch, an undervoltage detection circuit 311, a first bootstrap diode simulation circuit 312 and a second bootstrap diode simulation circuit 313;

[0045] The input end of the undervoltage detection circuit 311 and the source of the control switch are respectively used to connect to the VCC, the output end of the undervoltage protection circuit 13 is connected to the level shift circuit 32 and grounded, the drain of the control switch is connected to the input end of the first bootstrap diode simulation circuit 312, and the gate of the control switch is used to connect to the undervoltage detection circuit 311; the output end of the first bootstrap diode simulation circuit 312 is connected to the input end of the level shift circuit 32, the input end of the second bootstrap diode simulation circuit 313 is used to connect to the VCC, and the output end of the second bootstrap diode simulation circuit 313 is connected to the input end of the level shift circuit 32. By using a PMOS tube as a buffer stage, the response voltage of the buffer stage is reduced, and the two-part power supply on the high-voltage side is realized by the dual-level bootstrap power supply circuit 31 to ensure the VS negative bias capability of the chip. The new VS negative bias detection circuit generates a control signal to control the operation of the dual-level bootstrap power supply circuit 31 to achieve the purpose of output voltage clamping, so as to improve the applicability, reliability and market competitiveness of the HVIC chip.

[0046] In this embodiment, the undervoltage detection circuit 311 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, an inverter INV, a first diode D1, a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3;

[0047] The first end of the third resistor R3 is respectively connected to the source of the third MOS transistor M3, the source of the second MOS transistor M2 and the first end of the second resistor R2 and is also connected to the VCC; the second end of the third resistor R3 is respectively connected to the first end of the fourth resistor R4 and the gate of the first MOS transistor M1, and the second end of the fourth resistor R4 is grounded; the source of the first MOS transistor M1 is respectively connected to the drain of the second MOS transistor M2, the second end of the second resistor R2 and the first end of the first resistor R1, the second end of the first resistor R1 is connected to the anode of the first diode D1, and the cathode of the first diode D1 is connected to the input end of the level shift circuit 32; the gate of the second MOS transistor M2 is connected to the source of the second MOS transistor M2; the drain of the first MOS transistor M1 is respectively connected to the drain of the third MOS transistor M3 and the input end of the inverter INV, and the drain of the third MOS transistor M3 is connected to the gate of the third MOS transistor M3; the output end of the inverter INV is connected to the gate of the control switch.

[0048] The main function of the VS negative voltage detection circuit in the dead zone stage is to control the charging path from VCC to VCCA to achieve the purpose of clamping the output voltage on the high-voltage side. However, due to the particularity of the VS terminal voltage, which may be a negative voltage or a high voltage of up to 600V, the traditional negative voltage detection circuit 311 is likely to cause the risk of chip burning. The common negative voltage detection circuit 311 can be performed by comparing the resistor voltage divider value with the reference voltage. In order to solve this problem, the present invention uses the parasitic diode of the high-voltage LDMOS device as a negative voltage detection device, which can not only play the role of negative voltage detection, but also play the role of voltage resistance to protect the drive circuit.

[0049] The first diode D1 is a high-voltage diode, and the value of Vref is the reference voltage. The function of the first resistor R1 is to filter out the transient noise caused by the parasitic capacitance of the first diode D1. The second resistor R2 is a pull-up resistor, which is used to determine the potential of point E when VS is a positive voltage. The function of the second MOS tube M2 is to prevent the potential of point E from being too high and causing damage to the circuit components. The second MOS tube M2 is used as the main detection device, and its threshold voltage is 0.8V. The third MOS tube M3, as the load of the second MOS tube M2, can speed up the rise of point F. If Vref is set to 1V, then when the voltage of VS is higher than -0.5V, MN7 will be turned off, and then the control signal will be transmitted to the gate of the control switch PSW to turn on the control switch PSW to charge the bootstrap capacitor. In the dead zone stage, VS will become negative. Due to the forward clamping effect of the diode, the potential of point E will be pulled down. If the voltage of VS is lower than -0.5V, the voltage of point E will be pulled down to below 0.2V by the first diode D1, so that MN7 is turned on, and the negative voltage detection module will output a high-level signal to turn off the control switch PSW, thereby achieving the purpose of clamping the output stage voltage.

[0050] In this embodiment, the first bootstrap diode simulation circuit 312 includes: a first bootstrap diode simulator P1, a fifth resistor RD1, a fourth MOS transistor N1 and a MOS transistor JFET1;

[0051] The drain of the first bootstrap diode simulator P1 is connected to the drain of the control switch, the source of the first bootstrap diode simulator P1 is respectively connected to the first end of the fifth resistor RD1 and the drain of the MOS transistor JFET1, the gate of the first bootstrap diode simulator P1 is respectively connected to the second end of the fifth resistor RD1 and the drain of the fourth MOS transistor N1, the source of the MOS transistor JFET1 is connected to the input end of the level shift circuit 32, and the gate of the MOS transistor JFET1 is grounded; the source of the fourth MOS transistor N1 is grounded, and the gate of the fourth MOS transistor N1 is used to connect to the LIN port. The connection point between the first end of the fifth resistor RD1 and the drain of the MOS transistor JFET1 is denoted as S1.

[0052] In this embodiment, the second bootstrap diode simulation circuit 313 includes: a second bootstrap diode simulator P2, a sixth resistor RD2, a fifth MOS transistor N2 and a MOS transistor JFET2;

[0053] The drain of the second bootstrap diode simulator P2 is connected to the VCC, the source of the second bootstrap diode simulator P2 is respectively connected to the first end of the sixth resistor RD2 and the drain of the MOS transistor JFET2, the gate of the second bootstrap diode simulator P2 is respectively connected to the second end of the sixth resistor RD2 and the drain of the fifth MOS transistor N2, the source of the MOS transistor JFET2 is connected to the input end of the level shift circuit 32, and the gate of the MOS transistor JFET2 is grounded; the source of the fifth MOS transistor N2 is grounded, and the gate of the fifth MOS transistor N2 is connected to the gate of the fourth MOS transistor N1. The connection point between the first end of the sixth resistor RD2 and the drain of the MOS transistor JFET2 is recorded as S2.

[0054] Specifically, Figure 5 As shown. When LIN = 1, the first bootstrap diode simulator P1 and the fourth MOS tube N1 are turned on at the same time, and VCC charges the bootstrap capacitor CBST through the channel of the first bootstrap diode simulator P1 and the MOS tube JFET1; when LIN is zero and HIN is high, the high-voltage side GaN device is turned on, and the high-voltage side floating ground VS gradually rises to VBUS. At this time, the fourth MOS tube N1 and the first bootstrap diode simulator P1 are turned off, and the potential of the S1 point in the diode model rises with the rise of VCCA. However, as long as the voltage at the S1 point exceeds the pinch-off voltage of the MOS tube JFET1, the MOS tube JFET1 will close the channel from the drain to the source. At this time, even if VS continues to increase, the potential of S1 will not continue to increase, achieving the purpose of withstand voltage. Using the JFET bootstrap diode simulator, better reverse recovery characteristics can be obtained, because JFET has no body diode and therefore there is no reverse recovery current, and the P1 tube is a low-voltage device with a high doping concentration, so the reverse recovery current is extremely small.

[0055] In this embodiment, the level shift circuit 32 includes: a transistor Q1, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube LDMOS1 and a seventeenth MOS tube LDMOS2;

[0056] The base of the transistor Q1 is connected to the source of the MOS transistor JFET1, the collector of the transistor Q1 is connected to the power supply voltage, and the emitter of the transistor Q1 is respectively connected to the source of the MOS transistor JFET2, the source of the sixth MOS transistor M6, the source of the seventh MOS transistor M7, the source of the eighth MOS transistor M8, the source of the ninth MOS transistor M9, the source of the tenth MOS transistor M10, and the source of the eleventh MOS transistor M11; the gate of the sixth MOS transistor M6 is respectively connected to the gate of the seventh MOS transistor M7 and the gate of the eighth MOS transistor M8, and the gate of the ninth MOS transistor M9 is respectively connected to the gate of the tenth MOS transistor M10 and the gate of the eleventh MOS transistor M11; the drain of the sixth MOS transistor M6 is connected to the drain of the sixteenth MOS transistor LDMOS1, the drain of the seventh MOS transistor M7 is connected to the drain of the twelfth MOS transistor M12, and the drain of the eighth MOS transistor M8 is connected to the drain of the fourteenth MOS transistor M14;

[0057] The drain of the ninth MOS tube M9 is connected to the drain of the seventeenth MOS tube LDMOS2, the drain of the tenth MOS tube M10 is respectively connected to the drain and gate of the thirteenth MOS tube M13, and the drain of the eleventh MOS tube M11 is respectively connected to the drain and gate of the fifteenth MOS tube M15;

[0058] The source of the twelfth MOS tube M12 is respectively connected to the source of the thirteenth MOS tube M13, the source of the fourteenth MOS tube M14 and the source of the fifteenth MOS tube M15 and is grounded; the gate of the twelfth MOS tube M12 is connected to the gate of the thirteenth MOS tube M13, the gate of the fourteenth MOS tube M14 is connected to the gate of the fifteenth MOS tube M15; the source of the twelfth MOS tube M12 is connected to the cathode of the first diode D1;

[0059] The source of the sixteenth MOS transistor LDMOS1 is connected to the source of the seventeenth MOS transistor LDMOS2, the gate of the sixteenth MOS transistor LDMOS1 is used to connect to the SET port, and the gate of the seventeenth MOS transistor LDMOS2 is used to connect to the RESET port.

[0060] In this embodiment, a first end of the RS trigger circuit 33 is connected to the source of the eleventh MOS transistor M11 , and a second end of the RS trigger circuit 33 is connected to the source of the fifteenth MOS transistor M15 and is grounded.

[0061] In this embodiment, the output buffer circuit 34 includes: a first capacitor C BST and the first transistor GaNFET1, the first capacitor C BSTThe two ends of the first transistor GaNFET1 are respectively connected to the two ends of the RS trigger circuit 33, the source of the first transistor GaNFET1 is grounded, the gate of the first transistor GaNFET1 is connected to the RS trigger circuit 33, and the drain of the first transistor GaNFET1 is used to connect the bus voltage V BUS .

[0062] Specifically, the essence of the signal loss caused by the negative bias of VS is that after the signal passes through the high-voltage level shifting circuit, it cannot be received by the buffer, so the signal cannot be transmitted to the subsequent circuit. The reason why the buffer cannot receive the output signal of the high-voltage level shifting circuit is that as the floating ground VS on the high-voltage side decreases, its threshold voltage also decreases. When the threshold voltage drops below the level of the previous signal, the signal cannot continue to be transmitted. Therefore, in order to increase the VS negative bias capability of the chip, it is necessary to make the threshold voltage of the high-voltage side receiving stage circuit (the first stage circuit from VCCA to the VS voltage domain) not change with the change of VS. The turn-on condition of the PMOS tube is that the source-gate voltage difference is greater than the absolute value Vth of the turn-on voltage of the PMOS tube, that is, as long as the gate voltage is lower than the power supply voltage by Vth, it can respond, and it is not related to grounding. Therefore, this characteristic of PMOS can be used to solve the problem that the responsiveness of the LDMOS subsequent circuit to its signal is affected by the negative bias of VS.

[0063] The gate driver circuit of the bootstrap circuit 3 adopts a PMOS tube level shift structure, thereby isolating the correlation between the receiving stage response voltage and VS. Secondly, the power supply of the high-voltage area is divided into two, one is VCCA that is finally output to the gate of the high-voltage side power device, and the other is HB, which is used to power the first stage of the high-voltage area receiving circuit. The two are isolated by a transistor Q1. When VS becomes negative, the control circuit detects the negative voltage value of VS and outputs a control signal to turn off the control switch K (PSW) of the charging path. The value of VCCA will change with the change of the high-voltage side floating ground VS to ensure that the VCCA-VS voltage is constant and prevent the gate-source breakdown of the GaN device; and the voltage of HB is powered by the second bootstrap diode simulation circuit in the VS negative voltage stage, so its potential does not change with the change of the high-voltage side floating ground VS, thereby ensuring that the input signal can still be transmitted to the subsequent circuit in the VS negative voltage stage. The specific working process of the dual-level bootstrap power supply module will be described in detail below. When the high-voltage side GaN is turned off and the low-voltage side GaN is turned on, the VS voltage is zero. At this time, the switch PSW is turned on, VCC charges VCCA through the first bootstrap diode simulation circuit, and charges HB through the second bootstrap diode simulation circuit 313. At this time, the voltages of VCCA and HB are basically the same, and the circuit works in the same way as the traditional bootstrap power supply circuit. When the high-voltage side GaN is turned on and the low-voltage side GaN is turned off, the VS voltage is VBUS. At this time, the switch PSW is turned on, the first bootstrap diode simulation circuit 312 and the second bootstrap diode simulation circuit 313 are both reverse withstand voltage, and VCCA supplies power to HB through the transistor Q1, so the HB voltage is approximately equal to VCCA. In this case, the circuit works in the same way as the traditional bootstrap power supply circuit.

[0064] When the working state of the circuit is in the dead zone stage between the high-voltage side power tube being turned off and the low-voltage side power tube being turned on, the voltage of VS becomes a negative voltage, and the control circuit detects the negative voltage and controls the switch PSW to be disconnected. At this time, VCCA changes with the change of VS, but HB is still powered by VCC through the second bootstrap diode simulation circuit 313, so the potential of HB does not change. The high-voltage level shifting circuit operates in the voltage domain of VCCA-COM, the high-voltage receiving stage operates at the HB-VS voltage, and the high-voltage side output stage circuit and RS trigger operate at the VCCA-VS voltage. Since the high-voltage receiving stage is a current comparator structure, its response voltage is the threshold voltage Vth,p of the seventh MOS tube M7 and the eighth MOS tube M8. Since the HB potential does not change at this time, the VS potential drop will not affect the response voltage of the high-voltage receiving stage, and the input signal can be transmitted to the subsequent path. In the process of VS voltage changing from positive to negative, the voltage waveform of the key nodes in the circuit is as follows: Figure 8As shown. It can be seen that the high-voltage receiving stage works at the voltage of HB-VS, so the high and low levels of its output signal are HB and VS respectively, and the RS trigger works at the voltage of VCCA-VS. Due to the disconnection of the switch PSW and the isolation of the triode Q1, the voltage of VCCA changes with the VS voltage at this time, and its value is less than HB. Therefore, the existence of the high-voltage receiving stage circuit expands the level range of the output voltage. No matter how much VS is reduced, as long as the device withstand voltage meets the requirements, the output voltage of the high-voltage side receiving stage circuit includes the response threshold of the RS trigger.

[0065] The gate clamping technology with high VS negative bias capability of the present invention can not only realize the gate protection of GaN, but also take into account the static power consumption and VS negative bias capability of the high voltage side.

[0066] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0067] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A high voltage integrated circuit, characterized in that: include: Multiple RC filters, multiple Schmitt circuits, multiple filter circuits, multiple level conversion circuits, dead zone interlock circuits, bootstrap circuits, pulse circuits, delay circuits, AND gates, drive output circuits, temperature protection circuits, undervoltage protection circuits, overcurrent protection circuits, fault logic control circuits, and fault output circuits; The plurality of RC filters are used to access the driving signal, and sequentially pass through the plurality of Schmitt circuits, the plurality of filter circuits, the plurality of level conversion circuits and the dead zone interlocking circuit, output a pulse signal through the dead zone interlocking circuit, and output the pulse signal to the driving output circuit through the pulse circuit; the pulse signal sequentially passes through the delay circuit and the AND gate to output the pulse signal; The input end of the undervoltage protection circuit is connected to the input end of the bootstrap circuit and is used to connect to a power supply, and the output end of the bootstrap circuit is connected to the drive output circuit; The output end of the undervoltage protection circuit is connected to the input end of the fault logic control circuit, and the output end of the fault logic control circuit is respectively connected to the input end of the AND gate and the input end of the pulse circuit; The output end of the fault logic control circuit is used to output a fault signal through the fault output circuit; the input end of the overcurrent protection circuit is connected to the output ends of the plurality of level conversion circuits, and the output end of the overcurrent protection circuit is connected to the input end of the fault logic control circuit; The bootstrap circuit comprises: a dual-level bootstrap power supply circuit, a level shift circuit, an RS trigger circuit and an output buffer circuit; The input end of the dual-level bootstrap power supply circuit is connected to the power supply, the output end of the dual-level bootstrap power supply circuit is connected to the level shift circuit, the RS trigger circuit and the output buffer circuit in sequence, and the output end of the output buffer circuit is connected to the input end of the dead zone generating circuit.

2. The high voltage integrated circuit according to claim 1, characterized in that: The dual-level bootstrap power supply circuit comprises: a control switch, an undervoltage detection circuit, a first bootstrap diode simulation circuit and a second bootstrap diode simulation circuit; The input end of the undervoltage detection circuit and the source of the control switch are respectively used to connect to the power supply, the output end of the undervoltage protection circuit is connected to the level shift circuit and grounded, the drain of the control switch is connected to the input end of the first bootstrap diode simulation circuit, and the gate of the control switch is used to connect to the undervoltage detection circuit; the output end of the first bootstrap diode simulation circuit is connected to the input end of the level shift circuit, the input end of the second bootstrap diode simulation circuit is used to connect to the power supply, and the output end of the second bootstrap diode simulation circuit is connected to the input end of the level shift circuit.

3. The high voltage integrated circuit according to claim 2, characterized in that: The undervoltage detection circuit comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, an inverter, a first diode, a first MOS transistor, a second MOS transistor and a third MOS transistor; The first end of the third resistor is respectively connected to the source of the third MOS tube, the source of the second MOS tube and the first end of the second resistor and is connected to the power supply; the second end of the third resistor is respectively connected to the first end of the fourth resistor and the gate of the first MOS tube, and the second end of the fourth resistor is grounded; the source of the first MOS tube is respectively connected to the drain of the second MOS tube, the second end of the second resistor and the first end of the first resistor, the second end of the first resistor is connected to the positive electrode of the first diode, and the negative electrode of the first diode is connected to the input end of the level shift circuit; the gate of the second MOS tube is connected to the source of the second MOS tube; the drain of the first MOS tube is respectively connected to the drain of the third MOS tube and the input end of the inverter, and the drain of the third MOS tube is connected to the gate of the third MOS tube; the output end of the inverter is connected to the gate of the control switch.

4. The high voltage integrated circuit according to claim 3, characterized in that: The first bootstrap diode simulation circuit includes: a first bootstrap diode simulator, a fifth resistor, a fourth MOS transistor and a MOS transistor JFET1; The drain of the first bootstrap diode simulator is connected to the drain of the control switch, the source of the first bootstrap diode simulator is respectively connected to the first end of the fifth resistor and the drain of the MOS tube JFET1, the gate of the first bootstrap diode simulator is respectively connected to the second end of the fifth resistor and the drain of the fourth MOS tube, the source of the MOS tube JFET1 is connected to the input end of the level shift circuit, and the gate of the MOS tube JFET1 is grounded; the source of the fourth MOS tube is grounded, and the gate of the fourth MOS tube is used to connect to the LIN port.

5. The high voltage integrated circuit according to claim 4, characterized in that: The second bootstrap diode simulation circuit includes: a second bootstrap diode simulator, a sixth resistor, a fifth MOS transistor and a MOS transistor JFET2; The drain of the second bootstrap diode simulator is connected to the power supply, the source of the second bootstrap diode simulator is respectively connected to the first end of the sixth resistor and the drain of the MOS tube JFET2, the gate of the second bootstrap diode simulator is respectively connected to the second end of the sixth resistor and the drain of the fifth MOS tube, the source of the MOS tube JFET2 is connected to the input end of the level shift circuit, and the gate of the MOS tube JFET2 is grounded; the source of the fifth MOS tube is grounded, and the gate of the fifth MOS tube is connected to the gate of the fourth MOS tube.

6. The high voltage integrated circuit according to claim 5, characterized in that: The level shift circuit includes: a triode, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube and a seventeenth MOS tube; The base of the transistor is connected to the source of the MOS tube JFET1, the collector of the transistor is connected to the power supply voltage, and the emitter of the transistor is respectively connected to the source of the MOS tube JFET2, the source of the sixth MOS tube, the source of the seventh MOS tube, the source of the eighth MOS tube, the source of the ninth MOS tube, the source of the tenth MOS tube and the source of the eleventh MOS tube; the gate of the sixth MOS tube is respectively connected to the gate of the seventh MOS tube and the gate of the eighth MOS tube, and the gate of the ninth MOS tube is respectively connected to the gate of the tenth MOS tube and the gate of the eleventh MOS tube; the drain of the sixth MOS tube is connected to the drain of the sixteenth MOS tube, the drain of the seventh MOS tube is connected to the drain of the twelfth MOS tube, and the drain of the eighth MOS tube is connected to the drain of the fourteenth MOS tube; The drain of the ninth MOS tube is connected to the drain of the seventeenth MOS tube, the drain of the tenth MOS tube is respectively connected to the drain and gate of the thirteenth MOS tube, and the drain of the eleventh MOS tube is respectively connected to the drain and gate of the fifteenth MOS tube; The source of the twelfth MOS tube is respectively connected to the source of the thirteenth MOS tube, the source of the fourteenth MOS tube and the source of the fifteenth MOS tube and is grounded; the gate of the twelfth MOS tube is connected to the gate of the thirteenth MOS tube, the gate of the fourteenth MOS tube is connected to the gate of the fifteenth MOS tube; the source of the twelfth MOS tube is connected to the cathode of the first diode; The source of the sixteenth MOS tube is connected to the source of the seventeenth MOS tube, the gate of the sixteenth MOS tube is used to connect to the SET port, and the gate of the seventeenth MOS tube is used to connect to the RESET port.

7. The high voltage integrated circuit according to claim 6, characterized in that: The first end of the RS trigger circuit is connected to the source of the eleventh MOS tube, and the second end of the RS trigger circuit is connected to the source of the fifteenth MOS tube and is grounded.

8. The high voltage integrated circuit according to claim 7, characterized in that: The output buffer circuit includes: a first capacitor and a first transistor, wherein two ends of the first capacitor are respectively connected to two ends of the RS trigger circuit, the source of the first transistor is grounded, the gate of the first transistor is connected to the RS trigger circuit, and the drain of the first transistor is used to connect to the bus voltage.

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