Satellite-borne detection load data acquisition system

Abstract

The invention provides a satellite-borne detection load data acquisition system. The satellite-borne detection load data acquisition system comprises an ADC conversion module, a DAC conversion module, a data processing module and a clock generation module, the ADC conversion module samples and converts the front-end radio frequency signal to be acquired into a high-speed digital signal, and outputs the high-speed digital signal to the rear-end FPGA unit in the form of 204B high-speed serial digital data; the DAC conversion module is used for converting the multiple paths of 204B high-speed serial digital signals into radio frequency modulation signals and outputting the radio frequency modulation signals to the outside; the clock generation module comprises a clock signal input unit, a clock jitter attenuator unit and a high-frequency PLL generation unit; and the matching circuit is arranged on an output link of the clock generation module so as to be compatible with various clock input interfaces. High-precision data signal acquisition can be carried out, the satellite-borne detection load data transmission requirement can be better met, and the system has the advantages that the size of a basic circuit board is smaller, the number of layout and wiring is smaller, and the system cost is low.

Description

Technical Field

[0001] The present application belongs to the technical field of satellite-borne detection payloads, and in particular, relates to a satellite-borne detection payload data acquisition system. Background Art

[0002] With the rapid development of commercial aerospace, various types of satellite-borne detection payloads have also made great progress, including various detection payloads, synthetic aperture and phased array radars, and various communication unit modules for intersatellite communication. Specifically, the detection accuracy of the detection payload, data processing speed, imaging speed and accuracy of the satellite-borne radar, and communication speed of intersatellite communication have been greatly improved. The important reason for the above progress is that the data conversion rate of the core data processing unit module, namely the ADC and DAC modules, has been continuously improved. The increase in sampling rate has made the conversion of raw detection data and imaging data more accurate and faster, thereby promoting the performance improvement of the overall payload.

[0003] However, most of the current ADC / DAC digital conversion interfaces are differential LVDS interfaces. LVDS has been widely used in the field of commercial aerospace data conversion in the past due to its differential transmission, strong common-mode interference resistance, and long transmission distance. However, with the development trend mentioned above, when the data sampling rate is significantly improved, the upper limit of the LVDS data transmission rate limits the overall data processing speed, and because LVDS belongs to parallel differential data transmission, this leads to higher-speed serial data transmission than high-speed serial data transmission; when there are more functional modules of the payload and the density of components on the PCB increases, layout and wiring will become very difficult, and the only way to solve this problem is to increase the number of layers and size of the PCB, which also leads to a significant increase in the overall system cost. Summary of the invention

[0004] In view of this, the present application aims to propose a satellite-borne detection payload data acquisition system to solve the current problems of insufficient LVDS parallel data transmission rate, difficult printed circuit board layout and wiring, and ultimately leading to high overall system cost.

[0005] To achieve the above purpose, the technical solution of this application is implemented as follows: The present application provides a satellite-borne detection payload data acquisition system, comprising an ADC conversion module, a DAC conversion module, a data processing module and a clock generation module, wherein the data processing module comprises a connected FPGA unit and an MCU unit; The ADC conversion module is configured to sample the RF signal to be sampled through the balun transformer at the front end and convert it into a high-speed digital signal, and output it to the back-end FPGA unit in the form of 204B high-speed serial digital data; The DAC conversion module is configured to convert the multi-channel 204B high-speed serial digital signals sent by the back-end FPGA unit into radio frequency modulated signals for external output; The clock generation module includes a clock signal input unit, a clock jitter attenuator unit, and a high-frequency PLL generation unit. In response to a clock signal being input to the clock jitter attenuator unit, each channel of the clock jitter attenuator unit is configured separately by the MCU unit to provide corresponding required clocks to the ADC conversion module, the DAC conversion module, and the FPGA unit, respectively. One of the output channels of the clock jitter attenuator unit is selected as the input clock of the back-end high-frequency PLL generation unit to provide a clock signal to the ADC conversion module and the DAC conversion module. It also includes a matching circuit arranged on the output link of the clock generation module to be compatible with multiple clock input interfaces.

[0006] Further, the clock signal input unit includes a constant temperature crystal oscillator, a temperature compensated crystal oscillator and an external clock; In response to selecting the external clock, a radio frequency connector welding board is used as an input of an external signal source; In response to selecting the constant temperature crystal oscillator and the temperature compensated crystal oscillator, the loop filter pin of the clock jitter attenuator unit is connected to the voltage control pin of the corresponding crystal oscillator to fine-tune the output frequency of the crystal oscillator in real time.

[0007] Further, in response to the frequency of the radio frequency signal to be sampled being lower than 1.65 GHz, the clock jitter attenuator unit is used as a clock generation source; In response to the frequency of the radio frequency signal to be sampled being higher than 1.65 GHz and lower than 2.75 GHz, the high frequency PLL generating unit is used as a clock generating source.

[0008] Further, in response to the clock input interface being a CMOS interface, the matching circuit is composed of a first resistor arranged on the first branch and a second resistor arranged on the second branch, wherein the first resistor and the second resistor are 0Ω resistors.

[0009] Further, in response to the clock input interface being an LVDS interface, the matching circuit includes a first branch and a second branch; The first branch and the second branch are respectively provided with a first capacitor and a second capacitor; A first resistor, a second resistor, a third resistor and a fourth resistor connected in parallel are connected between the first branch and the second branch, wherein the third resistor and the fourth resistor are connected to the line between the first resistor and the second resistor, the other end of the third resistor is connected to the VCC power supply, and the other end of the fourth resistor is grounded; A fifth resistor and a sixth resistor connected in series are further connected between the first branch and the second branch, and the other ends of the fifth resistor and the sixth resistor are grounded.

[0010] Further, in response to the clock input interface being an LVPECL interface, the matching circuit includes a first branch and a second branch; The first branch and the second branch are respectively provided with a first capacitor and a second capacitor; A first resistor, a second resistor, and a third resistor connected in parallel are connected between the first branch and the second branch, the third resistor is connected to the line between the first resistor and the second resistor, wherein the third resistor is a 0Ω resistor; A fourth resistor and a fifth resistor connected in series are further connected between the first branch and the second branch, and the other ends of the fourth resistor and the fifth resistor are grounded.

[0011] Further, the clock input interface is a CML interface, and the matching circuit includes a first branch and a second branch; The first branch and the second branch are respectively provided with a first capacitor and a second capacitor; A first resistor, a second resistor and a third resistor connected in parallel are connected between the first branch and the second branch, wherein the third resistor is connected to the line between the first resistor and the second resistor, and the other end of the third resistor is connected to a VCC power supply; A fourth resistor and a fifth resistor connected in series are further connected between the first branch and the second branch, and the other ends of the fourth resistor and the fifth resistor are grounded.

[0012] Furthermore, the number of the balun transformers is four, wherein two of the balun transformers are used to isolate interference from two input RF signals to be sampled, and the other two balun transformers are used to isolate interference from the RF modulated signals output by the DAC conversion module, and the balun transformers use a balun transformer with an impedance ratio of 1:2.

[0013] Furthermore, the ADC conversion module and the DAC conversion module are connected to the FPGA unit via a JESD204B interface.

[0014] Compared with the prior art, the satellite-borne detection payload data acquisition system described in this application has the following beneficial effects: A satellite-borne detection payload data acquisition system described in the present application can perform high-precision data signal acquisition, significantly improve data sampling efficiency, and better meet the data transmission needs of satellite-borne detection payloads. The system has the advantages of smaller basic circuit board size, fewer layout wirings, significantly lower system cost, and better practical application effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 This is an overall structural block diagram of a satellite-borne detection payload data acquisition system described in an embodiment of the present application; Figure 2 A timing relationship diagram of the device clock and the system reference clock described in the embodiment of the present application; Figure 3 This is a structural block diagram of the clock generation module described in an embodiment of the present application; Figure 4 This is a schematic diagram of a clock output matching circuit according to an embodiment of the present application; Figure 5 This is a structural block diagram of the basic components of the JESD204B interface described in the embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0017] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The words "first", "second" and similar words used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprises" and other similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but can be Including electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0018] At present, the core modules in satellite-borne detection payloads are mostly core sampling devices such as ADC and DAC; the function of ADC is to convert the received RF detection data into digital form at a sampling clock that is about twice its frequency, and quantify the high-frequency analog signal to be measured into a digital signal that can be processed by the back-end digital processor, and then transfer the high-speed data signal to the back-end digital processing system for related algorithm processing. After the processing is completed, the high-speed signal is sent to the DAC; the function of DAC is to convert the high-speed digital signal into a high-frequency analog signal for external transmission after receiving it. This ADC and DAC unit is widely used in the currently commonly used fields of microwave communication, intersatellite communication, and satellite-borne payload detection.

[0019] However, in most high-speed signal transmission fields, digital signal transmission is carried out in the form of differential LVDS signals. LVDS differential signals have been widely used in high-speed signal transmission fields due to their advantages such as low power consumption, strong resistance to common-mode interference, and long transmission distance. However, when facing large-capacity data transmission, the maximum transmission rate of LVDS signals is only 655Mbps, which is gradually unable to meet the needs of high-speed data transmission. Moreover, LVDS transmission belongs to parallel differential data transmission, which in the current high-density circuit board design with increasingly complex functions will lead to the problem of too tight component layout, resulting in an increasing number of PCB board layers, and thus a significant increase in the overall system cost.

[0020] Based on the above problems, this application proposes a data transmission solution based on the JESD204B high-speed serial interface, and proposes a complete sampling circuit design and peripheral module design scheme such as a clock circuit that matches it. The JESD204B interface is a high-speed serial interface with a maximum transmission rate of up to 12.5Gbps. It can well solve the current problems of insufficient LVDS parallel data transmission rate and difficulties in layout and wiring. It has high application value and innovation, and has been applied in actual projects with good results.

[0021] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0022] A satellite-borne detection payload data acquisition system of this embodiment includes an ADC conversion module, a DAC conversion module, a data processing module and a clock generation module, wherein the data processing module includes a connected FPGA unit and an MCU unit; The ADC conversion module is configured to sample the RF signal to be sampled through the balun transformer at the front end and convert it into a high-speed digital signal, and output it to the back-end FPGA unit in the form of 204B high-speed serial digital data; The DAC conversion module is configured to convert the multiple 204B high-speed serial digital signals sent by the back-end FPGA unit into radio frequency modulated signals for external output; The clock generation module includes a clock signal input unit, a clock jitter attenuator unit and a high-frequency PLL generation unit. In response to the clock signal being input to the clock jitter attenuator unit, each channel of the clock jitter attenuator unit is individually configured through the MCU unit to provide corresponding required clocks to the ADC conversion module, the DAC conversion module and the FPGA unit respectively. One of the output channels of the clock jitter attenuator unit is selected as the input clock of the back-end high-frequency PLL generation unit to provide clock signals to the ADC conversion module and the DAC conversion module. The invention also includes a matching circuit arranged on the output link of the clock generation module to be compatible with various clock input interfaces.

[0023] A satellite-borne detection payload data acquisition system described in this embodiment can perform high-precision data signal acquisition, and the data sampling efficiency is significantly improved, which can better meet the data transmission requirements of satellite-borne detection payloads. The system has the advantages of smaller basic circuit board size, fewer layout wirings, significantly lower system costs, and better practical application effects.

[0024] The following is a detailed explanation of each module unit: like Figure 1 As shown, it is a block diagram of the overall solution of the present application, and the main body is divided into an ADC conversion module, a DAC conversion module, a data processing module, and a clock generation unit.

[0025] Since the ADC conversion module and the DAC conversion module support dual-channel input and dual-channel output, for the ADC conversion module input, after the two high-frequency analog signals are input externally, they first need to pass through two 1:2 Balun transformers for impedance transformation and impedance matching, and the transformers can isolate external interference to a certain extent; the purpose of selecting a 1:2 Balun is to convert a single-ended 50Ω high-frequency analog single-ended signal into a differential signal with an impedance of 100Ω, and input it into the ADC; for the DAC conversion module, when the DAC conversion module outputs the high-frequency analog signal in a differential form, the external part must also be matched with a corresponding 1:2 Balun transformer, which also performs impedance transformation and impedance matching. In particular, since the differential 100Ω is converted into a single-ended 50Ω, attention should be paid to reverse connection when connecting the balun transformer.

[0026] For the ADC conversion module and the DAC conversion module, the function of the ADC conversion module is to sample the RF signal to be sampled (high-frequency analog signal) through the balun transformer at the front end and convert it into a high-speed digital signal, and output it to the back-end receiving module, i.e., the FPGA unit, in the form of 204B serial data. The function of the DAC conversion module is to convert the multiple 204B high-speed serial digital signals sent via the back-end FPGA into high-frequency analog signals (RF modulated signals) for external output.

[0027] The normal operation of the ADC conversion module and the DAC conversion module requires an external clock source to provide two clocks: the device clock (DeviceCLK) and the system reference clock (REF CLK). At the same time, the FPGA unit as a data processing unit also requires the same device clock and system reference clock to achieve synchronization between the sender and the receiver.

[0028] The clocks of both the sender and the receiver are determined by Figure 1 The device clock (Device CLK) is generated by the CLK Unit in the device clock generator. It is the main clock for the working of components. For the ADC conversion module and the DAC conversion module, it is the sampling clock of the high-frequency RF signal. According to the Nyquist sampling theorem, the frequency value of the sampling clock needs to be twice or more than the frequency of the signal to be sampled. For the FPGA unit, it is the reference clock for receiving and sending JESD204B data. The function of the system reference clock (REF CLK) is to achieve device clock synchronization between different devices. Specifically, it is used to indicate the edge of the device clock of different data converters, because data sampling and conversion are based on the edge of the clock. Therefore, after the edge of the device clock is accurately calibrated by the reference clock, the clock synchronization between different units can be achieved. The specific timing relationship that needs to be met is as follows Figure 2 As shown: Specifically, the first rising edge of the system reference clock in the figure needs to be easily captured by the device clock.

[0029] And, when the reference clock completes the synchronization of the device clock, the RX side will pull the handshake signal Sync signal low, and when the TX side detects that the Sync signal is pulled low, it will start to transmit 204B high-speed serial data. For ADC and FPGA, ADC belongs to TX and FPGA belongs to RX. For DAC and FPGA, DAC belongs to RX and FPGA belongs to TX.

[0030] For the data processing module, its main component is the FPGA+MCU processing architecture. The FPGA unit is responsible for receiving the multiple 204B high-speed serial data sent by the ADC conversion module. After processing, the data is sent to the DAC conversion module in the form of multiple high-speed 204B serial data, and converted into a radio frequency modulated signal for external transmission. The main function of the MCU unit is to independently and flexibly configure each module that needs to be configured in the overall system through the SPI signal configuration, mainly including the sampling configuration of the ADC conversion module and the DAC conversion module, and the output clock frequency configuration of the clock unit CLK Unit. In addition, some commonly used communication interfaces are added between the FPGA unit and the MCU unit, including the SPI serial port and the FMC communication interface, to meet the communication needs between processors.

[0031] As another important module of this application, CLK Unit (clock generation module) is mainly composed of three parts, as follows Figure 3 As shown, they are a clock signal input unit, a clock jitter attenuator unit and a high-frequency PLL generating unit.

[0032] The first is the crystal oscillator input module, that is, the clock signal input unit. This unit has three clock selection schemes: oven controlled crystal oscillator (OCXO), temperature compensated crystal oscillator (TCXO) and external clock input (reserved). According to specific usage requirements, you can flexibly choose one of the schemes to use.

[0033] Both OCXO and TCXO are on-board clocks. For external clock input, you can choose to use an RF connector soldering board and input it through an external signal source. The external signal source can be flexibly selected, and you can choose an independent signal source input or match it with an external clock circuit board, which can better meet the input clock needs.

[0034] In particular, when using a constant temperature crystal oscillator and a temperature compensated crystal oscillator, it is necessary to connect the loop filter pin of the clock generation chip (i.e., the PLL_COUT signal in the figure) to the voltage control pin of the corresponding crystal oscillator to fine-tune the crystal oscillator output frequency in real time to ensure the stability of the crystal oscillator output. This requirement is not required when selecting an external clock input.

[0035] For the clock jitter attenuator unit, TI's LMK04828 is selected. This chip supports 14 clock outputs. The frequency of a single clock can be flexibly configured through software, and the maximum output frequency can reach 3.1GHz. The specific configuration method is configured through the SPI signal through the MCU unit of the back-end data processing module.

[0036] Considering that the maximum clock output frequency of LMK04828 is 20MHz~3.1GHz, a high-precision PLL chip LMX2582 is added, which supports dual-channel output and an output clock range of 20MHz~5.5GHz to meet the needs of RF signal sampling around 2GHz.

[0037] Therefore, if Figure 3 As shown in the middle block diagram, after the clock is input to the jitter attenuator, each channel of the chip is configured separately through the SPI method of the MCU unit, and the corresponding required clock can be provided to the ADC conversion module, the DAC conversion module and the FPGA. In addition, by selecting an output channel of the attenuator as the input clock of the back-end high-frequency PLL, the sampling requirements of higher-frequency RF signals can be met. When the frequency of the signal to be sampled is lower than 1.65GHz, LMK04828 can be used alone as a clock providing unit. When the signal frequency is higher than 1.65GHz and lower than 2.75GHz, the device clock can be selected to be provided by LMX2582. Therefore, the clock unit module involved in this embodiment can better meet the sampling requirements of RF signals in various frequency ranges.

[0038] like Figure 4 As shown, it is a matching circuit solution for the clock output module, which is used to adapt to different interface design solutions. The clock input interfaces of the current high-speed digital conversion chips commonly use CMOS, LVDS, LVPECL and CML interfaces. This application takes into account the current different interface requirements and designs a multifunctional matching circuit on the output link of the clock unit, which can be compatible with the above-mentioned commonly used interface forms.

[0039] When the interface used is a CMOS interface, the matching resistors between the output differential clocks are not welded (NC, NOT Connection), and the coupling capacitor position on the output loop is replaced with a 0Ω resistor to meet the CMOS direct connection requirements.

[0040] When the interface used is the LVDS interface form, the R45 resistor, the R51 resistor, the R53 resistor and the R55 resistor are all NC, the C177 capacitor and the C178 capacitor are welded with a 0.1uF capacitor, and the R52 resistor and the R56 resistor are welded with a 50Ω resistor to meet the impedance matching requirements.

[0041] When the interface used is the LVPECL interface form, just need to make R45 resistor, R52 resistor, R56 resistor NC, solder R51 resistor, R55 resistor, solder 150Ω resistor, solder R53 resistor 0Ω resistor, solder C177 capacitor and C178 capacitor 0.1uF capacitor.

[0042] When the interface used is the CML interface form, it is necessary to weld the R45 resistor, the R51 resistor, the R55 resistor, the R52 resistor and the R56 resistor, and weld the C177 capacitor and the C178 capacitor; the R53 resistor does not need to be welded.

[0043] In addition, in this embodiment, the JESD204B interface is used. The interface is a high-speed serial data link of several Gb between a converter (usually ADC or DAC) and a receiver (usually FPGA or ASIC). The serial data link refers to a single serial channel between one or more converters and a receiver. The JESD204B interface supports multiple, aligned serial channels under multiple converters, which can better meet the increasing speed and resolution of current converters. Compared with the differential LVDS data transmission interface, the JESD204B interface is a high-speed serial data interface that can effectively reduce the number of differential pairs of data output, thereby making the package size of components smaller and reducing the number of wiring. This can greatly simplify the layout design of the circuit board, reduce the overall system cost, and better meet the current development needs of commercial aerospace high-speed data conversion and cost reduction; it has high application value and innovation.

[0044] In addition, the JESD204B interface can effectively solve the problem of deterministic delay of serial data on serial data links. For data converters, when receiving a signal, if you want to correctly reconstruct the analog domain sampled signal, the key is to understand the timing relationship between the sampled signal and its digital representation, which is affected by the delay of the converter; for the ADC conversion module, it is defined as the number of clock cycles from the moment the input signal sampling edge is reached until the converter outputs the digital signal. Similarly, for the DAC conversion module, the delay is defined as the number of clock cycles from the moment the digital signal enters the DAC conversion module until the analog output begins to change.

[0045] as follows Figure 5 As shown in the figure, in the JESD204B system, the device clock is used as the time reference for each component in the system. Each converter and receiver obtains the device clock generated by the clock generator circuit unit. The generator circuit is responsible for generating all device clocks from the same source, which makes the system design more flexible. The JESD204B interface can well ensure that the device is resynchronized between two power-on cycles and between different links, and the delay is reproducible and deterministic.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

[0047] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A satellite-borne detection payload data acquisition system, characterized in that: It includes an ADC conversion module, a DAC conversion module, a data processing module and a clock generation module, wherein the data processing module includes a connected FPGA unit and an MCU unit; The ADC conversion module is configured to sample the RF signal to be sampled through the balun transformer at the front end and convert it into a high-speed digital signal, and output it to the back-end FPGA unit in the form of 204B high-speed serial digital data; The DAC conversion module is configured to convert the multi-channel 204B high-speed serial digital signals sent by the back-end FPGA unit into radio frequency modulated signals for external output; The clock generation module includes a clock signal input unit, a clock jitter attenuator unit and a high-frequency PLL generation unit. In response to the clock signal being input to the clock jitter attenuator unit, each channel of the clock jitter attenuator unit is configured separately by the MCU unit to provide corresponding required clocks to the ADC conversion module, the DAC conversion module and the FPGA unit respectively, and one of the output channels of the clock jitter attenuator unit is selected as the input clock of the back-end high-frequency PLL generation unit to provide a clock signal to the ADC conversion module and the DAC conversion module; It also includes a matching circuit arranged on the output link of the clock generation module to be compatible with multiple clock input interfaces.

2. The satellite-borne detection payload data acquisition system according to claim 1, characterized in that: The clock signal input unit includes a constant temperature crystal oscillator, a temperature compensated crystal oscillator and an external clock; In response to selecting the external clock, a radio frequency connector welding board is used as an input of an external signal source; In response to selecting the constant temperature crystal oscillator and the temperature compensated crystal oscillator, the loop filter pin of the clock jitter attenuator unit is connected to the voltage control pin of the corresponding crystal oscillator to fine-tune the output frequency of the crystal oscillator in real time.

3. The satellite-borne detection payload data acquisition system according to claim 1, characterized in that: In response to the frequency of the radio frequency signal to be sampled being lower than 1.65 GHz, using the clock jitter attenuator unit as a clock generation source; In response to the frequency of the radio frequency signal to be sampled being higher than 1.65 GHz and lower than 2.75 GHz, the high frequency PLL generating unit is used as a clock generating source.

4. The satellite-borne detection payload data acquisition system according to claim 1, characterized in that: In response to the clock input interface being a CMOS interface, the matching circuit is composed of a first resistor arranged on a first branch and a second resistor arranged on a second branch, wherein the first resistor and the second resistor are 0Ω resistors.

5. The satellite-borne detection payload data acquisition system according to claim 1, characterized in that: In response to the clock input interface being an LVDS interface, the matching circuit includes a first branch and a second branch; The first branch and the second branch are respectively provided with a first capacitor and a second capacitor; A first resistor, a second resistor, a third resistor and a fourth resistor connected in parallel are connected between the first branch and the second branch, wherein the third resistor and the fourth resistor are connected to the line between the first resistor and the second resistor, the other end of the third resistor is connected to the VCC power supply, and the other end of the fourth resistor is grounded; A fifth resistor and a sixth resistor connected in series are further connected between the first branch and the second branch, and the other ends of the fifth resistor and the sixth resistor are grounded.

6. The satellite-borne detection payload data acquisition system according to claim 1, characterized in that: In response to the clock input interface being an LVPECL interface, the matching circuit includes a first branch and a second branch; The first branch and the second branch are respectively provided with a first capacitor and a second capacitor; A first resistor, a second resistor, and a third resistor connected in parallel are connected between the first branch and the second branch, the third resistor is connected to the line between the first resistor and the second resistor, wherein the third resistor is a 0Ω resistor; A fourth resistor and a fifth resistor connected in series are further connected between the first branch and the second branch, and the other ends of the fourth resistor and the fifth resistor are grounded.

7. The satellite-borne detection payload data acquisition system according to claim 1, characterized in that: The clock input interface is a CML interface, and the matching circuit includes a first branch and a second branch; The first branch and the second branch are respectively provided with a first capacitor and a second capacitor; A first resistor, a second resistor and a third resistor connected in parallel are connected between the first branch and the second branch, wherein the third resistor is connected to the line between the first resistor and the second resistor, and the other end of the third resistor is connected to a VCC power supply; A fourth resistor and a fifth resistor connected in series are further connected between the first branch and the second branch, and the other ends of the fourth resistor and the fifth resistor are grounded.

8. The satellite-borne detection payload data acquisition system according to claim 1, characterized in that: The number of the balun transformers is four, wherein two of the balun transformers are used to isolate interference from two input RF signals to be sampled, and the other two balun transformers are used to isolate interference from the RF modulated signals output by the DAC conversion module. The balun transformers use balun transformers with an impedance ratio of 1:

2.

9. The satellite-borne detection payload data acquisition system according to claim 1, characterized in that: The ADC conversion module and the DAC conversion module are connected to the FPGA unit via a JESD204B interface.

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