Communication system function performance collaborative verification architecture and method based on UVM

Abstract

The invention discloses a communication system function performance collaborative verification architecture and method based on a UVM, the communication system function performance collaborative verification architecture based on the UVM comprises a to-be-tested communication system design Top DUT, a top verification environment Topenv and an interface, and the to-be-tested communication system design Top DUT and the top verification environment Topenv are connected through the interface and communicate with each other; the communication system function performance collaborative verification method based on the UVM verifies the system by using the communication system verification architecture. Compared with traditional function verification, through function and performance cooperative verification, an innovative solution is brought to verification work of a communication system, and the research and development period of a communication chip is shortened.

Description

Technical Field

[0001] The present invention relates to a communication system verification architecture and method, in particular to a UVM-based communication system functional performance collaborative verification architecture and method. Background Art

[0002] The communication system uses different transmission media to transmit data signals to various devices and systems. It has become an important way of IoT communication transmission, especially in the fields of smart grid, industrial automation, smart home, etc. With its unique advantages, it has made important contributions to the intelligent development and energy conservation and environmental protection of modern society. Due to the existence of noise interference and signal attenuation in the communication channel, the reliability of its communication is reduced. In order to improve the adaptability of the communication system to different channels, the communication reliability can be optimized at the physical layer through spectrum optimization, error correction coding and other methods. Therefore, the design verification of the communication system has become increasingly important. However, with the complexity of the design of the communication system, new verification challenges have also been brought about. How to maximize the output of the verification work input within a given time, verify the performance while verifying its function, that is, improve the verification efficiency, and how to reduce the manual operation in completing a verification project and cover all possible operating states, that is, improve the verification reliability, are all challenges in the current communication system circuit verification. Summary of the invention

[0003] Purpose of the invention: The technical problem to be solved by the present invention is to provide a UVM-based communication system functional performance collaborative verification architecture and method in view of the deficiencies in the prior art.

[0004] In order to solve the above technical problems, the present invention discloses a UVM-based communication system functional performance collaborative verification architecture and method, wherein a UVM-based communication system functional performance collaborative verification architecture comprises: a communication system design Top DUT to be tested, a top-level verification environment Top_env and an interface, wherein the communication system design Top DUT to be tested and the top-level verification environment Top_env are connected through the interface and communicate with each other;

[0005] The communication system design Top DUT to be tested includes N sub-modules to be tested and a group of registers for storing control information of the sub-modules to be tested and working status information of the sub-modules to be tested;

[0006] The top-level verification environment Top_env includes:

[0007] N verification sub-environments correspond one-to-one to the N sub-modules to be tested in the Top DUT of the communication system design to be tested, and verify them;

[0008] A Top reference model is a model used to simulate the behavior of the communication system to be tested and provide a standard for the verification result;

[0009] A Top scoreboard, which is used to collect and analyze the expected output data of the Top reference model and the actual output data of the communication system under test, calculate the difference between the actual output behavior and the expected output behavior and the system performance indicators, and generate reports;

[0010] A register model is used to describe and simulate registers and register fields in the communication system to be tested. The top-level verification environment Top_env interacts with the registers in the communication system to be tested and verifies the registers in the communication system to be tested by reading, writing and modifying the values ​​of the register model.

[0011] a virtual sequencer to provide a unified control and coordination interface for managing and coordinating the generation, execution, and analysis of multiple test transaction stimulus sequences;

[0012] and a bus agent for modeling and verifying the bus protocol supported in the communication system under test, and generating, controlling and analyzing the bus communication in the communication system under test.

[0013] Furthermore, each of the N verification sub-environments includes:

[0014] A reference model is used to simulate the hardware behavior of the corresponding sub-module under test and provide a standard for the verification of the corresponding sub-module under test;

[0015] A scoreboard that collects and analyzes the expected output behavior of the reference model and the actual output behavior of the submodule under test, calculates the difference between the actual output data and the expected output data, and generates a report;

[0016] an input agent to simulate, generate, and validate input signals;

[0017] and an output agent to monitor, analyze, and verify the output data behavior in the submodule under test;

[0018] Among them, the input agent transmits the generated input signal to the sub-module under test through the interface; the input agent hands over the monitored input signal of the sub-module under test to the reference model for processing, and the reference model sends the expected output behavior to the scoreboard; the output agent obtains the actual output data behavior of the sub-module under test from the interface and hands it over to the scoreboard for processing.

[0019] Furthermore, the input agent includes:

[0020] The sequencer is responsible for controlling and generating transaction stimulus sequences and passing the transaction stimulus sequences to the driver;

[0021] The driver is used to control the input transaction stimulus sequence and convert the transaction level to the signal level; simulate the data exchange between the submodule to be tested and the verification environment to verify the submodule to be tested;

[0022] and a first monitor, for monitoring and capturing input signals of the submodule under test during the operation of the verification work;

[0023] The output agent includes: a second monitor for monitoring and capturing the output signal of the submodule to be tested during the verification work operation.

[0024] The present invention also discloses a UVM-based communication system functional performance collaborative verification method, which uses the above-mentioned UVM-based communication system functional performance collaborative verification architecture to verify the communication system, specifically comprising:

[0025] Step 1, initializing the verification architecture of the communication system;

[0026] Step 2: Generate transaction incentives based on corresponding functional and performance test examples, including directed and randomly constrained transaction incentives;

[0027] Step 3, the virtual sequencer receives the generated transaction stimulus and coordinates and sends the transaction stimulus to the sequencers in each verification sub-environment;

[0028] Step 4, determining whether the input agent of each verification sub-environment in the verification architecture is activated, if so, executing step 5, otherwise executing step 6;

[0029] Step 5, verify that the sequencer in the sub-environment receives the corresponding transaction stimulus sent by the virtual sequencer, and execute step 7;

[0030] Step 6, respectively starting the first monitor and the second monitor in the verification sub-environment, wherein: the data monitored by the first monitor is transmitted to the reference model in the corresponding sub-verification environment; the data monitored by the second monitor is transmitted to the scoreboard in the corresponding sub-verification environment;

[0031] Step 7, starting the driver in each verification sub-environment of the activated input agent, obtaining the transaction stimulus from the sequencer in the verification sub-environment, and driving the transaction stimulus to the interface;

[0032] Step 8: The reference model and the Top reference model in each verification sub-environment process the transaction stimulus obtained from the monitor through their own simulation circuit behavior to obtain the expected output result, and transmit the result to the scoreboard and the Top scoreboard in each verification sub-environment;

[0033] Step 9: Use the function and performance collaborative verification strategy to compare the expected output result with the actual output result of the communication system to complete the verification of the communication system.

[0034] Furthermore, the transaction stimulus described in step 2 is a random transaction stimulus that traverses all communication frequency bands, modes, and functional requirements, and includes boundary conditions and abnormal conditions such as large signals, small signals, and signals under different SNR conditions for performance testing.

[0035] Furthermore, the function and performance co-verification strategy described in step 9 is to use the signal to quantization noise ratio SQNR for comparison.

[0036] Furthermore, the function and performance collaborative verification strategy specifically includes:

[0037] Calculate the error of each point: match each point in the expected output result sequence with the actual output result sequence one by one, calculate the difference, that is, the error, and use error[n] to represent the error of the nth point, where N represents the total number of points;

[0038] Calculate the noise power: add up the squares of the amplitudes of all error points and divide by the number of error points N to get the noise power Pn, as follows:

[0039]

[0040] Calculate the signal power: add up the squares of the amplitudes of each point in the expected output sequence, and divide by the number of points to get the signal power Ps, as follows:

[0041]

[0042] Calculate SQNR: Divide the signal power by the noise power, and then take 10 times the logarithm to get the SQNR value, as follows:

[0043]

[0044] A SQNR threshold is preset, that is, when the SQNR is greater than the threshold, it indicates that the performance of the communication system to be tested meets the system design requirements and the verification is passed, otherwise it is failed.

[0045] Beneficial effects:

[0046] Aiming at the problems of high verification cost, long verification cycle, low efficiency and high verification complexity of current communication system, the present invention introduces a function and performance collaborative verification strategy, proposes a verification architecture and function and performance collaborative verification method of UVM-based communication system, focuses on test case development through function and performance collaborative verification, improves verification efficiency, brings innovative solutions to the verification work of communication system, and shortens the research and development cycle of communication chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0048] Figure 1 This is a schematic diagram of verifying the flow of stimulus data when the communication system acts as a transmitter.

[0049] Figure 2 This is a schematic diagram of verifying the flow of stimulus data when the communication system acts as a receiving end.

[0050] Figure 3 Schematic diagram of the verification environment structure of the communication system.

[0051] Figure 4 Validate the flow chart for the communication system. DETAILED DESCRIPTION

[0052] The present invention proposes a UVM-based communication system function performance collaborative verification architecture and method, which improves verification efficiency through function and performance collaborative verification, brings innovative solutions to the verification work of the communication system, and shortens the communication chip development cycle. The specific technical solutions are as follows:

[0053] A UVM-based communication system functional performance verification architecture includes: a communication system design Top DUT to be tested, a top-level verification environment Top_env, and an interface, wherein the communication system design Top DUT to be tested and the top-level verification environment Top_env are connected through the interface and communicate with each other;

[0054] The communication system design Top DUT to be tested includes N sub-modules to be tested and a group of registers for storing control information of the sub-modules to be tested and working status information of the sub-modules to be tested;

[0055] The top-level verification environment Top_env includes:

[0056] N verification sub-environments correspond one-to-one to the N sub-modules to be tested in the Top DUT of the communication system design to be tested, and verify them;

[0057] A Top reference model is a model used to simulate the behavior of the communication system to be tested and provide a standard for the verification result;

[0058] A Top scoreboard, which is used to collect and analyze the expected output data of the Top reference model and the actual output data of the communication system under test, calculate the difference between the actual output behavior and the expected output behavior and system performance indicators such as SQNR, and generate reports;

[0059] A register model is used to describe and simulate registers and register fields in the communication system to be tested. The top-level verification environment Top_env interacts with the registers in the communication system to be tested and verifies the registers in the communication system to be tested by reading, writing and modifying the values ​​of the register model.

[0060] a virtual sequencer to provide a unified control and coordination interface for managing and coordinating the generation, execution, and analysis of multiple test transaction stimulus sequences;

[0061] and a bus agent for modeling and verifying the bus protocol supported in the communication system under test, and generating, controlling and analyzing the bus communication in the communication system under test.

[0062] Furthermore, each of the N verification sub-environments includes:

[0063] A reference model is used to simulate the hardware behavior of the corresponding sub-module under test and provide a standard for the verification of the corresponding sub-module under test;

[0064] A scoreboard that collects and analyzes the expected output behavior of the reference model and the actual output behavior of the submodule under test, calculates the difference between the actual output data and the expected output data, and generates a report;

[0065] an input agent to simulate, generate, and validate input signals;

[0066] and an output agent to monitor, analyze, and verify the output data behavior in the submodule under test;

[0067] Among them, the input agent transmits the generated input signal to the sub-module under test through the interface; the input agent hands over the monitored input signal of the sub-module under test to the reference model for processing, and the reference model sends the expected output behavior to the scoreboard; the output agent obtains the actual output data behavior of the sub-module under test from the interface and hands it over to the scoreboard for processing.

[0068] Furthermore, the input agent includes:

[0069] The sequencer is responsible for controlling and generating transaction stimulus sequences and passing the transaction stimulus sequences to the driver;

[0070] The driver is used to control the input transaction stimulus sequence and convert the transaction level to the signal level; simulate the data exchange between the submodule to be tested and the verification environment to verify the submodule to be tested;

[0071] and a first monitor, for monitoring and capturing input signals of the submodule under test during the operation of the verification work;

[0072] The output agent includes: a second monitor for monitoring and capturing the output signal of the submodule to be tested during the verification work operation.

[0073] like Figure 1 The figure shows the flow of transaction stimulus data in the verification process when the communication system is used as the transmitter. Specifically, the constrained random stimulus (which traverses all frequency bands, basic modes and extended modes, and functional requirements, and contains large signals, small signals and other boundary conditions and abnormal conditions for performance testing) composed of the TX data source (consisting of frame control data and payload data) and register configuration information is input to the communication system design to be verified (DUT) through the interface in the verification environment on the one hand, and input to the TX reference model of the communication system through the DPI interface or text form on the other hand. Finally, the output data stream of the communication system and the output data stream of the TX reference model are verified through the functional and performance collaborative verification strategy to check whether the design meets the transmission specification requirements of the communication system and avoid over-design of the communication system.

[0074] In some embodiments, optionally, implementation methods of the TX reference model include but are not limited to C language reference model, systemC reference model, matlab reference model, etc.

[0075] like Figure 2 As shown, it is a schematic diagram of the transaction stimulus data flow in the verification process when the communication system is used as the receiving end. Specifically, the constrained random stimulus composed of the RX data source and register configuration information (a random transaction stimulus that traverses all frequency bands, basic modes and extended modes, and functional requirements, and contains boundary conditions and abnormal conditions such as large signals and small signals for performance testing) is input to the communication system design to be verified (DUT) through the interface in the verification environment on the one hand, and is input to the RX reference model of the communication system through the DPI interface or text form on the other hand. Finally, the output frame control data 1 and payload data 1 of the communication system are compared with the output frame control data 2 and payload data 2 of the RX reference model, and the reception accuracy is used to check whether the design meets the reception specification requirements of the communication system.

[0076] In some embodiments, optionally, implementation methods of the RX reference model include but are not limited to C language reference model, systemC reference model, matlab reference model, etc.

[0077] like Figure 3As shown, it is a schematic diagram of the verification environment architecture of the communication system. The specific technical solution is as follows: the verification environment of the communication system includes multiple configurable and reusable modular components. Specifically: the verification environment consists of a Top circuit design to be verified (a communication system hardware circuit design consisting of circuit modules including submodule A, submodule B and registers), a Top reference model, a Top scoreboard component, a register model component, a bus agent component (including a sequencer Bus, a driver Bus and a monitor Bus), an interface and multiple verification sub-environment N_env components (each N_env includes a reference model N, a scoreboard N, an input agent N (including a sequencer N, a driver N and a monitor N1), an output agent N (including a monitor N2)) and other components.

[0078] The present invention also discloses a method for collaboratively verifying the functional performance of a communication system, which uses the above-mentioned verification architecture based on the UVM communication system to verify the communication system, specifically comprising:

[0079] Step 1, initializing the verification architecture of the communication system;

[0080] Step 2: Generate transaction incentives based on corresponding functional and performance test examples, including directed and randomly constrained transaction incentives;

[0081] Step 3, the virtual sequencer receives the generated transaction stimulus and coordinates and sends the transaction stimulus to the sequencers in each verification sub-environment;

[0082] Step 4, determining whether the input agent of each verification sub-environment in the verification architecture is activated, if so, executing step 5, otherwise executing step 6;

[0083] Step 5, verify that the sequencer in the sub-environment receives the corresponding transaction stimulus sent by the virtual sequencer, and execute step 7;

[0084] Step 6, respectively starting the first monitor and the second monitor in the verification sub-environment, wherein: the data monitored by the first monitor is transmitted to the reference model in the corresponding sub-verification environment; the data monitored by the second monitor is transmitted to the scoreboard in the corresponding sub-verification environment;

[0085] Step 7, starting the driver in each verification sub-environment of the activated input agent, obtaining the transaction stimulus from the sequencer in the verification sub-environment, and driving the transaction stimulus to the interface;

[0086] Step 8: The reference model and the Top reference model in each verification sub-environment process the transaction stimulus obtained from the monitor through their own simulation circuit behavior to obtain the expected output result, and transmit the result to the scoreboard and the Top scoreboard in each verification sub-environment;

[0087] Step 9: Use the function and performance collaborative verification strategy to compare the expected output result with the actual output result of the communication system to complete the verification of the communication system.

[0088] Furthermore, the transaction stimulus described in step 2 is a random transaction stimulus that traverses all communication frequency bands, modes, and functional requirements, and includes boundary conditions and abnormal conditions such as large signals, small signals, and signals under different SNR conditions for performance testing (for example: the signal is full amplitude, half amplitude, SNR is -6, 0, 30, etc.).

[0089] Furthermore, the function and performance co-verification strategy described in step 9 is to use the signal to quantization noise ratio SQNR for comparison.

[0090] Furthermore, the function and performance collaborative verification strategy specifically includes:

[0091] Calculate the error of each point: match each point in the expected output result sequence with the actual output result sequence one by one, calculate the difference, that is, the error, and use error[n] to represent the error of the nth point, where N represents the number of points;

[0092] Calculate the noise power: add up the squares of the amplitudes of all error points and divide by the number of error points N to get the noise power Pn, as follows:

[0093]

[0094] Calculate the signal power: add up the squares of the amplitudes of each point in the expected output sequence, and divide by the number of points to get the signal power Ps, as follows:

[0095]

[0096] Calculate SQNR: Divide the signal power by the noise power, and then take 10 times the logarithm to get the SQNR value, as follows:

[0097]

[0098] A SQNR threshold is preset, that is, when the SQNR is greater than the threshold, it indicates that the performance of the communication system to be tested meets the system design requirements and the verification is passed, otherwise it is failed.

[0099] like Figure 4The figure shows a communication system verification flow chart based on the above verification environment architecture. The flow is as follows: Step 1, initialize the system verification environment platform; Step 2, generate transaction stimuli according to the corresponding test examples, including directed and randomly constrained transaction stimuli; Step 3, the virtual sequencer receives the generated transaction stimuli and sends the transaction stimuli to the subsequencer; Step 4, determine whether the input agents of each subenvironment in the verification environment are activated; Step 5, if the input agent in the subenvironment is activated, the sequencer in the subenvironment receives the corresponding transaction stimuli sent by the virtual sequencer. If the input agent in the sub-environment is not activated, the monitors in the input and output agents in the sub-environment are started respectively, wherein the data monitored by the input agent is transmitted to the corresponding reference model at the transaction level through the TLM port, and the data monitored by the output agent is transmitted to the corresponding scoreboard at the transaction level through the TLM port; Step 6, start the driver in the input agent in each activated sub-environment, obtain the transaction stimulus from its corresponding sub-sequencer through the TLM port, and drive the transaction-level stimulus to the corresponding interface at the signal level; Step 7, start the monitors in the input and output agents in the activated sub-environment respectively, wherein the data monitored by the input agent is transmitted to the corresponding reference model at the transaction level through the TLM port, and the data monitored by the output agent is transmitted to the corresponding scoreboard at the transaction level through the TLM port; Step 8, each sub-reference model and the Top reference model process the acquired transaction by simulating its corresponding circuit function to obtain the expected output result, and transmit these results to the corresponding scoreboard. Step 9, each sub-environment scoreboard and the Top scoreboard receive the expected output result and the actual circuit output result; Step 10, use the fuzzy comparison verification strategy to compare the result data of both parties;

[0100] Example:

[0101] An exemplary embodiment of the verification process of the communication system of the present application based on the State Grid dual-mode communication interconnection technical specifications will be described in more detail below.

[0102] Step 1: Initialize the verification environment: In the build_phase stage, instantiate each component and interface in the verification environment, and set the input agent in each sub-N_env to an inactive state (especially, if only a single sub-module design is to be verified, the input agent in the corresponding sub-env needs to be set to an active state); connect each component in the verification environment in the connect_phase stage;

[0103] The Top_env component is derived from the uvm_env class as a structured standard unit container, and instantiates multiple sub-N_env, bus agent, register model, Top scoreboard and other components encapsulated by it. The communication system circuit to be verified based on the State Grid dual-mode communication interconnection technical specification is connected to the Top_env component through an interface component. For each sub-N_env component, it is also derived from the uvm_env class, and the input agent, output agent, scoreboard and other components encapsulated by it are instantiated internally. The internal components are connected through the TLM port, and are also connected to the sub-module circuit to be verified through the interface component to form a sub-module verification environment. Here, the submodule N_env includes but is not limited to (CRC module verification environment, turbo module verification environment, FFT module verification environment, robo module verification environment, etc.); the virtual sequencer and each subsequencer are derived from the uvm_sequencer class, which is the medium for communication between transactions and drivers and the router in the entire incentive link; the bus agent and the input and output agents in each sub-N_env component are derived from the uvm_agent class, which contains the sequencer, driver and monitor derived from the uvm_sequencer class, uvm_driver class and uvm_monitor class respectively. The register model is derived from the uvm_reg class, and the register model abstracts a hierarchical register list, and the address, domain, attribute and other information contained in the list are consistent with the register content in the communication system. In particular, the register model is connected to the bus agent through the bridging function of the internal bus adapter and is successfully integrated in the verification environment of the codec circuit design; the implementation methods of each sub-reference model N and the Top reference model include but are not limited to the C language reference model, the systemC reference model, the matlab reference model and the like; each sub-scoreboard N and the Top scoreboard are derived from the uvm_scoreboard class, which compares the output from the reference model with the output behavior of each sub-output agent to determine whether the system design circuit meets the specification requirements;

[0104] Step 2: Generate transaction stimuli, including directional and randomly constrained transaction stimuli. According to the design specification requirements, it is a random transaction stimulus that traverses all frequency bands, basic modes and extended modes, and functional requirements, and contains boundary conditions and abnormal conditions such as large signals, small signals, and signals under different SNR conditions for performance testing.

[0105] Step 3: The virtual sequencer receives the generated transaction stimulus and sends it to the subsequencer Bus in the bus agent component;

[0106] Step 4: Determine whether the input agent in each sub-environment N_env in the verification environment is activated. Since the input agent in each sub-environment N_env has been set to be inactive in step 1, the input agent in each sub-environment N_env is in an inactive state;

[0107] Step 5: The sequencer Bus in the bus agent receives the corresponding transaction stimulus sent by the virtual sequencer. The monitors in the input and output agents in the sub-environment N_env are started respectively, wherein the data monitored by the input agent is transmitted to the corresponding reference model at the transaction level through the TLM port, and the data monitored by the output agent is transmitted to the corresponding scoreboard at the transaction level through the TLM port;

[0108] Step 6: Start the driver Bus in the bus agent, get the transaction stimulus from the sequencer Bus through the TLM port, and drive the transaction level stimulus to the corresponding interface at the signal level to realize the driving of the communication system bus;

[0109] Step 7, respectively start the monitors in the input and output agents in the inactivated sub-environment, wherein the data monitored by the input agent is transmitted to the corresponding reference model at the transaction level through the TLM port, and the data monitored by the output agent is transmitted to the corresponding scoreboard at the transaction level through the TLM port;

[0110] Step 8: Each sub-reference model and the Top reference model processes the acquired transaction by simulating its corresponding circuit function to obtain the expected output results, and transmits these results to the corresponding scoreboard.

[0111] Step 9: each sub-environment scoreboard and the top scoreboard receive the expected output result and the actual circuit output result; optionally, the scoreboard component may include a function coverage module; the function coverage module is used to determine the function coverage of the communication system based on the verification result. The completeness of the verification is judged by the coverage.

[0112] Step 10, when the communication system acts as a transmitter: the scoreboard adopts a fuzzy comparison verification strategy, that is, the signal to quantization noise ratio SQNR is used for comparison. In the communication system, since the actual hardware calculation uses fixed-point numbers, while the reference model calculation uses floating-point numbers, quantization errors will occur during the calculation process, resulting in errors between the hardware output results and the reference model output results. Calculating the SQNR when the communication system acts as a transmitter is to measure the signal-to-noise ratio between the actual hardware output results and its reference model output results. The specific calculation process is as follows:

[0113] Calculate the error of each point: Match each point of the model output sequence with the hardware output sequence one by one, and calculate the difference (i.e. error) between them error[n]

[0114] Calculate the noise power: add up the squares of the amplitudes of all error points and divide by the number of error points to get the noise power Pn.

[0115]

[0116] Where |error[n]| represents the magnitude of error point n, and N represents the number of error points.

[0117] Calculate the signal power: add up the square of the amplitude of each point in the model output sequence, and then divide by the number of points to get the signal power Ps.

[0118]

[0119] Here, |signal[n]| represents the amplitude of the nth point in the output sequence, and N represents the number of points in the output sequence.

[0120] Calculate SQNR: Divide the signal power by the noise power and take 10 times the logarithm to get the SQNR value.

[0121]

[0122] In this example, the SQNR threshold is set to 40dB, that is, when the SQNR is greater than 40dB, it indicates that the verification is passed and the communication system to be verified meets the design specifications; otherwise, it indicates that the verification has failed and the communication system to be verified does not meet the design specifications. In particular, when the traditional bit-level precise comparison is used for verification, the reference model needs to be calculated using the same fixed-point or floating-point rules as the communication system hardware to be verified. The disadvantages are: spending too much time on the development of the verification platform instead of focusing on the development of test examples, and failing to discover over-design of the communication system, resulting in excess performance.

[0123] When the communication system acts as the receiving end: by setting the SQNR threshold and the accuracy of decoding the frame control data and payload data information, it is determined whether the communication system to be verified meets the design specifications.

[0124] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium can store a computer program, and the computer program can run the invention content of a UVM-based communication system functional performance collaborative verification architecture and method provided by the present invention and some or all of the steps in each embodiment when executed by the data processing unit. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0125] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on such an understanding, the technical solutions in the embodiments of the present invention can be essentially or partly contributed to the prior art in the form of computer programs, i.e., software products, which can be stored in a storage medium and include several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, an MCU or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0126] The present invention provides a kind of communication system functional performance collaborative verification framework and method based on UVM, and there are many methods and approaches to specifically realize the technical scheme, and the above is only a preferred implementation mode of the present invention, and it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and embellishments can also be made, and these improvements and embellishments should also be regarded as the protection scope of the present invention. Each component that is not clear in the present embodiment can be realized by prior art.

Claims

1. A UVM-based communication system functional performance collaborative verification architecture, characterized in that: include: A communication system design Top DUT to be tested, a top-level verification environment Top_env and an interface, wherein the communication system design Top DUT to be tested and the top-level verification environment Top_env are connected through the interface and communicate with each other; The communication system design Top DUT to be tested includes N sub-modules to be tested and a group of registers for storing control information of the sub-modules to be tested and working status information of the sub-modules to be tested; The top-level verification environment Top_env includes: N verification sub-environments correspond one-to-one to the N sub-modules to be tested in the communication system design Top DUT to be tested, and verify them; A Top reference model is a model used to simulate the behavior of the communication system to be tested, providing a standard for the verification result comparison; A Top scoreboard, which is used to collect and analyze the expected output behavior of the Top reference model and the actual output behavior of the communication system under test, calculate the difference between the actual output data and the expected output data and the system performance indicators, and generate reports; A register model is used to describe and simulate registers and register fields in the communication system to be tested. The top-level verification environment Top_env interacts with the registers in the communication system to be tested and verifies the registers in the communication system to be tested by reading, writing and modifying the values ​​of the register model. a virtual sequencer to provide a unified control and coordination interface for managing and coordinating the generation, execution, and analysis of multiple test transaction stimulus sequences; and a bus agent for modeling and verifying the bus protocol supported in the communication system under test, and generating, controlling and analyzing the bus communication behavior in the communication system under test.

2. According to a UVM-based communication system functional performance collaborative verification architecture described in claim 1, it is characterized in that, Each of the N verification sub-environments includes: A reference model is used to simulate the hardware behavior of the corresponding sub-module under test and provide a standard for the verification of the corresponding sub-module under test; A scoreboard that collects and analyzes the expected output behavior of the reference model and the actual output behavior of the submodule under test, calculates the difference between the actual output data and the expected output data, and generates a report; an input agent to simulate, generate, and validate input signals; and an output agent to monitor, analyze, and verify the output behavior in the submodule under test; Among them, the input agent transmits the generated input signal to the sub-module under test through the interface; the input agent hands over the monitored input signal of the sub-module under test to the reference model for processing, and the reference model sends the expected output behavior to the scoreboard; the output agent obtains the actual output data behavior of the sub-module under test from the interface and hands it over to the scoreboard for processing.

3. According to a kind of UVM-based communication system functional performance collaborative verification architecture described in claim 2, it is characterized in that, The input agent comprises: The sequencer is responsible for controlling and generating transaction stimulus sequences and passing the transaction stimulus sequences to the driver; The driver is used to control the input transaction stimulus sequence and convert the transaction level to the signal level; simulate the data signal exchange between the submodule to be tested and the verification environment to verify the submodule to be tested; and a first monitor, for monitoring and capturing input signals of the submodule under test during the operation of the verification work; The output agent includes: a second monitor for monitoring and capturing the output behavior of the submodule to be tested during the verification work operation.

4. A UVM-based communication system functional performance collaborative verification method, using the UVM-based communication system functional performance collaborative verification architecture described in claim 3 to perform function and performance collaborative verification on the communication system, characterized in that: include: Step 1, initializing the verification architecture of the communication system; Step 2, generating transaction incentives according to the test examples of functions and performances corresponding to the communication system, including directed and randomly constrained transaction incentives; Step 3, the virtual sequencer receives the generated transaction stimulus and coordinates and sends the transaction stimulus to the sequencers in each verification sub-environment; Step 4, determining whether the input agent of each verification sub-environment in the verification architecture is activated, if so, executing step 5, otherwise executing step 6; Step 5, verify that the sequencer in the sub-environment receives the corresponding transaction stimulus sent by the virtual sequencer, and execute step 7; Step 6, respectively starting the first monitor and the second monitor in the verification sub-environment, wherein: the data monitored by the first monitor is transmitted to the reference model in the corresponding sub-verification environment; the data monitored by the second monitor is transmitted to the scoreboard in the corresponding sub-verification environment; Step 7, starting the driver in each verification sub-environment of the activated input agent, obtaining the transaction stimulus from the sequencer in the verification sub-environment, and driving the transaction stimulus to the interface; Step 8: The reference model and the Top reference model in each verification sub-environment process the transaction stimulus obtained from the monitor through their own simulation circuit behavior to obtain the expected output result, and transmit the result to the scoreboard and the Top scoreboard in each verification sub-environment; Step 9: Use the function and performance collaborative verification strategy to compare the expected output behavior with the actual output behavior of the communication system to complete the verification of the communication system.

5. According to a kind of communication system functional performance collaborative verification method based on UVM described in claim 4, it is characterized in that, The transaction stimulus described in step 2 is a random transaction stimulus that traverses all communication frequency bands, modes, and functional requirements and includes different signal boundary conditions and abnormal conditions for performance testing.

6. According to a kind of communication system functional performance collaborative verification method based on UVM described in claim 5, it is characterized in that, The functional and performance co-verification strategy described in step 9 is to use the signal to quantization noise ratio SQNR to compare system performance.

7. A UVM-based communication system functional performance collaborative verification method according to claim 6, characterized in that: The functional and performance collaborative verification strategy specifically includes: Calculate the error of each point: match each point in the expected output result sequence with the actual output result sequence one by one, calculate the difference, that is, the error, and use error[n] to represent the error of the nth point, where N represents the total number of points; Calculate the noise power: add up the squares of the amplitudes of all error points and divide by the number of error points N to get the noise power Pn, as follows: Calculate the signal power: add up the squares of the amplitudes of each point in the expected output sequence, and divide by the number of points to get the signal power Ps, as follows: Calculate SQNR: Divide the signal power by the noise power, and then take 10 times the logarithm to get the SQNR value, as follows: A SQNR threshold is preset, that is, when the SQNR is greater than the threshold, it indicates that the performance of the communication system to be tested meets the system design requirements and the verification is passed, otherwise it is failed.

8. According to a UVM-based communication system functional performance collaborative verification architecture described in claim 1, it is characterized in that, The verification of the register in the communication system to be tested at least includes verifying the behavior and response of the register, and the correctness and consistency of the register under different operations.

9. According to a UVM-based communication system functional performance collaborative verification architecture described in claim 1, it is characterized in that, The verification of the bus communication in the communication system to be tested is to ensure the correctness and consistency of the bus communication in different operation modes.

10. According to a UVM-based communication system functional performance collaborative verification architecture described in claim 3, it is characterized in that, The verification of the submodule to be tested at least includes verifying the response correctness, function and performance of the submodule to be tested.

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