Manufacturing method of semiconductor device
By forming a protective layer in the semiconductor device to cover the first part of the side wall of the work function layer and removing the second hard mask layer under the cover, the problem of damage to the side walls by the etchant is solved, and the performance of the transistor and the semiconductor device is improved.
Patent Information
- Application Number
- CN202311137232.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-05
- Publication Date
- 2025-03-14
AI Technical Summary
After removing the second portion of the work function layer in the semiconductor device, the etchant may cause damage to it through the remaining first portion sidewalls, resulting in poor transistor performance.
After removing the second portion of the work function layer, a protective layer covering at least the first portion of the side wall is formed, and the second hard mask layer is removed with the protective layer covering to prevent damage to the first portion of the side wall.
By covering the protective layer, the etchant is effectively prevented from causing damage to the first part of the side wall of the work function layer, thereby improving the performance of the transistor formed based on the first region, and thus improving the overall performance of the semiconductor device.
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Figure CN119630048A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art
[0002] In the related art, corresponding work function layers are formed in different types of transistors to improve the performance of the transistors. Summary of the invention
[0003] According to one aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate structure, the substrate structure comprising: a substrate, comprising a first region and a second region for different types of transistors, a plurality of fins spaced apart on the substrate, an etch stop layer on the plurality of fins, a work function layer on the etch stop layer, the work function layer comprising a first portion on the first region and a second portion on the second region, and a patterned hard mask layer, the hard mask layer comprising a first hard mask layer and a second hard mask layer on the first hard mask layer, the hard mask layer having an opening, the opening exposing the second portion; removing the second portion with the etch stop layer as a stop layer so that the sidewalls of the first portion are exposed; forming a protective layer covering at least the sidewalls; and removing the second hard mask layer after forming the protective layer.
[0004] According to another aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate structure, the substrate structure comprising: a substrate, comprising a first region and a second region for different types of transistors, a plurality of fins spaced apart on the substrate, a work function layer on the plurality of fins, the work function layer comprising a first portion on the first region and a second portion on the second region, and a patterned hard mask layer, the hard mask layer comprising a first hard mask layer and a second hard mask layer on the first hard mask layer, the hard mask layer having an opening, the opening exposing the second portion; removing the second portion to expose the sidewalls of the first portion; forming a protective layer covering at least the sidewalls; and removing the second hard mask layer after forming the protective layer.
[0005] In some embodiments, the protection layer further covers the fins among the plurality of fins on the second region.
[0006] In some embodiments, the protection layer fills at least a portion of the opening, and an upper surface of the protection layer is higher than an upper surface of the fins on the second region among the plurality of fins.
[0007] In some embodiments, the protective layer completely fills the opening.
[0008] In some embodiments, the protection layer further covers the second hard mask layer.
[0009] In some embodiments, after forming the protection layer, removing the second hard mask layer includes: performing a first etching process to remove a portion of the protection layer located on the second hard mask layer and the second hard mask layer.
[0010] In some embodiments, the method further includes: after removing the second hard mask layer, performing a second etching process to remove remaining portions of the first hard mask layer and the protection layer.
[0011] In some embodiments, the first etching process includes a dry etching process.
[0012] In some embodiments, a thickness of a portion of the protection layer on the second hard mask layer is 30 nanometers to 200 nanometers.
[0013] In some embodiments, the protection layer only fills a portion of the opening, and a distance between an upper surface of the protection layer and an upper surface of the second hard mask layer is less than or equal to 50 nanometers.
[0014] In some embodiments, the first hard mask layer and the protection layer are made of the same material.
[0015] In some embodiments, the material of the second hard mask layer includes silicon oxide.
[0016] In some embodiments, the first region is a region for a P-type transistor, and the second region is a region for an N-type transistor.
[0017] In some embodiments, the material of the work function layer includes metal nitride.
[0018] In the method for manufacturing a semiconductor device provided by an embodiment of the present disclosure, after removing the second portion of the work function layer on the second region, a protective layer is first formed to cover at least the exposed sidewalls of the first portion of the work function layer remaining on the first region, and then the second hard mask layer is removed when the sidewalls are covered by the protective layer. In this way, the etchant used in the process of removing the second hard mask layer can be prevented from damaging the first portion through the exposed sidewalls of the first portion of the work function layer. In this way, the performance of the transistor formed based on the first region can be improved.
[0019] Other features, aspects and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings constitute a part of this specification, and illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0021] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:
[0022] Figure 1A to Figure 1C It is a schematic diagram of some stages of a method for manufacturing a semiconductor device in the related art;
[0023] Figure 2 is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
[0024] Figure 3 to Figure 6B Schematic diagrams of some stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.
[0025] It should be understood that the size of each part shown in the accompanying drawings is not necessarily drawn according to the actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION
[0026] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.
[0027] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprises" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0028] In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be an intermediate component between the specific component and the first component or the second component. When a specific component is described as being connected to other components, the specific component may be directly connected to the other components without an intermediate component, or may not be directly connected to the other components but have an intermediate component.
[0029] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries, such as general dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.
[0030] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.
[0031] Figure 1A to Figure 1C The present invention is a schematic diagram of some stages of a method for manufacturing a semiconductor device in the related art.
[0032] First, if Figure 1A As shown, a first hard mask material layer 1141', a second hard mask material layer 1142', an anti-reflective layer 121 and a patterned photoresist 122 are sequentially formed on the work function layer 113 on the plurality of fins 112 spaced apart on the substrate 111. Here, the work function layer 113 may be formed after removing the dummy gate. The photoresist 122 may define a first region A1 and a second region A2 for different types of transistors in the substrate 111.
[0033] Then, the first hard mask material layer 1141′, the second hard mask material layer 1142′ and the anti-reflection layer 121 are etched using the photoresist 122 as a mask, and the remaining portion of the anti-reflection layer 121 is removed to obtain Figure 1B The patterned first hard mask layer 1141 and the second hard mask layer 1142 are shown. For example, the first hard mask material layer 1141', the second hard mask material layer 1142' and the anti-reflective layer 121 may be etched by a dry etching process.
[0034] The first and second hard mask layers 1141 and 1142 cover a portion 113a (hereinafter referred to as the first portion 113a) of the work function layer 113 on the first region A1 and expose another portion 113b (hereinafter referred to as the second portion 113b) of the work function layer 113 on the second region A2.
[0035] Next, if Figure 1C As shown, the exposed second portion 113 b of the work function layer 113 is removed, and the first portion 113 a of the work function layer 113 remains.
[0036] like Figure 1C As shown, after removing the second portion 113 b of the work function layer 113 , the second hard mask layer 1142 also needs to be removed.
[0037] Through analysis, the etchant (eg, diluted hydrofluoric acid solution) used in the process of removing the second hard mask layer 1142 may damage the work function layer 113a through the exposed portion of the work function layer 113a, thereby resulting in poor performance of the transistor formed based on the first area A1.
[0038] In view of this, the embodiments of the present disclosure propose the following solution, which can improve the performance of semiconductor devices.
[0039] Figure 2 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 3 to Figure 6B Schematic diagrams of some stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.
[0040] Combine the following Figure 2 and Figure 3 to Figure 6B , the manufacturing method of the semiconductor device of some embodiments of the present disclosure is described.
[0041] like Figure 2 As shown, the method for manufacturing a semiconductor device includes steps S202 to S208.
[0042] In step S202, a substrate structure is provided.
[0043] Combine the following Figure 3 The substrate structure of some embodiments of the present disclosure is described. Figure 3 is a schematic cross-sectional view of a substrate structure according to some embodiments of the present disclosure.
[0044] like Figure 3 As shown, the substrate structure 110 includes a substrate 111 , a plurality of fins 112 spaced apart on the substrate 111 , a work function layer 113 on the plurality of fins 112 , and a patterned hard mask layer 114 .
[0045] The substrate 111 includes a first region A1 and a second region A2 for different types of transistors. The first region A1 and the second region A2 may be formed by Figure 1A The photoresist 122 is shown defined.
[0046] As some implementations, the first region A1 is a region for a P-type transistor, and the second region is a region for an N-type transistor. As some other implementations, the first region A1 is a region for an N-type transistor, and the second region is a region for a P-type transistor. The transistor may be, but is not limited to, a fin field effect transistor.
[0047] The substrate 111 may be a semiconductor substrate. The semiconductor substrate may be, for example, silicon (Si), germanium (Ge) or other element semiconductor substrates, or may be a compound semiconductor substrate such as gallium arsenide (GaAs). The material of the fin 112 may be the same as or different from that of the substrate 111.
[0048] The fins 112 may be formed in a variety of ways. As some implementations, a plurality of fins 112 are integrally provided with the substrate 111. For example, the substrate material may be etched to obtain an integrally provided substrate 111 and a plurality of fins 112. As other implementations, the plurality of fins 112 are non-integrally provided with the substrate 111. For example, a fin material may be formed on the substrate 111, and then the fin material may be patterned to form non-integrally provided fins 112 and substrate 111. For example, the fin material may be patterned by a self-aligned double patterning (SADP) process to obtain a smaller fin 112.
[0049] See also Figure 3 The work function layer 113 includes a first portion 113a on the first area A1 and a second portion 113b on the second area A2. The patterned hard mask layer 114 includes a first hard mask layer 1141 and a second hard mask layer 1142 on the first hard mask layer 1141. The hard mask layer 114 has an opening V, and the opening V exposes the second portion 113b of the work function layer 113 on the second area A2.
[0050] In some embodiments, the first hard mask layer 1141 and the second hard mask layer 1142 may be formed according to Figure 1A to Figure 1B In this case, the thickness of the second hard mask material layer 1142 ′ is less than the thickness of the anti-reflection layer 121 .
[0051] By forming a second hard mask material layer 1142' with a smaller thickness on the first hard mask material layer 1141' instead of directly forming a thicker anti-reflection layer 121 on the first hard mask material layer 1141', the etchant used in the process of removing the thicker anti-reflection layer 121 can be prevented from damaging the pattern of the first hard mask layer 1141, so that the first hard mask layer 1141 can better protect the first portion 113a when the second portion 113b is subsequently removed. In this way, the performance of the transistor formed based on the first area A1 can be improved, thereby improving the performance of the semiconductor device.
[0052] In some embodiments, the material of the work function layer 113 may include metal nitride, for example, titanium nitride (TiN).
[0053] In some embodiments, the first hard mask layer 1141 may include a carbon layer formed by a spin coating process, ie, a spin-on carbon layer.
[0054] In some embodiments, the material of the second hard mask layer 1142 includes silicon oxide (SiO2). Figure 1A A low temperature silicon oxide layer may be grown on the first hard mask material layer 1141 ′ to obtain a second hard mask material layer 1142 ′. In this case, the material of the second hard mask layer 1142 includes low temperature grown silicon oxide.
[0055] In some embodiments, see Figure 3 The substrate structure 110 further includes a plurality of isolation regions 115 spaced apart on the substrate 111. The fin 112 may protrude from between two adjacent isolation regions 115. The material of the isolation region 115 may include, but is not limited to, silicon oxide, such as silicon oxide.
[0056] In some embodiments, see Figure 3 , the substrate structure 110 also includes Figure 3 An etch stop layer 116 is shown. The etch stop layer 116 is on the plurality of fins 112 , and the work function layer 113 is on the etch stop layer 116 .
[0057] For example, see Figure 3 The etch stop layer 116 may cover the upper surface of the isolation region 115 and portions of the plurality of fins 112 protruding from the isolation region 115 , and the work function layer 113 may cover the etch stop layer 116 .
[0058] As some implementations, the material of the etch stop layer 116 may include tantalum nitride (TaN).
[0059] In some embodiments, see Figure 3 The substrate structure 110 further includes a blocking member 117 for blocking the gate. The material of the blocking member 117 may include silicon oxide, silicon nitride, silicon carbonitride, silicon carbon nitride, etc. The silicon oxide may be, for example, silicon oxide. The silicon nitride may be, for example, silicon nitride (Si3N4). The silicon carbonitride may be, for example, silicon carbon nitride (SiCN). The silicon carbon nitride may be, for example, silicon oxycarbonitride (SiOCN).
[0060] Next, in step S204 , the second portion of the work function layer is removed to expose the sidewall of the first portion of the work function layer.
[0061] Figure 4 is a schematic cross-sectional view of a substrate structure after the second portion of the work function layer is removed according to some embodiments of the present disclosure.
[0062] In some embodiments, the work function layer 113 may be etched using the hard mask layer 114 as a mask to remove the second portion 113 b of the work function layer 113 , thereby exposing the sidewall SW of the first portion 113 a of the work function layer 113 .
[0063] As some implementations, the work function layer 113 may be etched by a dry etching process or a wet etching process to remove the second portion 113 b of the work function layer 113 .
[0064] Taking the case where the material of the work function layer 113 includes titanium nitride as an example, an etchant such as phosphoric acid or SC2 cleaning solution may be used to remove the exposed second portion 113 b of the work function layer 113 .
[0065] In some embodiments, when the substrate structure 110 includes an etch stop layer 116, the second portion 113b of the work function layer 113 may be removed using the etch stop layer 116 as a stop layer, so that the sidewall SW of the first portion 113a is exposed, and the upper surface of the portion of the etch stop layer 116 on the second region A2 is exposed. In this way, the fin 112 on the second region A2 may be prevented from being damaged during the process of removing the second portion 113b of the work function layer 113, thereby improving the performance of the transistor formed based on the second region A2, and further improving the performance of the semiconductor device.
[0066] Next, in step S206 , a protection layer is formed to at least cover the sidewalls.
[0067] The protective layer covering the side wall can be realized in various ways, which will be described below in conjunction with some embodiments.
[0068] Then, in step S208 , after forming the protection layer, the second hard mask layer is removed.
[0069] In the above embodiment, after removing the second portion 113b of the work function layer 113 on the second region A2, a protective layer is first formed to cover at least the sidewall SW exposed by the first portion 113a of the work function layer 113 remaining on the first region A1, and then the second hard mask layer 1142 is removed when the sidewall SW is covered by the protective layer. In this way, the etchant used in the process of removing the second hard mask layer 1142 can be prevented from damaging the first portion 113a through the sidewall SW exposed by the first portion 113a of the work function layer 113. In this way, the performance of the transistor formed based on the first region A1 can be improved, thereby improving the performance of the semiconductor device.
[0070] In some embodiments, the first region A1 is a region for a P-type transistor, the second region A2 is a region for an N-type transistor, and the material of the work function layer 113 includes titanium nitride. Thus, the work function layer including titanium nitride can be formed only in the region for the P-type transistor.
[0071] In some embodiments, the protection layer formed in step S206 also covers the fins 112 on the second area A2 among the plurality of fins 112 .
[0072] In this way, the damage caused to the fin 112 on the second region A2 by the etchant used in the process of removing the second hard mask layer 1142 can be reduced, thereby improving the performance of the transistor formed based on the second region A2 and further improving the performance of the semiconductor device.
[0073] For ease of understanding, the following Figure 5A and 5B The protective layer formed in step S206 is further described. Figure 5A to Figure 5B It is a schematic diagram of the structure of a protective layer formed according to some embodiments of the present disclosure.
[0074] In some embodiments, see Figure 5A to Figure 5B The protection layer 130 fills at least a portion of the opening V, and an upper surface of the protection layer 130 is higher than an upper surface of the fin 112 on the second area A2 among the plurality of fins 112 .
[0075] In this way, damage to the first part 113a can be more effectively prevented, and the damage caused to the fin 112 on the second area A2 by the etchant used in the process of removing the second hard mask layer 1142 can be further reduced, thereby further improving the performance of the transistor formed based on the second area A2, and further improving the performance of the semiconductor device.
[0076] For some implementations, see Figure 5A , the protection layer 130 only fills the portion of the opening V, and the distance between the upper surface of the protection layer 130 and the upper surface of the second hard mask layer 1142 is less than or equal to 50 nanometers, for example, 20 nanometers, 30 nanometers or 40 nanometers. In this way, damage to the first portion 113a can be more effectively prevented, and damage to the fin 112 on the second area A2 caused by the etchant used in the process of removing the second hard mask layer 1142 can be further reduced, so that the performance of the transistor formed based on the second area A2 can be further improved, and the performance of the semiconductor device can be further improved.
[0077] As some other implementations, the protection layer 130 completely fills the opening V.
[0078] For example, the upper surface of the protection layer 130 may be flush with the upper surface of the second hard mask layer 1142. It should be noted that the "flush" mentioned herein refers to flushness within the semiconductor process deviation range.
[0079] Due to the viscosity of the material of the protective layer 130 , there may be a gap between the protective layer 130 and a part of the opening V (for example, in the angle area formed by the fin 112 and the isolation area 115 ). It should be understood that this situation also refers to the situation where the protective layer 130 completely fills the opening V.
[0080] The protective layer 130 completely fills the opening V, which can more effectively prevent damage to the first part 113a and can further reduce the damage caused to the fin 112 on the second area A2 by the etchant used in the process of removing the second hard mask layer 1142, thereby further improving the performance of the transistor formed based on the second area A2, and further improving the performance of the semiconductor device.
[0081] For some other implementations, see Figure 5B , the protection layer 130 completely fills the opening V and also covers the second hard mask layer 1142. In this way, the difficulty of estimating the amount of etchant used in the process of removing the second hard mask layer 1142 can be reduced. In this way, the damage caused to the fin 112 on the second area A2 by the etchant used in the process of removing the second hard mask layer 1142 can be further reduced, and the manufacturing difficulty can be reduced.
[0082] In some embodiments, when the protection layer 130 completely fills the opening V and also covers the second hard mask layer 1142 , the thickness of the portion of the protection layer 130 on the second hard mask layer 1142 is 30 nm to 200 nm, for example, 50 nm, 100 nm or 120 nm.
[0083] The protective layer 130 having a certain thickness formed on the second hard mask layer 1142 can reduce the process difficulty of forming the protective layer 130 while further reducing the damage caused to the fin 112 on the second area A2 by the etchant used in the process of removing the second hard mask layer 1142, thereby reducing the manufacturing difficulty of the semiconductor device.
[0084] Combine the following Fig. 6A and 6B In the formation Figure 5B The process flow of some embodiments after the protective layer 130 is shown will be described.
[0085] like Fig. 6AAs shown, after forming the protection layer 130 filling the opening V and covering the second hard mask layer 1142 , a first etching process may be performed to remove the portion of the protection layer 130 located on the second hard mask layer 1142 and the second hard mask layer 1142 .
[0086] It is understood that when the second hard mask layer 1142 is removed, a portion of the first hard mask layer 1141 may also be removed.
[0087] In some embodiments, the first etching process includes a dry etching process or a wet etching process.
[0088] As some implementations, the first etching process includes a dry etching process. By using the dry etching process to remove the portion of the protective layer 130 located on the second hard mask layer 1142 and the second hard mask layer 1142, the amount of the etchant used in the process of removing the second hard mask layer 1142 can be more accurately controlled, which is more conducive to making the etchant just etch away the second hard mask layer 1142.
[0089] Next, if Figure 6B As shown, after removing the second hard mask layer 1142 , a second etching process may be performed to remove the first hard mask layer 1141 and the remaining portion 130 a of the protection layer 130 .
[0090] In some embodiments, the second etching process includes a dry etching process or a wet etching process.
[0091] In this way, the first hard mask layer 1141, the second hard mask layer 1142 and the protective layer 130 can be removed by performing a first etching process and a second etching process. In this way, the process flow can be simplified and the manufacturing cost can be reduced.
[0092] In some embodiments, the first hard mask layer 1141 and the protective layer 130 are made of the same material. For example, the first hard mask layer 1141 and the protective layer 130 both include a spin-on carbon layer. In this way, the same etchant can be used to remove the remaining portion 130a of the first hard mask layer 1141 and the protective layer 130, thereby further simplifying the process flow and improving manufacturing efficiency.
[0093] In subsequent processes, a work function layer for a corresponding type of transistor may be formed on the fin 112 on the second area A2 of the substrate 111 , and then a metal gate across the fin 112 may be formed, which will not be described in detail herein.
[0094] The method for manufacturing a semiconductor device according to the embodiment of the present disclosure may be applied to, but is not limited to, a replacement metal gate (RMG) process of 10 nanometers or less.
[0095] So far, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution disclosed here.
[0096] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, comprising: A substrate structure is provided, the substrate structure comprising: a substrate including a first region and a second region for transistors of different types, a plurality of fins spaced apart on the substrate, an etch stop layer on the plurality of fins, a work function layer on the etch stop layer, the work function layer comprising a first portion on the first region and a second portion on the second region, and a patterned hard mask layer, the hard mask layer comprising a first hard mask layer and a second hard mask layer on the first hard mask layer, the hard mask layer having an opening, the opening exposing the second portion; removing the second portion by using the etching stop layer as a stop layer, so that the sidewall of the first portion is exposed; forming a protective layer covering at least the side wall; and After forming the protection layer, the second hard mask layer is removed.
2. A method for manufacturing a semiconductor device, comprising: A substrate structure is provided, the substrate structure comprising: a substrate including a first region and a second region for transistors of different types, a plurality of fins spaced apart on the substrate, a work function layer on the plurality of fins, the work function layer comprising a first portion on the first region and a second portion on the second region, and a patterned hard mask layer, the hard mask layer comprising a first hard mask layer and a second hard mask layer on the first hard mask layer, the hard mask layer having an opening, the opening exposing the second portion; removing the second portion so that the side wall of the first portion is exposed; forming a protective layer covering at least the side wall; and After forming the protection layer, the second hard mask layer is removed.
3. The method according to claim 1 or 2, wherein: The protection layer also covers the fins on the second region among the plurality of fins.
4. The method according to claim 3, wherein: The protection layer fills at least a portion of the opening, and an upper surface of the protection layer is higher than an upper surface of the fins on the second region among the plurality of fins.
5. The method according to claim 4, wherein: The protective layer completely fills the opening.
6. The method according to claim 5, wherein: The protection layer also covers the second hard mask layer.
7. The method according to claim 6, wherein: After forming the protection layer, removing the second hard mask layer comprises: A first etching process is performed to remove a portion of the protection layer located on the second hard mask layer and the second hard mask layer.
8. The method according to claim 7, further comprising: After removing the second hard mask layer, a second etching process is performed to remove the remaining portion of the first hard mask layer and the protection layer.
9. The method according to claim 7, wherein: The first etching process includes a dry etching process.
10. The method according to claim 6, wherein: A thickness of a portion of the protection layer on the second hard mask layer is 30 nanometers to 200 nanometers.
11. The method according to claim 4, wherein: The protection layer only fills a portion of the opening, and a distance between an upper surface of the protection layer and an upper surface of the second hard mask layer is less than or equal to 50 nanometers.
12. The method according to claim 1 or 2, wherein: The first hard mask layer and the protection layer are made of the same material.
13. The method according to claim 1 or 2, wherein: The material of the second hard mask layer includes silicon oxide.
14. The method according to claim 1 or 2, wherein: The first region is a region for a P-type transistor, and the second region is a region for an N-type transistor.
15. The method according to claim 1 or 2, wherein: The material of the work function layer includes metal nitride.