RC-IGBT device preparation method and RC-IGBT device

Abstract

The invention relates to a preparation method of an RC-IGBT device and the RC-IGBT device, and belongs to the technical field of semiconductors. Comprising the following steps: forming a gate electrode, an emitter and a diode anode of the RC-IGBT device on the surface of one side of an epitaxial layer; injecting protons into the surface of one side, far away from the gate electrode, the emitter and the diode anode, of the epitaxial layer to form a composite epitaxial layer; forming a first drift region on the surface of one side, far away from the gate electrode, the emitter and the diode anode, of the composite epitaxial layer; forming a second drift region on the surface of one side, away from the composite epitaxial layer, of the first drift region; and forming a collector electrode and a diode cathode of the RC-IGBT device on the surface of one side, far away from the first drift region, of the second drift region. The diode is constructed in the IGBT device in a proton injection mode, the reverse recovery performance of the diode can be improved without controlling the service life of a carrier, and the performance of the IGBT and the reverse recovery performance of the diode are both considered.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing an RC-IGBT device and the RC-IGBT device. Background Art

[0002] Insulated-Gate Bipolar Transistor (IGBT), as a widely used power electronic device, usually requires an anti-parallel diode to release current. However, in actual production and use, the anti-parallel diode not only requires additional packaging, has additional wire bonding, introduces parasitic inductance and parasitic resistance, but also occupies additional packaging area. Therefore, the reverse conducting insulated gate bipolar transistor (RC-IGBT) was proposed. RC-IGBT integrates IGBT and reverse diode on one chip, which not only reduces the chip packaging size and cost, but also improves the reliability and power density of the device, playing an important role in the miniaturization and efficiency of power electronic equipment.

[0003] Since the collector of an IGBT device is usually a P-type semiconductor region, a conventional RC-IGBT forms an N+ region by injecting strip-shaped N+ ions into the back of the IGBT device, so that the N+ region forms a PN junction with the P-type collector, thereby realizing the function of a diode in the IGBT. However, the injection of N+ ions will increase the concentration of carriers. During the reverse recovery process of the diode, these additional injected carriers will cause more charge storage, which will take longer to dissipate the stored charge, prolonging the reverse recovery time of the diode and increasing the energy loss of the reverse recovery process. In order to improve the reverse recovery performance of the diode, it is usually necessary to electron irradiate the entire back of the RC-IGBT device, thereby reducing the carrier lifetime in the device and reducing the reverse recovery charge of the diode. However, the reduction in carrier lifetime will result in a reduction in the number of carriers available for conduction in the on-state of the IGBT, increasing the on-resistance and energy loss of the IGBT, thereby reducing the performance of the IGBT.

[0004] In summary, the RC-IGBT device prepared by the method of integrating a diode in an IGBT device by injecting N+ ions in the prior art cannot take into account both the performance of the IGBT and the reverse recovery performance of the diode. Summary of the invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the problem that the RC-IGBT device prepared by the ion implantation method in the prior art cannot take into account both the performance of the IGBT and the reverse recovery performance of the diode.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing an RC-IGBT device, comprising: Forming a gate electrode, an emitter and a diode anode of the RC-IGBT device on a surface of one side of the epitaxial layer; Injecting protons into the surface of the epitaxial layer away from the gate electrode, the emitter and the diode anode to form a composite epitaxial layer; Forming a first drift region on a surface of the composite epitaxial layer away from the gate electrode, the emitter and the diode anode; forming a second drift region on a surface of the first drift region away from the composite epitaxial layer; A collector electrode and a diode cathode of the RC-IGBT device are formed on a surface of the second drift region which is away from the first drift region.

[0007] Preferably, injecting protons into a surface of the epitaxial layer away from the gate electrode, the emitter and the diode anode comprises: Prepare a photolithography plate, wherein the photolithography plate includes a plurality of through holes arranged in an array; Protons are injected into the surface of the epitaxial layer away from the gate electrode, the emitter and the diode anode through a plurality of through holes on the photolithography plate.

[0008] Preferably, the shape of the through hole includes rectangle, circle and polygon.

[0009] Preferably, forming a gate electrode, an emitter and a diode anode of the RC-IGBT device on a surface of one side of the epitaxial layer comprises: Performing ion implantation on the epitaxial layer to form a buffer layer on a side of the epitaxial layer away from the first drift region; Etching the buffer layer and a portion of the epitaxial layer to form a first trench and a second trench; forming a first gate electrode and a second gate electrode in the first trench and the second trench respectively; Performing ion implantation on the buffer layer located on the side of the first gate electrode away from the second gate electrode and the buffer layer located between the first gate electrode and the second gate electrode, respectively, to form a P-type body region on the side of the buffer layer away from the epitaxial layer; Performing ion implantation on the buffer layer located on the side of the second gate electrode away from the first gate electrode to form a P-type anode region; wherein the thickness of the P-type anode region is the same as the thickness of the buffer layer; Performing ion implantation on the P-type body region and the P-type anode region respectively, forming an IGBT conductive region on a side of the P-type body region away from the buffer layer, and forming a diode anode conductive region on a side of the P-type anode region away from the epitaxial layer; Forming an ILD oxide layer on the surface of the first gate electrode and the second gate electrode away from the epitaxial layer; A first metal layer is deposited on the surface of the IGBT conductive region, the surface of the diode anode conductive region and the surface of the ILD oxide layer.

[0010] Preferably, forming a first gate electrode and a second gate electrode in the first trench and the second trench respectively comprises: Depositing a first gate oxide layer at the bottom and sidewall of the first trench, wherein the first gate oxide layer has a third trench; Filling a first polysilicon layer in the third trench, and depositing a second gate oxide layer on the surface of the first polysilicon layer to obtain a first gate electrode; Depositing a third gate oxide layer at the bottom and sidewall of the second trench, wherein the third gate oxide layer has a fourth trench; A second polysilicon layer is filled in the fourth trench, and a fourth gate oxide layer is deposited on the surface of the second polysilicon layer to obtain a second gate electrode.

[0011] Preferably, forming a P-type body region in the buffer layer on a side away from the epitaxial layer comprises: Performing P-ion implantation on the buffer layer located on the side of the first gate electrode away from the second gate electrode to form a first P-type body region in contact with the first gate electrode on the side of the first gate electrode away from the second gate electrode; P- ion implantation is performed on the buffer layer between the first gate electrode and the second gate electrode to form a second P-type body region between the first gate electrode and the second gate electrode and in contact with the first gate electrode and the second gate electrode.

[0012] Preferably, forming an IGBT conductive region in the P-type body region away from the buffer layer, and forming a diode anode conductive region in the P-type anode region away from the epitaxial layer comprises: Performing N+ ion implantation on the first P-type body region to form a first N+ region in contact with the first gate electrode on a side of the first gate electrode away from the second gate electrode; Performing P+ ion implantation on the first P-type body region to form a first P+ region in contact with the first N+ region on a side of the first N+ region away from the first gate electrode; Performing N+ ion implantation on the second P-type body region to form a second N+ region in contact with the first gate electrode on a side of the first gate electrode close to the second gate electrode; Performing P+ ion implantation on the second P-type body region to form a second P+ region in contact with the second N+ region on a side of the second N+ region away from the first gate electrode; P+ ions are implanted into the P-type anode region to form a third P+ region.

[0013] Preferably, forming a collector electrode and a diode cathode of the RC-IGBT device on a surface of the second drift region away from the first drift region comprises: Performing P-type impurity implantation into the second drift region to form a P-type semiconductor layer on a side of the second drift region away from the first drift region; Injecting N-type impurities into the P-type semiconductor layer to form a diode cathode conductive region in the P-type semiconductor layer; wherein the thickness of the diode cathode conductive region is the same as the thickness of the P-type semiconductor layer; A second metal layer is deposited on a surface of the P-type semiconductor layer away from the second drift region.

[0014] The present invention further provides an RC-IGBT device, which is prepared by the above-mentioned method for preparing the RC-IGBT device, and specifically comprises: Composite epitaxial layer; A gate electrode is arranged on a surface of one side of the composite epitaxial layer; An emitter electrode is arranged on a surface of the composite epitaxial layer on a side where a gate electrode is arranged; A diode anode is arranged on the surface of the composite epitaxial layer on one side where the gate electrode is arranged; A first drift region is arranged on a surface of the composite epitaxial layer away from the gate electrode, the emitter and the diode anode; A second drift region is arranged on a surface of the first drift region away from the composite epitaxial layer; A collector electrode is arranged on a surface of the second drift region away from the first drift region; The diode cathode is arranged on a surface of the second drift region which is away from the first drift region.

[0015] Preferably, the gate electrode comprises a first gate electrode and a second gate electrode, and an ILD oxide layer is disposed on a surface of the first gate electrode and the second gate electrode away from the composite epitaxial layer; The buffer layer of the RC-IGBT device is arranged on a side of the first gate electrode away from the second gate electrode and between the first gate electrode and the second gate electrode; the P-type body region of the RC-IGBT device is arranged on a side of the buffer layer away from the composite epitaxial layer; The IGBT conductive region of the RC-IGBT device is arranged in the P-type body region on a side away from the buffer layer, and specifically includes: A first N+ region is disposed on a side of the first gate electrode away from the second gate electrode and in contact with the first gate electrode; A first P+ region, disposed on a side of the first N+ region away from the first gate electrode and in contact with the first N+ region; A second N+ region is disposed on a side of the first gate electrode close to the second gate electrode and in contact with the first gate electrode; A second P+ region, disposed on a side of the second N+ region away from the first gate electrode and in contact with the second N+ region; The diode anode is arranged on a side of the second gate electrode away from the first gate electrode, and specifically comprises: A P-type anode region is arranged on a surface of the composite epitaxial layer away from the first drift region; A diode anode conductive region is arranged in the P-type anode region at a side away from the composite epitaxial layer; The emitter comprises a first metal layer, which is arranged on the surface of the IGBT conductive region, the surface of the diode anode conductive region and the surface of the ILD oxide layer; The collector comprises: A P-type semiconductor layer is arranged on a side of the second drift region away from the first drift region; A second metal layer is disposed on a side of the P-type semiconductor layer away from the second drift region; The diode cathode includes a diode cathode conductive region, which is disposed in the P-type semiconductor layer; wherein the thickness of the diode cathode conductive region is the same as the thickness of the P-type semiconductor layer.

[0016] The preparation method of the RC-IGBT device provided in this application has the following beneficial effects: 1. By injecting protons on the surface of the epitaxial layer to change the electrical properties of the epitaxial layer, part of the epitaxial layer is transformed into a P-type region, thereby obtaining a composite structure of P-type and N-type doping, that is, a composite epitaxial layer, and forming a first drift region and a second drift region on the surface of the composite epitaxial layer. Due to the N-type characteristics of the drift region, a PN junction is formed at the junction of the drift region and the P-type region in the composite epitaxial layer, thereby forming a diode cathode. By constructing a diode in an IGBT device using proton implantation, the amount of minority carriers stored in the P-type and N-type regions can be reduced. When the diode switches from forward bias to reverse bias, the stored charge that needs to be dissipated is reduced, thereby shortening the reverse recovery time of the diode and reducing the energy consumed by charge recombination during the reverse recovery process. The reverse recovery performance of the diode can be improved without controlling the carrier lifetime, which will not affect the performance of the IGBT. In addition, since protons are heavier than electrons, when protons are irradiated on the back of the device, only the protons accumulated on the back of the device can be regulated to improve the proton lifetime, thereby further reducing the energy loss during the reverse recovery process of the diode and avoiding the problem of IGBT performance degradation caused by shortened carrier lifetime.

[0017] 2. The back structure of the traditional RC-IGBT uses a strip structure to separate the IGBT and diode areas. However, due to the inconsistency of the functions of the IGBT and the diode during actual use, the heat generated in the two areas is also inconsistent, and the maximum junction temperature of the device is limited to the area with high temperature. Therefore, uneven heat dissipation will also limit the scope of use of the device. This application designs a photolithography plate composed of multiple through holes arranged in an array, and localized proton injection is performed on the epitaxial layer through the through holes on the photolithography plate, so that the IGBT area and the diode area are evenly distributed on the back of the device, so that the heat dissipation of different areas of the device diffuses mutually when the device works at different frequencies, thereby raising the junction temperature of the device, so that the device can work at a higher temperature, and broaden the scope of use of the device. In addition, the improvement of heat dissipation performance also optimizes the switching performance of the IGBT and the short-circuit performance of the device; in addition, since the back structure of the device provided by this application reduces the heat dissipation of the device, the volume of the device can be reduced while keeping the short-circuit performance of the device unchanged, thereby reducing the production cost of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein: Figure 1 A flow chart of a method for preparing an RC-IGBT device provided in this application; Figure 2 This is a schematic diagram of the back surface morphology of a traditional RC-IGBT device; Figure 3A schematic diagram of the back side morphology of the RC-IGBT device provided in this application; Figure 4 The front process flow chart of the RC-IGBT device provided in this application; wherein, Figure 4 (a) is a schematic diagram of forming a buffer layer on the epitaxial layer. Figure 4 (b) in Figure 4 Schematic diagram of forming a gate electrode on the structure shown in (a). Figure 4 (c) in Figure 4 Schematic diagram of the formation of a P-type body region on the structure shown in (b). Figure 4 (d) in Figure 4 Schematic diagram of forming a P-type anode region on the structure shown in (c). Figure 4 The (e) in Figure 4 Schematic diagram of forming a conductive area on the structure shown in (d). Figure 4 (f) in Figure 4 Schematic diagram of forming an ILD oxide layer on the structure shown in (e). Figure 4 The (g) in Figure 4 Schematic diagram of forming a first metal layer on (f); Figure 5 A process flow chart for forming a first gate electrode and a second gate electrode in a first trench and a second trench; wherein: Figure 5 (a) is a schematic diagram of forming a first gate oxide layer in the first trench. Figure 5 (b) in Figure 5 Schematic diagram of forming a first polysilicon layer and a second gate oxide layer on the structure shown in (a). Figure 5 (c) is a schematic diagram of forming a third gate oxide layer in the second trench. Figure 5 (d) in Figure 5 Schematic diagram of forming a second polysilicon layer and a fourth gate oxide layer on the structure shown in (c); Figure 6 is a process flow chart for preparing a P-type body region; wherein, Figure 6 (a) is a schematic diagram of forming the first P-type body region in the buffer layer. Figure 6 (b) in Figure 6 Schematic diagram of forming a second P-type body region on the structure shown in (a); Figure 7 The following is a process flow chart for preparing the IGBT conductive area and the diode anode conductive area; wherein: Figure 7 (a) is a schematic diagram of forming a first N+ region in the first P-type body region. Figure 7 (b) in Figure 7 Schematic diagram of forming the first P+ region on the structure shown in (a). Figure 7(c) is a schematic diagram of forming a second N+ region in the second P-type body region. Figure 7 (d) in Figure 7 Schematic diagram of forming a second P+ region on the structure shown in (c). Figure 7 The (e) in Figure 7 Schematic diagram of forming a third P+ region on the structure shown in (d); Figure 8 The back process flow chart of the RC-IGBT device provided in this application; wherein, Figure 8 (a) is a schematic diagram of forming the first drift region on the surface of the composite epitaxial layer. Figure 8 (b) in Figure 8 Schematic diagram of forming a second drift region on the structure shown in (a). Figure 8 (c) in Figure 8 Schematic diagram of forming a P-type semiconductor layer on the structure shown in (b). Figure 8 (d) in Figure 8 Schematic diagram of the cathode conductive region of the diode formed on the structure shown in (c). Figure 8 The (e) in Figure 8 Schematic diagram of forming a second metal layer on the structure shown in (d); Description of the Figures: 1. epitaxial layer; A. composite epitaxial layer; 2. buffer layer; 3. first trench; 4. second trench; 5. first gate electrode; 51. first gate oxide layer; 511. third trench; 52. first polysilicon layer; 53. second gate oxide layer; 6. second gate electrode; 61. third gate oxide layer; 611. fourth trench; 62. second polysilicon layer; 63. fourth gate oxide layer; 7. P-type body region; 71. first A P-type body region; 72, a second P-type body region; 8, a P-type anode region; 9, an IGBT conductive region; 91, a first N+ region; 92, a first P+ region; 93, a second N+ region; 94, a second P+ region; 10, a diode anode conductive region; 11, an ILD oxide layer; 12, a first metal layer; 13, a first drift region; 14, a second drift region; 15, a P-type semiconductor layer; 16, a diode cathode conductive region; 17, a second metal layer. DETAILED DESCRIPTION

[0019] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0020] See also Figure 1 , Figure 1 A flow chart of a method for preparing an RC-IGBT device provided in the present application, the method comprising the following steps: S1: forming a gate electrode, an emitter and a diode anode of the RC-IGBT device on the surface of one side of the epitaxial layer; S2: Protons are injected into the surface of the epitaxial layer away from the gate electrode, the emitter and the diode anode to form a composite epitaxial layer; S3: forming a first drift region on a surface of the composite epitaxial layer away from the gate electrode, the emitter and the diode anode; S4: forming a second drift region on a surface of the first drift region away from the composite epitaxial layer; S5: forming a collector and a diode cathode of the RC-IGBT device on a surface of the second drift region away from the first drift region.

[0021] The present application changes the electrical properties of the epitaxial layer by injecting protons on the surface of the epitaxial layer, so that part of the epitaxial layer is transformed into a P-type region, thereby obtaining a composite structure of P-type and N-type doping, that is, a composite epitaxial layer, and forming a first drift region and a second drift region on the surface of the composite epitaxial layer. Due to the N-type characteristics of the drift region, a PN junction is formed at the junction of the drift region and the P-type region in the composite epitaxial layer, thereby forming a diode cathode. By constructing a diode in an IGBT device by proton injection, the storage amount of minority carriers in the P-type and N-type regions can be reduced. When the diode is switched from forward bias to reverse bias, the stored charge that needs to be dissipated is reduced, thereby shortening the reverse recovery time of the diode, reducing the energy consumed by charge recombination during the reverse recovery process, and improving the reverse recovery performance of the diode without controlling the carrier lifetime. Since the IGBT region is not affected by the carrier lifetime control technology, the performance of the IGBT is lower than the conduction loss and turn-off loss of the IGBT in the traditional RC-IGBT device, effectively improving the performance of the device.

[0022] In addition, by irradiating the back of the device with protons, the overcharge current generated by the diode during the freewheeling process can be reduced. On the one hand, the di / dt of the device when it is turned on can be effectively suppressed. According to the formula It can be seen that when di / dt is suppressed, the gate oscillation generated by the device during switching will decrease, so that the device can work at a lower driving resistance Rg. Furthermore, since the driving resistance is proportional to the switching loss, the turn-on energy loss of the device can be further reduced by proton irradiating the back of the device. On the other hand, the reduction of overcharge current will further reduce the reverse recovery time of the diode, reduce the dead time of the device, and increase the turn-on speed and operating frequency of the device. Furthermore, the reduction of conduction loss and switching loss makes the device energy accumulation speed lower. Under the same packaging and unchanged thermal resistance, the temperature rise rate of the device is slowed down, effectively improving the reliability and service life of the device. In addition, since the weight of protons is greater than that of electrons, when proton irradiating the back of the device, only the protons gathered on the back of the device can be regulated to improve the proton lifetime, avoiding the problem of IGBT performance degradation caused by shortening the carrier lifetime.

[0023] Furthermore, the back side structure of conventional RC-IGBT devices uses a strip structure to separate the IGBT and diode regions, such as Figure 2 As shown in the figure, in actual use, due to the different functions of IGBT and diode, the heat generated by the two functional partitions is also different. The strip partition leads to a large temperature gradient on the back of the device and uneven heat dissipation, and the maximum junction temperature of the entire RC-IGBT device is limited to the area with high temperature rise. Therefore, high heat generation in a single area in the strip structure will make the maximum junction temperature of the device lower, thereby limiting the scope of use of the device.

[0024] Based on this, the present application optimizes device performance through improved structure and morphology, and through the arrangement of IGBT and diode partitions on the back of the RC-IGBT device, the device can achieve uniform heat dissipation during use, reduce the temperature gradient on the back of the device, and thus increase the maximum junction temperature of the device.

[0025] Specifically, injecting protons into the surface of the epitaxial layer away from the gate electrode, the emitter and the diode anode comprises: preparing a photoresist plate, wherein the photoresist plate comprises a plurality of through holes arranged in an array; Protons are injected into the surface of the epitaxial layer away from the gate electrode, the emitter and the diode anode through a plurality of through holes on the photolithography plate.

[0026] Optionally, the shape of the through hole includes rectangle, circle, polygon and the like.

[0027] For example, Figure 3 Two photolithography plates with different through-hole shapes provided by the present application are shown, wherein: Figure 3 (a) is a photolithography plate with rectangular through holes. Figure 3 (b) is a photolithography plate with hexagonal through holes.

[0028] Specifically, the present application performs local proton injection into the epitaxial layer through a through hole, so that the IGBT area and the diode area are evenly distributed on the back of the device, so that the heat dissipation of different areas of the device can diffuse with each other when the device works at different frequencies. Whether the IGBT partition heat dissipation is high in a high-frequency working environment or the diode partition heat dissipation is high in a low-frequency environment, it can be adapted, thereby raising the junction temperature shortcoming of the device and allowing the device to work at a higher temperature limit; at the same time, since the switching performance of the IGBT increases with temperature, the increase in temperature excites more carriers, which will lead to an increase in the switching loss of the device. Therefore, temperature has a strong correlation with the switching loss of the RC-IGBT device. The present application significantly improves the IGB by evenly distributing the IGB and diode areas on the back of the device. The boundary contact area between T and the diode is reduced, thereby reducing the inconsistency between the switching loss and the center loss caused by the temperature at the IGBT partition boundary, and further optimizing the switching loss variation curve of the RC-IGBT device during operation with the temperature; in addition, since the device will encounter a short-circuit condition during actual use, if the short-circuit performance of the device cannot withstand the short-circuit condition, it will directly cause damage to the device. The short-circuit performance of the device refers to the working time of the device under extreme conditions, and the performance is strongly correlated with the temperature accumulation of the device. Therefore, the structure designed in the present application improves the short-circuit performance of the device by improving the heat dissipation performance of the device; in addition, the improvement of the heat dissipation performance of the device makes it possible to reduce the size of the device while maintaining the short-circuit performance of the device unchanged, thereby reducing the production cost of the device.

[0029] Specifically, based on the above embodiment, the present application also provides another method for preparing a RC-IGBT device to further explain the above method for preparing a RC-IGBT device. The preparation method includes a device front side process and a device back side process. Figure 4 The figure shows the process flow of the front side of the device, which specifically includes: S100: performing ion implantation on the epitaxial layer 1 to form a buffer layer 2 in the epitaxial layer 1, such as Figure 4 As shown in (a) in .

[0030] S101: etching the buffer layer 2 and part of the epitaxial layer 1 to form a first trench 3 and a second trench 4; forming a first gate electrode 5 and a second gate electrode 6 in the first trench 3 and the second trench 4, respectively. Figure 4 As shown in (b) in .

[0031] Specifically, Figure 5 As shown, in some embodiments of the present application, the specific implementation steps of forming the first gate electrode 5 and the second gate electrode 6 in the first trench 3 and the second trench 4 include: A first gate oxide layer 51 is deposited at the bottom and sidewall of the first trench 3. The first gate oxide layer 51 has a third trench 511. Figure 5 As shown in (a) in .

[0032] The first polysilicon layer 52 is filled in the third trench 511, and a second gate oxide layer 53 is deposited on the surface of the first polysilicon layer 52 to obtain a first gate electrode 5. Figure 5 As shown in (b) in .

[0033] A third gate oxide layer 61 is deposited on the bottom and sidewall of the second trench 4. The third gate oxide layer 61 has a fourth trench 611. Figure 5 As shown in (c) in .

[0034] The second polysilicon layer 62 is filled in the fourth trench 611, and a fourth gate oxide layer 63 is deposited on the surface of the second polysilicon layer 62 to obtain a second gate electrode 6. Figure 5 As shown in (d) in .

[0035] S102: Ion implantation is performed on the buffer layer 2 located on the side of the first gate electrode 5 away from the second gate electrode 6 and the buffer layer 2 located between the first gate electrode 5 and the second gate electrode 6, respectively, to form a P-type body region 7 on the side of the buffer layer 2 away from the epitaxial layer 1, such as Figure 4 As shown in (c) in .

[0036] Specifically, Figure 6 As shown, in some embodiments of the present application, the specific implementation steps of forming the P-type body region 7 on the side of the buffer layer 2 away from the epitaxial layer 1 include: P- ion implantation is performed on the buffer layer 2 located at the side of the first gate electrode 5 away from the second gate electrode 6, so as to form a first P-type body region 71 in contact with the first gate electrode 5 at the side of the first gate electrode 5 away from the second gate electrode 6. Figure 6 As shown in (a) in .

[0037] P-ion implantation is performed on the buffer layer 2 between the first gate electrode 5 and the second gate electrode 6 to form a second P-type body region 72 in contact with the first gate electrode 5 and the second gate electrode 6 between the first gate electrode 5 and the second gate electrode 6. Figure 6 As shown in (b) in .

[0038] S103: performing ion implantation on the buffer layer 2 located on the side of the second gate electrode 6 away from the first gate electrode 5 to form a P-type anode region 8; wherein the thickness of the P-type anode region 8 is the same as the thickness of the buffer layer 2; Figure 4 As shown in (d) in .

[0039] S104: ion implantation is performed on the P-type body region 7 and the P-type anode region 8 respectively, so as to form an IGBT conductive region 9 on the side of the P-type body region 7 away from the buffer layer 2, and to form a diode anode conductive region 10 on the side of the P-type anode region 8 away from the epitaxial layer 1. Figure 4As shown in (e) in .

[0040] Specifically, Figure 7 As shown, in some embodiments of the present application, the specific implementation steps of step S104 include: N+ ion implantation is performed on the first P-type body region 71 to form a first N+ region 91 in contact with the first gate electrode 5 on the side of the first gate electrode 5 away from the second gate electrode 6. Figure 7 As shown in (a) in .

[0041] P+ ion implantation is performed on the first P-type body region 71 to form a first P+ region 92 in contact with the first N+ region 91 on the side of the first N+ region 91 away from the first gate electrode 5. Figure 7 As shown in (b) in .

[0042] N+ ion implantation is performed on the second P-type body region 72 to form a second N+ region 93 in contact with the first gate electrode 5 on the side of the first gate electrode 5 close to the second gate electrode 6. Figure 7 As shown in (c) in .

[0043] P+ ion implantation is performed on the second P-type body region 72 to form a second P+ region 94 in contact with the second N+ region 93 on the side of the second N+ region 93 away from the first gate electrode 5. Figure 7 As shown in (d) in .

[0044] P+ ions are implanted into the P-type anode region 8 to form a third P+ region, which is the diode anode conductive region 10. Figure 7 As shown in (e) in .

[0045] S105: forming an ILD oxide layer 11 on the surface of the first gate electrode 5 and the second gate electrode 6 away from the epitaxial layer 1, such as Figure 4 As shown in (f) in .

[0046] S106: Depositing a first metal layer 12 on the surface of the IGBT conductive region 9, the surface of the diode anode conductive region 10 and the surface of the ILD oxide layer 11, such as Figure 4 As shown in (g) in .

[0047] Furthermore, if Figure 8 The figure shows the process flow of the device backside, which specifically includes: S107: Protons are injected into the surface of the epitaxial layer 1 away from the gate electrode, the emitter and the diode anode to form a composite epitaxial layer A.

[0048] S108: forming a first drift region 13 on the surface of the composite epitaxial layer A away from the gate electrode, the emitter and the diode anode, such as Figure 8 As shown in (a) in .

[0049] S109: forming a second drift region 14 on the surface of the first drift region 13 away from the composite epitaxial layer A, such as Figure 8 As shown in (b) in .

[0050] S110: P-type impurities are implanted into the second drift region 14 to form a P-type semiconductor layer 15 on the side of the second drift region 14 away from the first drift region 13. Figure 8 As shown in (c) in .

[0051] Optionally, in some embodiments of the present application, after forming the P-type semiconductor layer 15 , the P-type semiconductor layer 15 is further subjected to laser annealing to activate ions in the P-type semiconductor layer 15 .

[0052] S111: N-type impurities are implanted into the P-type semiconductor layer 15 to form a diode cathode conductive region 16 in the P-type semiconductor layer 15; wherein the thickness of the diode cathode conductive region 16 is the same as the thickness of the P-type semiconductor layer 15, such as Figure 8 As shown in (d) in .

[0053] S112: depositing a second metal layer 17 on the surface of the P-type semiconductor layer 15 away from the second drift region 14, such as Figure 8 As shown in (e) in .

[0054] The embodiment of the present application further provides an RC-IGBT device, which is prepared using the above-mentioned method for preparing the RC-IGBT device, and specifically includes: Composite epitaxial layer; A gate electrode is arranged on one side surface of the composite epitaxial layer; An emitter electrode is arranged on a surface of a side of the composite epitaxial layer where a gate electrode is arranged; The diode anode is arranged on the surface of the composite epitaxial layer on one side where the gate electrode is arranged; A first drift region is arranged on a surface of the composite epitaxial layer away from the gate electrode, the emitter and the diode anode; A second drift region is arranged on a surface of the first drift region away from the composite epitaxial layer; A collector electrode is arranged on a surface of the second drift region away from the first drift region; The diode cathode is arranged on a surface of the second drift region away from the first drift region.

[0055] Furthermore, the gate electrode includes a first gate electrode and a second gate electrode, and an ILD oxide layer is disposed on a surface of the first gate electrode and the second gate electrode away from the composite epitaxial layer; The buffer layer of the RC-IGBT device is arranged on a side of the first gate electrode away from the second gate electrode and between the first gate electrode and the second gate electrode; the P-type body region of the RC-IGBT device is arranged on a side of the buffer layer away from the composite epitaxial layer; The IGBT conductive region of the RC-IGBT device is arranged in the P-type body region on the side away from the buffer layer, and specifically includes: A first N+ region is arranged on a side of the first gate electrode away from the second gate electrode and in contact with the first gate electrode; A first P+ region is disposed on a side of the first N+ region away from the first gate electrode and in contact with the first N+ region; A second N+ region is disposed on a side of the first gate electrode close to the second gate electrode and in contact with the first gate electrode; A second P+ region is disposed on a side of the second N+ region away from the first gate electrode and in contact with the second N+ region; The diode anode is arranged on a side of the second gate electrode away from the first gate electrode, and specifically comprises: A P-type anode region is arranged on a surface of the composite epitaxial layer away from the first drift region; The diode anode conductive region is arranged in the P-type anode region and away from the composite epitaxial layer; The emitter includes a first metal layer, which is arranged on the surface of the IGBT conductive region, the surface of the diode anode conductive region and the surface of the ILD oxide layer; The collector includes: A P-type semiconductor layer is arranged on a side of the second drift region away from the first drift region; A second metal layer is disposed on a side of the P-type semiconductor layer away from the second drift region; The diode cathode includes a diode cathode conductive region, which is arranged in the P-type semiconductor layer; wherein the thickness of the diode cathode conductive region is the same as the thickness of the P-type semiconductor layer.

[0056] The RC-IGBT device provided in the embodiment of the present application can optimize the reverse recovery performance of the diode without increasing the IGBT loss, reduce the reverse recovery current tail in the diode, and slow down the heating rate of the device. At the same time, the back side of the RC-IGBT device dissipates heat evenly and has good heat dissipation performance and short-circuit performance.

[0057] Obviously, the above embodiments are merely examples for the purpose of clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims

1. A method for preparing an RC-IGBT device, characterized in that: include: Forming a gate electrode, an emitter and a diode anode of the RC-IGBT device on a surface of one side of the epitaxial layer; Injecting protons into the surface of the epitaxial layer away from the gate electrode, the emitter and the diode anode to form a composite epitaxial layer; Forming a first drift region on a surface of the composite epitaxial layer away from the gate electrode, the emitter and the diode anode; forming a second drift region on a surface of the first drift region away from the composite epitaxial layer; A collector electrode and a diode cathode of the RC-IGBT device are formed on a surface of the second drift region that is away from the first drift region.

2. The method for preparing the RC-IGBT device according to claim 1, characterized in that: Injecting protons into a surface of the epitaxial layer away from the gate electrode, the emitter and the diode anode comprises: Prepare a photolithography plate, wherein the photolithography plate includes a plurality of through holes arranged in an array; Protons are injected into the surface of the epitaxial layer away from the gate electrode, the emitter and the diode anode through a plurality of through holes on the photolithography plate.

3. The method for preparing the RC-IGBT device according to claim 1, characterized in that: The shapes of the through holes include rectangle, circle and polygon.

4. The method for preparing the RC-IGBT device according to claim 1, characterized in that: The gate electrode, emitter and diode anode of the RC-IGBT device are formed on the surface of one side of the epitaxial layer, including: Performing ion implantation on the epitaxial layer to form a buffer layer on a side of the epitaxial layer away from the first drift region; Etching the buffer layer and a portion of the epitaxial layer to form a first trench and a second trench; forming a first gate electrode and a second gate electrode in the first trench and the second trench respectively; Performing ion implantation on the buffer layer located on the side of the first gate electrode away from the second gate electrode and the buffer layer located between the first gate electrode and the second gate electrode, respectively, to form a P-type body region on the side of the buffer layer away from the epitaxial layer; Performing ion implantation on the buffer layer located on the side of the second gate electrode away from the first gate electrode to form a P-type anode region; wherein the thickness of the P-type anode region is the same as the thickness of the buffer layer; Performing ion implantation on the P-type body region and the P-type anode region respectively, forming an IGBT conductive region on a side of the P-type body region away from the buffer layer, and forming a diode anode conductive region on a side of the P-type anode region away from the epitaxial layer; Forming an ILD oxide layer on the surface of the first gate electrode and the second gate electrode away from the epitaxial layer; A first metal layer is deposited on the surface of the IGBT conductive region, the surface of the diode anode conductive region and the surface of the ILD oxide layer.

5. The method for preparing the RC-IGBT device according to claim 4, characterized in that: Forming a first gate electrode and a second gate electrode in the first trench and the second trench, respectively, comprises: Depositing a first gate oxide layer at the bottom and sidewall of the first trench, wherein the first gate oxide layer has a third trench; Filling a first polysilicon layer in the third trench, and depositing a second gate oxide layer on the surface of the first polysilicon layer to obtain a first gate electrode; Depositing a third gate oxide layer at the bottom and sidewall of the second trench, wherein the third gate oxide layer has a fourth trench; A second polysilicon layer is filled in the fourth trench, and a fourth gate oxide layer is deposited on the surface of the second polysilicon layer to obtain a second gate electrode.

6. The method for preparing the RC-IGBT device according to claim 4, characterized in that: Forming a P-type body region in the buffer layer away from the epitaxial layer comprises: Performing P- ion implantation on the buffer layer located on the side of the first gate electrode away from the second gate electrode, so as to form a first P-type body region in contact with the first gate electrode on the side of the first gate electrode away from the second gate electrode; P- ion implantation is performed on the buffer layer between the first gate electrode and the second gate electrode to form a second P-type body region between the first gate electrode and the second gate electrode and in contact with the first gate electrode and the second gate electrode.

7. The method for preparing the RC-IGBT device according to claim 6, characterized in that: Forming an IGBT conductive region in the P-type body region away from the buffer layer, and forming a diode anode conductive region in the P-type anode region away from the epitaxial layer comprises: Performing N+ ion implantation on the first P-type body region to form a first N+ region in contact with the first gate electrode on a side of the first gate electrode away from the second gate electrode; Performing P+ ion implantation on the first P-type body region to form a first P+ region in contact with the first N+ region on a side of the first N+ region away from the first gate electrode; Performing N+ ion implantation on the second P-type body region to form a second N+ region in contact with the first gate electrode on a side of the first gate electrode close to the second gate electrode; Performing P+ ion implantation on the second P-type body region to form a second P+ region in contact with the second N+ region on a side of the second N+ region away from the first gate electrode; P+ ions are implanted into the P-type anode region to form a third P+ region.

8. The method for preparing the RC-IGBT device according to claim 1, characterized in that: Forming a collector electrode and a diode cathode of an RC-IGBT device on a surface of the second drift region away from the first drift region comprises: Performing P-type impurity implantation into the second drift region to form a P-type semiconductor layer on a side of the second drift region away from the first drift region; Injecting N-type impurities into the P-type semiconductor layer to form a diode cathode conductive region in the P-type semiconductor layer; wherein the thickness of the diode cathode conductive region is the same as the thickness of the P-type semiconductor layer; A second metal layer is deposited on a surface of the P-type semiconductor layer away from the second drift region.

9. An RC-IGBT device, characterized in that: The RC-IGBT device is prepared by the method for preparing the RC-IGBT device according to any one of claims 1 to 8, which specifically comprises: Composite epitaxial layer; A gate electrode is arranged on a surface of one side of the composite epitaxial layer; An emitter electrode is arranged on a surface of the composite epitaxial layer on a side where a gate electrode is arranged; A diode anode is arranged on the surface of the composite epitaxial layer on one side where the gate electrode is arranged; A first drift region is arranged on a surface of the composite epitaxial layer away from the gate electrode, the emitter and the diode anode; A second drift region is arranged on a surface of the first drift region away from the composite epitaxial layer; A collector electrode is arranged on a surface of the second drift region away from the first drift region; The diode cathode is arranged on a surface of the second drift region which is away from the first drift region.

10. The RC-IGBT device according to claim 9, characterized in that: The gate electrode comprises a first gate electrode and a second gate electrode, and an ILD oxide layer is disposed on a surface of the first gate electrode and the second gate electrode away from the composite epitaxial layer; The buffer layer of the RC-IGBT device is arranged on a side of the first gate electrode away from the second gate electrode and between the first gate electrode and the second gate electrode; the P-type body region of the RC-IGBT device is arranged on a side of the buffer layer away from the composite epitaxial layer; The IGBT conductive region of the RC-IGBT device is arranged in the P-type body region on a side away from the buffer layer, and specifically includes: A first N+ region is disposed on a side of the first gate electrode away from the second gate electrode and in contact with the first gate electrode; A first P+ region, disposed on a side of the first N+ region away from the first gate electrode and in contact with the first N+ region; A second N+ region is disposed on a side of the first gate electrode close to the second gate electrode and in contact with the first gate electrode; A second P+ region, disposed on a side of the second N+ region away from the first gate electrode and in contact with the second N+ region; The diode anode is arranged on a side of the second gate electrode away from the first gate electrode, and specifically comprises: A P-type anode region is arranged on a surface of the composite epitaxial layer away from the first drift region; A diode anode conductive region is arranged in the P-type anode region at a side away from the composite epitaxial layer; The emitter comprises a first metal layer, which is arranged on the surface of the IGBT conductive region, the surface of the diode anode conductive region and the surface of the ILD oxide layer; The collector comprises: A P-type semiconductor layer is arranged on a side of the second drift region away from the first drift region; A second metal layer is disposed on a side of the P-type semiconductor layer away from the second drift region; The diode cathode includes a diode cathode conductive region, which is disposed in the P-type semiconductor layer; wherein the thickness of the diode cathode conductive region is the same as the thickness of the P-type semiconductor layer.

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