Substrate frame design for three-dimensional stacked electronic components

Abstract

To mitigate stress on a substrate in a three-dimensional (3D) stacked electronic assembly, a substrate frame may be divided into a plurality of frame portions separated by spaces between the frame portions. These intervals allow the substrate to expand / contract in response to temperature changes and other environmental conditions, and generally allow the substrate to move in one or more axial directions. The spacing between the substrate portions may be design-specific for each substrate design. The placement of IC packages on both sides of the substrate may be analyzed by physical measurements, physical model simulation, or using trained neural networks to identify maximum warpage regions. The space in the substrate frame may then be placed alongside or aligned with the maximum warpage region to reduce stresses on the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. non-provisional application No. 17 / 851,754, filed on June 28, 2022, entitled “SUBSTRATE FRAME DESIGN FOR THREE-DIMENSIONAL STACKED ELECTRONIC ASSEMBLIES,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure generally describes substrate frame designs for three-dimensional (3D) stacked electronic components. More particularly, the present disclosure describes substrate frame designs that are divided into multiple frame portions to relieve stress on the electronic components. Background Art

[0004] A chiplet is a modular integrated circuit that is specifically designed to be used with other similar modular chiplets to form larger, more complex processing systems. This allows functional blocks to be divided into different chiplets in the design, providing greater flexibility and modularity in the design process. Compared to traditional monolithic integrated circuit (IC) designs, chiplet-based designs use smaller independent dies connected together. Each chiplet can be specifically designed to perform a separate function, such as a processing core, graphics processing unit, math coprocessor, hardware accelerator, and so on. Chiplet-based designs also reduce manufacturing costs because larger dies can be divided into smaller chiplets to increase yield and binning. As costs increase and Moore's Law slows, traditional monolithic chip development becomes less attractive because chiplets are cheaper and have a faster time to market. The emergence of a relatively new chiplet-based ecosystem is beginning to enable alternative methods of designing complex systems by integrating pre-tested chiplet dies into larger packages.

[0005] To accommodate the increasing number of chiplet-based or multi-IC designs, manufacturers are turning to 3D packaging as a space-efficient footprint solution for electronic components. 3D packaging includes 3D integration of multiple substrates connected by traditional interconnect methods in a vertical stack. 3D packaging may include 3D system-in-package (SiP), 3D wafer-level packaging (3D WLP), and other emerging packaging designs. However, while vertical stacking in 3D components can reduce the footprint of the entire component, these vertical stacks may increase the mechanical stress on the individual substrates. Therefore, improvements are needed in this area. Summary of the invention

[0006] In some embodiments, a three-dimensional (3D) stacked electronic component may include: a printed circuit board; a package substrate; a plurality of integrated circuit (IC) packages, the plurality of IC packages being mounted to the package substrate; and a substrate frame, the substrate frame being disposed between the printed circuit board and the package substrate in the 3D stacked electronic component. The substrate frame may define a cavity inside the substrate frame and between the printed circuit board and the package substrate. The plurality of IC packages may be mounted to the package substrate inside the cavity. The substrate frame may be divided into a plurality of frame portions, the plurality of frame portions being separated by spaces between the plurality of frame portions.

[0007] In some specific embodiments, a substrate frame for a 3D stacked electronic component may include: a first side, the first side including a first interconnect, the first interconnect is configured to be mounted to a first substrate, the first substrate having a plurality of integrated circuit (IC) packages mounted to the first substrate. The component may also include a second side, the second side including a second interconnect, the second interconnect is configured to be mounted to a second substrate, so that the substrate frame can be disposed between the first substrate and the second substrate in the 3D stacked electronic component, and a cavity can be defined within the substrate frame and between the first substrate and the second substrate, and a plurality of integrated IC packages are mounted in the cavity. The component may also include a plurality of frame portions, the plurality of frame portions being separated by spaces between the plurality of frame portions.

[0008] In some embodiments, a method of assembling a three-dimensional (3D) stacked electronic component may include: mounting a plurality of integrated circuit (IC) packages to a first substrate; and connecting a substrate frame to the first substrate and to a second substrate. The substrate frame may define a cavity within the substrate frame and between the first substrate and the second substrate. The plurality of IC packages may be mounted to the first substrate within the cavity. The substrate frame is divided into a plurality of frame portions, the plurality of frame portions being separated by spaces between the plurality of frame portions.

[0009] In any specific embodiment, any and all of the following features may be implemented in any combination and without limitation. The assembly may also include a second plurality of IC packages. The package substrate may include a first side to which a plurality of IC packages are mounted inside the cavity. The package substrate may include a second side to which a second plurality of IC packages may be mounted. The second plurality of IC packages may be mounted to the second side of the package substrate within the footprint of the cavity. The second plurality of IC packages may include fewer IC packages than the plurality of IC packages, thereby causing warpage in the package substrate. The space between the plurality of frame portions of the substrate frame may be located next to the warpage in the package substrate to reduce the warpage. The printed circuit board may extend beyond the footprint of the package substrate. The assembly may also include a second package substrate, which may be mounted to the printed circuit board via a second substrate frame. The substrate frame may have a rectangular shape. The space separating the plurality of frame portions may be located on the side of the substrate frame. The space separating the plurality of frame portions may be located at the corner of the substrate frame. The width of the plurality of frame portions may be maintained across the space between the plurality of frame portions. The space between the plurality of frame portions may be located in the substrate frame so that the substrate frame is symmetrical with respect to an axis. The width of the plurality of frame portions may be at least five times greater than the length of the space between the plurality of frame portions. Identifying the region of the first substrate having warpage may include: measuring the displacement of the region of the first substrate after mounting the plurality of IC packages to the first substrate relative to the displacement of the region of the first substrate before mounting the plurality of IC packages to the first substrate. The method / operation may also include: measuring the displacement of the region of the first substrate after connecting the substrate frame to the first substrate to determine whether the displacement of the region has been reduced by mounting the first substrate to the substrate frame. Identifying the region of the first substrate having warpage includes: simulating a 3D model of the first substrate having the plurality of IC packages mounted to the first substrate. The method / operation may also include: simulating a 3D model of the substrate frame connected to the 3D model of the first substrate to determine whether the warpage of the region has been reduced by adding the 3D model of the substrate frame. The method / operation may also include: determining the location of the space between the plurality of frame portions in the substrate frame based on identifying the region of the first substrate having warpage. The method / operation may also include: determining the location of the space between the plurality of frame portions in the substrate frame based on the output provided by a machine learning model, the machine learning model being trained to receive the location of the plurality of IC packages and output the location of the space. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The nature and advantages of the various embodiments may be further understood with reference to the remainder of the specification and the accompanying drawings, in which like reference numerals are used to refer to like parts. In some cases, a sub-label is associated with a reference numeral to indicate one of multiple similar components. When a reference numeral is referenced without specifying an existing sub-label, it is intended to refer to all such multiple similar parts.

[0011] Figure 1 3D stacked electronic components are shown according to some specific embodiments.

[0012] Figure 2 A bird's eye view of a 3D stacked electronic assembly is shown in accordance with some specific embodiments.

[0013] Figure 3 A diagram illustrating a 3D stacked electronic assembly using a substrate frame divided into a plurality of frame portions in accordance with some specific embodiments.

[0014] Figure 4 A diagram illustrating a space between two frame portions according to some specific embodiments.

[0015] Figure 5 A 3D stacked electronic assembly with an additional frame portion is shown in accordance with some specific embodiments.

[0016] Figure 6 A 3D stacked electronic component with space at the corner of a packaging substrate is shown in accordance with some specific embodiments.

[0017] Figure 7 Alternative geometries for substrate frames are shown according to some specific embodiments.

[0018] Fig. 8A Simulation or measurement results indicating warpage of a package substrate according to some specific embodiments are shown.

[0019] Figure 8B The design of a substrate frame based on a warpage map according to some specific embodiments is shown.

[0020] Fig. 9 A flow chart of a method for assembling a 3D stacked electronic component according to some specific embodiments is shown.

[0021] Fig.10 A flow chart for identifying spatial locations in a substrate frame using a neural network is shown, according to some specific embodiments.

[0022] Fig.11 An exemplary computer system is shown in which various specific embodiments may be implemented. DETAILED DESCRIPTION

[0023] Three-dimensional (3D) stacked electronic components can stack multiple substrates on top of each other, with integrated circuit (IC) packages typically mounted on both sides of the substrates. In order to create space between the substrates in the stacked electronic components, a substrate frame can be placed between the substrates and around the IC package to create a cavity for the IC package between the substrates. Each of these substrates may be subject to internal stresses that cause warping in the substrate. This warping may be exacerbated when the IC package is not symmetrically mounted on the top and bottom of the substrate, or when different numbers of IC packages are mounted on each side of the substrate. Since the substrate frame is a rigid continuous member, the substrate frame tends to limit the expansion and contraction of the connected substrate in all directions, thereby further amplifying the warping of the substrate. Substrate warping may lead to manufacturing failures, reliability issues, and shortened life of electronic components.

[0024] To reduce stress on substrates in 3D stacked electronic assemblies, the substrate frame can be divided into multiple frame portions that are separated by spaces between the frame portions. These spacings allow the substrate to expand / contract in response to temperature changes and other environmental conditions, and typically allow the substrate to move in one or more axial directions. The spacing between the substrate portions can be design specific for each substrate design. The placement of the IC package on both sides of the substrate can be analyzed by physical measurement, physical model simulation, or using a trained neural network to identify the maximum warpage area. The space in the substrate frame can then be placed next to or aligned with the maximum warpage area to reduce stress on the substrate.

[0025] As traditional monolithic-based designs become increasingly expensive to manufacture, chiplets and modular ICs have become successful alternatives in system architectures to increase yields, reduce manufacturing costs, and increase the modularity of designs. Each IC can include a separate die manufactured from a silicon wafer. Instead of forcing all functions of a system (e.g., central processing unit (CPU), memory, graphics processing unit (GPU), various peripherals, etc.) to be manufactured on one large monolithic die, modular systems separate these functions into separate dies that can then be packaged together to perform the same overall function. By reducing the size of a single die, the yield and manufacturing cost of the entire system can be reduced.

[0026] Figure 1 A 3D stacked electronic assembly 100 is shown in accordance with some specific embodiments. Figure 1The view of assembly 100 shown may represent a cross-sectional view of assembly 100. Assembly 100 may include multiple substrates arranged in a vertical stack. As used herein, "substrate" may include any material on which electronic components may be mounted. For example, assembly 100 may include a first substrate, such as a packaging substrate 122 made of an organic material, a silicon wafer, a glass layer, and / or any other type of substrate material suitable for mounting a chiplet or IC die. In addition, assembly 100 may include a second substrate, such as a printed circuit board 108. Printed circuit board 108 may serve as the bottom layer in a 3D stacked electronic assembly 100. Although in Figure 1 Although not explicitly shown in the drawings, other substrates in addition to the packaging substrate 122 may be mounted to the printed circuit board 108. For example, additional packaging substrates may be mounted next to the packaging substrate 122 to form additional 3D vertical stacks on the printed circuit board 108. Thus, the area of ​​the printed circuit board 108 may extend beyond the footprint 128 of the packaging substrate 122. In the present disclosure, any type of substrate may be collectively referred to as a first substrate, a second substrate, etc., including the packaging substrate 122, the printed circuit board 108, and / or any other substrate that may be mounted above the packaging substrate 122 or at other locations on the printed circuit board 108.

[0027] A plurality of IC packages may be mounted to the packaging substrate 122. Typically, the IC packages may be mounted to both sides of the packaging substrate 122. For example, the packaging substrate 122 may include a first side (e.g., a bottom side) on which the first plurality of IC packages 104 are mounted. The packaging substrate 122 may also include a second side (e.g., a top side) on which the second plurality of IC packages 105 are mounted. In some designs, the first plurality of IC packages 104 and the second plurality of IC packages 105 may be mounted such that they are different in number, position, and / or size relative to each other on the top and bottom of the packaging substrate 122. For example, Figure 1 The top side of the packaging substrate 122 is shown to include fewer IC packages 105 than the IC packages 104 on the bottom of the packaging substrate 122. Additionally, the IC packages 105 on the top side of the packaging substrate 122 may be sized differently than the packages 104 on the bottom side of the packaging substrate 122. The IC packages 105 on the top side may also be placed in different locations compared to the IC packages 104 on the bottom side, such that the layout of the IC packages 105 on the top of the packaging substrate 122 and the resulting signal routing and open space are different than the layout, signal routing, and open space on the bottom of the packaging substrate 122.

[0028] The term "IC package" as used herein may refer to any integrated circuit mounted to a substrate in the 3D stacked electronic assembly 100. For example, an IC package may include separate integrated circuit dies, chiplets, and / or any other similar components. For example, IC packages 104, 105 may be manufactured from separate dies from one or more silicon wafers. IC packages 104, 105 may also perform multiple different functions, such as dedicated systems on chip (SOCs), GPUs, digital signal processors (DSPs), artificial intelligence (AI) accelerators, various codecs, Wi-Fi communication modules, memory controllers, memory caches, input / output (I / O) peripherals, and the like. Although manufactured on separate dies, each of these IC packages 104, 105 may be connected together using various interconnect architectures to perform substantially the same functions as those performed by similar monolithic designs, but in a distributed manner.

[0029] For example, the package substrate 122 may include a high-density interposer. The high-density interposer may include high-density wiring inside the interposer that is connected to pads on the bottom side of the package of the package substrate 122. The high-density interposer may be manufactured using organic materials, glass, silicon, and / or any other interposer material. The IC packages 104, 105 may communicate with each other through the interposer without requiring traffic to pass through any vertical interconnects between different substrates.

[0030] The substrate frame 112 can be disposed between the package substrate 122 and the printed circuit board 108. The substrate frame 112 can perform a variety of different functions. First, the substrate frame 112 can provide a vertical interconnect solution between the package substrate 122 and the printed circuit board 108. For example, the substrate frame 112 can include a first side (e.g., a top side) having a first interconnect 157. The first interconnect 157 can be configured to be mounted to a first substrate, such as the bottom of the package substrate 122. The substrate frame 112 can also include a second side (e.g., a bottom side) having a second interconnect 159. The second interconnect 159 can be configured to be mounted to a second substrate, such as the top side of the printed circuit board 108.

[0031] To provide interconnection between the package substrate 122 and the printed circuit board 108, some specific embodiments of the substrate frame 112 may include through-hole interconnects extending directly between the package substrate 122 and the location on the printed circuit board 108. For example, the substrate frame 112 may be formed of an agent or other molding material to surround the vertical interconnects extending through the substrate frame 112. In other specific embodiments, the substrate frame 112 may alternatively or additionally include one or more wiring or interconnect layers that route the connection from the top of the substrate frame 112 to different locations on the bottom of the substrate frame 112. Some specific embodiments may include a silicon layer 113 that includes a metal layer that provides wiring functions. The silicon layer 113 may also include other integrated circuits or circuit components that perform functions using signals transmitted through the interconnects. Therefore, the substrate frame 112 can allow the IC packages 104, 105 to communicate with other components and / or systems mounted to the printed circuit board 108.

[0032] Another function performed by the substrate frame 112 may be to define a cavity 106 within the substrate frame 112 and between the package substrate 122 and the printed circuit board 108. The cavity 106 may provide space for the IC package 104 mounted to the bottom side of the package substrate 122. Figure 1 108. Although not explicitly shown in the drawings, some designs may also include IC packages mounted to the top side of the printed circuit board 108. Therefore, the height of the substrate frame 112 may be sized to provide space between the IC package 104 on the bottom of the package substrate 122 and any IC package mounted to the top side of the printed circuit board 108. In some specific embodiments, the cavity 106 may surround the first plurality of IC packages 104 mounted to the bottom side of the package substrate 122. In addition, even if the second plurality of IC packages 105 mounted to the top side of the package substrate 102 are not enclosed in the cavity 106, in some designs these IC packages 105 may be mounted within the footprint 120 of the cavity 106 defined by the substrate frame 112. The vertical thickness of the substrate frame 112 may depend on the vertical thickness of the IC package. For example, the IC package 104 may be about 50 μm to about 750 μm thick, depending on the package. The vertical thickness of the substrate frame 112 may be designed to be at least 50 μm, including interconnects for providing the cavity 106.

[0033] Figure 2 An aerial view of a 3D stacked electronic assembly 100 is shown according to some specific embodiments. This aerial view of the assembly 100 shows how the substrate frame 112 is manufactured as a single continuous component. The cavity 106 defined by the substrate frame 112 surrounds the IC package 104 mounted to the bottom of the printed circuit board. In general, the substrate frame 112 can form a very rigid structure mounted to the periphery of the package substrate 122.

[0034] like Figures 1 to 2 As shown, the IC package 104 may include an IC package with various sizes, pin counts, mounting locations, mounting techniques, orientations, and / or other physical characteristics. In addition, the IC package 104 on the bottom of the package substrate 122 may be different from the IC package 105 on the top of the package substrate 122. These characteristic differences between the IC package 104 on the bottom of the package substrate 122 and the IC package 105 on the top of the package substrate 122 may cause stress differences between the top and bottom of the package substrate 122. This stress difference may cause the warping of the package substrate 122. "Warping" as used herein may generally refer to any displacement or deflection of the substrate relative to the baseline, flat profile. For example, installing more IC packages on one side of the package substrate 122 compared to the other side of the package substrate 122 may cause the package substrate 122 to bend, thereby causing displacement between the middle of the package substrate 122 and the edge or corner of the package substrate 122. Any warping in the package substrate 122 may cause reliability issues for the entire assembly 100. For example, such warping may lead to problems such as weakened or separated solder joints, misalignment between the mounting pads of the IC package and the package substrate 122, stress on the IC package itself, and / or many other mechanical problems that may cause the assembly 100 to fail during the manufacturing process or later during use. Therefore, minimizing warping and stress on the package substrate 122 represents a technical problem in the field of electronic assembly manufacturing.

[0035] It has been found that the addition of the substrate frame 112 tends to amplify or exacerbate stress and warpage of the package substrate 122. For example, a mismatch in the Young's modulus and / or coefficient of thermal expansion of the material used to make the substrate frame 112 compared to the material used in the package substrate 122 may cause the package substrate 122 and the substrate frame 112 to expand / contract very differently in response to changing environmental conditions. In detail, it has been found that the rigidity and overall structure of the substrate frame 112 may not allow the package substrate 122 to move adequately in response to changes in temperature, humidity, etc. For example, it has been found that when the substrate frame is all one-piece, it can represent a rigid structure that changes the warpage of the package substrate, and some situations can actually create a warpage profile in the package substrate or enhance the existing warpage of the package substrate. For example, without the substrate frame, a test package substrate may exhibit a warpage of about 100 μm, and with the frame, this warpage may increase to a warpage of about 250-300 μm.

[0036] Figure 3A view of a 3D stacked electronic assembly 300 using a substrate frame divided into a plurality of frame portions is shown in accordance with some specific embodiments. In this example, a substrate frame 312 has been divided into two frame portions 312-1, 312-2. A space separates the two frame portions 312-1, 312-2. The placement of the space corresponds to a midpoint along one side of the substrate frame 312. When the substrate frame 312 has a plurality of frame portions, the substrate frame 312 may be divided into two frame portions 312-1, 312-2. Figure 3 When the rectangular shape is shown, the space between the two frame portions 312-1, 312-2 can be located at the midpoint of the two parallel edges of the rectangular shape. Although this particular example places the space between the two frame portions 312-1, 312-2 at the midpoint of the edge of the substrate frame, this placement is not meant to be limiting. Other specific embodiments can place the space at any point along the edge of the substrate frame 312, so that the substrate frame 312 is divided into two frame portions.

[0037] Some specific embodiments may place a space between the two frame portions 312 - 1 , 312 - 2 so that the two frame portions 312 - 1 , 312 - 2 are symmetrical along an axis passing through the center of the substrate frame 312 . For example, Figure 3 The space between the two frame portions 312-1, 312-2 in the assembly 300 can be aligned so that the two frame portions 312-1, 312-2 are symmetrical along the vertical axis 330 and the horizontal axis (not shown). Other embodiments can place the space between the frame portions according to other axes passing through the center of the assembly 300. For example, the position 334 of the space between the frame portions can be the same as Figure 3 The axis 332 shown in FIG. 3 is used for alignment. This axis 332 can be rotated through the center of the assembly 300 to place the position 334 at any symmetrical position.

[0038] Figure 4 A view of a space 403 between two frame portions 312-1, 312-2 is shown according to some embodiments. In some embodiments, the substrate frame 312 can be distinguished from separate risers or interconnects that are not part of a unified frame design. For example, the substrate frame 312 can maintain the same width 404 across the space 403 that separates one frame portion from another frame portion (i.e., the top and bottom of the frame portion can be aligned across the space 403). Thus, the footprint 410 of the substrate frame 312 extending through the space 403 can still define the boundaries of the cavity in which the IC package is mounted.

[0039] In some specific embodiments, the length 402 of the space 403 may be about 1 mm. Alternatively, some specific embodiments may use a space of less than about 2 mm, less than about 3 mm, less than about 5 mm, less than about 7 mm, less than about 10 mm, less than about 15 mm, less than about 20 mm, etc., depending on the specific embodiment. The width 404 of the substrate frame 312 may be about 5 mm. In some specific embodiments, the width 404 of the substrate frame 312 may also be between about 5 mm and about 10 mm, between about 10 mm and about 15 mm, between about 15 mm and about 20 mm, between about 20 mm and about 25 mm, between about 25 mm and about 30 mm, between about 30 mm and about 35 mm, between about 35 mm and about 40 mm, and / or greater than about 40 mm, depending on the specific embodiment. The length 402 of the space 403 may be defined relative to the width 404 of the substrate frame 312. For example, the width 404 of the substrate frame 312 can be greater than or approximately 5.0 times the length 402 of the space 403. In other specific embodiments, the width 404 can be greater than or approximately 2.5 times the length 402, greater than or approximately 7.5 times the length 402, greater than or approximately 10 times the length 402, and / or greater than or approximately 15 times the length 402. These measurement ranges for the width 404 and the length 402 are provided by way of example only and are not meant to be limiting.

[0040] Each of these ranges may be more or less suitable for different components, depending on the specific embodiment, the number of interconnects, the interconnect density, the cavity size, and other design-related characteristics. However, test data shows that while increasing the length 402 of the space 403 can continue to reduce stress, there are diminishing returns after a certain length. For example, some specific embodiments show that the length 402 of the space 403 reduces the maximum incremental warpage for an initial 1 mm. After the initial 1 mm, the gradual reduction in warpage tends to have a reducing effect on the warpage of the packaging substrate. Therefore, some specific embodiments may use optimal spacings between about 1 mm and about 2 mm, between about 1 mm and about 3 mm, and between about 1 mm and about 5 mm, depending on the size of the substrate frame and the packaging substrate, to reduce warpage without unduly limiting the area of ​​the substrate frame to provide interconnections between the substrates.

[0041] Figure 5 3D stacked electronic assembly 500 with additional frame parts according to some specific embodiments is shown. Figure 3 The two frame portions 312-1, 312-2 shown in FIG. 1 are provided by way of example only and are not meant to be limiting. Other embodiments may use additional frame portions and additional locations for spaces between these frame portions. Figure 5In the example of the substrate frame 512, the substrate frame 512 is divided into four separate frame portions 512-1, 512-2, 512-3, 512-4. Other embodiments may include more than four frame portions, such as five frame portions, six frame portions, ten frame portions, etc. As described above, some embodiments may place spaces between the frame portions so that the frame portions are symmetrical with respect to the horizontal axis, the vertical axis, and / or the diagonal axis of the assembly 500.

[0042] Although a large number of frame portions can be used, it has been found that the greatest reduction in stress / warpage of the package substrate may occur between two frame portions (with two corresponding spaces between the frame portions). Adding additional frame portions can continue to reduce stress / warpage of the package substrate, however the effect of adding additional frame portions (i.e., adding more spaces to the substrate frame) is reduced, so that the improvement is not additive, and therefore shows a decreasing improvement as more frame portions are added. For example, adding the first two spaces to the substrate frame 512 can initially produce a substantial reduction in stress / warpage of the package substrate. However, while adding an additional two spaces to a substrate frame that already has four or six spaces can continue to reduce stress / warpage of the package substrate, the incremental improvement may not be as great. Therefore, electronic component designers can balance the improvements provided by adding more spaces to the substrate frame 512 with the area required for interconnection, the difficulty of manufacturing and assembly, and / or other competing priorities. For example, designs typically use the minimum area for through-interconnection between the package substrate and the printed circuit board. Therefore, in some specific embodiments, space can be added to the substrate frame 512 until the space begins to interfere with the interconnection routing.

[0043] Some embodiments may also prioritize maintaining the cavity 506 to protect or isolate the IC package 504 on the bottom side of the package substrate 522. For example, a cryptographic processor or other sensitive electronic components may be placed in the cavity 506 to shield these electronic components from external inspection and prevent unwanted electronic data transmission from entering or leaving the cavity 506. Therefore, the length of the space and the number of frame portions may be limited to, for example, two frame portions or four frame portions in order to maintain the integrity of the cavity 506.

[0044] Figure 6 A 3D stacked electronic assembly 600 is shown with spaces at the corners of a substrate frame 612 according to some specific embodiments. This specific embodiment shows how the spaces between substrate frame portions can be placed anywhere on the substrate frame 612. In this example, the spaces can be placed at the corners of the substrate frame 612. This arrangement can still maintain a symmetrical arrangement of the frame portions 612-1, 612-2, 612-3, 612-4.

[0045] Figure 7An alternative geometry of a substrate frame 712 is shown according to some specific embodiments. In this example, the package substrate 722 can include a single large IC package 704 mounted in the middle of the package substrate 722. The substrate frame 712 can be enlarged as needed to fill the remaining space on the package substrate 722 while still providing a cavity 706 for the IC package 704. The substrate frame 712 has been divided into four quadrants 712-1, 712-2, 712-3, 712-4, and the length of the space between the frame portions can optionally be enlarged as the width of the substrate frame 712 increases. This design may be advantageous when the IC package 704 includes a large number of interconnects, which in turn may require a larger area for the substrate frame 712 to extend these interconnects between the substrates.

[0046] Fig. 8A Simulation or measurement results indicating the warpage of the packaging substrate 830 according to some specific embodiments are shown. As described above, the warpage of the packaging substrate 830 can be measured by the displacement from the baseline flat position of the substrate 830. For example, before the IC package is mounted on the substrate 830, the substrate 830 can be relatively flat. Measuring the resulting warpage can include measuring the displacement at various positions on the packaging substrate 830. For example, when designing a substrate frame, a prototype of the packaging substrate 830 with the IC package mounted thereon can be manufactured. A displacement sensor that measures the displacement from the baseline position can be used to generate a warpage map 800. The individual measurements can then be compiled into a warpage map 800, which can then be used to design a substrate frame for a design used in large-scale manufacturing.

[0047] Alternatively, some embodiments may use a model of the packaging substrate 830 to simulate physical properties to generate the warpage map 800, rather than physically measuring the displacement of the prototype packaging substrate 830. For example, a 3D model of the packaging substrate 830 and the IC package mounted thereon may be simulated using standard simulation software to generate the warpage map 800 resulting from the internal stress and induced stress on the packaging substrate 830.

[0048] After generating the warpage map 800, locations on the packaging substrate 830 where the warpage exceeds a threshold amount can be identified. For example, region 802 corresponds to a first region having a warpage above a first threshold, and region 803 corresponds to a second region having a warpage below a second threshold. In this example, the warpage pattern of the packaging substrate 830 can represent a "cup shape" of the substrate.

[0049] Figure 8BThe design of the substrate frame 812 based on the warpage map 800 according to some specific embodiments is shown. In order to avoid exacerbating the warpage of the package substrate 830, the space in the substrate frame 812 can be located next to the areas 802, 803 on the package substrate 830 that exhibit the greatest warpage. For example, the space on the side of the substrate frame 812 can be next to the area 802 in the middle of the package substrate 830. In addition, the space can be added at the corner of the substrate frame 812 near the area 803. In some specific embodiments, the location of the space can be identified so that the space is aligned with the warpage area on the vertical axis, the horizontal axis, and / or the diagonal axis.

[0050] Fig. 9 A flowchart 900 of a method for assembling a 3D stacked electronic assembly according to some specific embodiments is shown. The method may include mounting a plurality of IC packages to a first substrate (902). As described above, the first substrate may include a packaging substrate or any other type of substrate. The plurality of IC packages may be mounted to a first side or bottom side of the first substrate. Additionally, a second plurality of IC packages may be mounted to a second side or top side of the first substrate. The packages may be mounted within a footprint or cavity defined by a substrate frame.

[0051] In some embodiments, spaces may be provided in the substrate frame to divide the substrate into a plurality of frame portions according to a predetermined design. Alternatively, some embodiments may use automated processing to identify the location of spaces in the substrate frame to optimally reduce warpage in the package substrate. For example, some embodiments may optionally include identifying an area of ​​the first substrate having warpage (910). This area may be identified by a simulation process as described above. This area may also be identified by measuring the warpage of the package substrate on which the IC package or a prototype version thereof is mounted. This area having warpage may be one of a plurality of areas on the substrate having warpage, each of which may be considered when identifying the location of the space in the substrate frame. Some embodiments may identify warpage by comparing the displacement amount to a threshold value above or below a baseline position. The method may also optionally identify or determine the location of spaces between a plurality of frame portions in the substrate frame based on identifying an area of ​​the substrate having warpage (912). For example, the automated process may place two, three, four, or some predetermined number of spaces in the substrate frame so that they are next to or aligned with the area having warpage. As described above, the spaces may be aligned on a horizontal axis or a vertical axis intersecting the area having warpage. Other embodiments may simulate multiple locations of space in the substrate frame to identify the best placement to minimize warping of the package substrate.

[0052] After determining the locations of the spaces dividing the portions of the substrate frame, the method may include connecting the substrate frame to the first substrate and the second substrate 904. The second substrate may include another package substrate, an interposer, an intermediate layer, a printed circuit board, and / or any other type of substrate.

[0053] Alternatively, some embodiments may optionally use a machine learning process with a neural network to identify the location of the space in the substrate frame based on the location of the IC package (914). Fig.10 A flow chart 1000 for identifying spatial locations in a substrate frame using a neural network 1006 is shown in accordance with some embodiments. The neural network 1006 can be trained to accept locations 1004 (e.g., coordinates) of IC packages on a packaging substrate 1002. Alternatively, some embodiments can instead train the neural network 1006 as a classification network to receive an image or bitmap of the packaging substrate 1002 and identify the locations 1004 of the IC packages. This identification can be performed in an initial layer of the neural network 1006. Thus, the training process can set the internal weights and parameters of the first layer of the neural network 1006 to identify or classify the locations 1004 of the IC packages.

[0054] The final layer of the neural network 1006 may be trained to output scores for different locations 1008 where the space should be located in the substrate frame in order to minimize warpage on the package substrate 1002. For example, a plurality of different locations may correspond to outputs on the neural network 1006, each output generating a score (e.g., between 0.0 and 1.0) indicating the preference of the neural network 1006 for locating the space at that location. The location 1008 of the space may be provided as an output to a system engineer for designing the substrate frame. Alternatively, the location 1008 of the space may alternatively be provided as an input to a computer system that controls an automated process for manufacturing the substrate frame. The neural network 1006 may include parameters or constants that may be adjusted to limit the number of spaces or the location of the space based on design constraints. For example, certain designs may restrict the placement of spaces in certain locations based on interconnect requirements. These areas may be provided as parameters to the neural network 1006 so that the spaces are not placed in these areas.

[0055] The neural network 1006 may be trained using labeled training data from a measured physical design or from a simulation model. For example, some embodiments may generate training data by placing IC packages on the package substrate 1002 in a variety of different configurations. A simulation may then be performed using different spatial locations to separate the frame portions of the substrate frame. The resulting simulation may determine whether the warpage of the package substrate 1002 is sufficiently reduced. The reduction in warpage may be used to label each set of locations as training data for the neural network 1006. Alternatively, the same process may be performed using a physical prototype with data captured from a displacement sensor.

[0056] It should be noted that Fig. 9 The specific steps shown according to various specific embodiments provide specific methods for assembling 3D stacked electronic components. According to alternative specific embodiments, other step sequences may also be performed. For example, alternative specific embodiments may perform the steps outlined above in a different order. Furthermore, Fig. 9 The individual steps illustrated may include multiple sub-steps, which may be performed in various sequences appropriate to the individual steps. Furthermore, additional steps may be added or removed depending on the specific application. Many variations, modifications, and substitutions also fall within the scope of the present disclosure.

[0057] Each method described herein can be implemented by a computer system. Each step of these methods can be automatically performed by a computer system, and / or can provide input / output involving a user. For example, a user can provide input for each step in the method, and each of these inputs can respond to a specific output requesting such input, wherein the output is generated by a computer system. Each input can be received in response to a corresponding request output. In addition, the input can be received from a user, from another computer system as a data stream, retrieved from a memory location, retrieved through a network, requested from a network service, etc. Similarly, the output can be provided to a user, provided to another computer system as a data stream, stored in a memory location, sent through a network, provided to a network service, etc. In short, each step of the method described herein can be performed by a computer system, and can involve any number of inputs, outputs, and / or requests of a computer system, which may or may not involve a user. Those steps that do not involve a user can be said to be automatically performed by a computer system without human intervention. Therefore, it should be understood from the present disclosure that each step of each method described herein can be changed to include input and output of a user, or can be automatically completed by a computer system without human intervention, wherein any determination is made by a processor. Furthermore, some specific embodiments of each of the methods described herein may be implemented as a set of instructions stored on a tangible, non-transitory storage medium to form a tangible software product.

[0058] For example, Fig. 9 The automated steps 910, 912, and 914 can all be automatically performed by a computer system, including simulating the warpage of the substrate frame, identifying the location of the space in the substrate frame, executing and / or training a neural network or other machine learning model, etc. An example computer system for performing these steps is described below. For example, these steps can be embodied in a set of instructions stored on one or more memory devices (e.g., non-transitory computer readable media), which causes one or more processors to perform these steps.

[0059] Fig.11 An exemplary computer system 1100 in which various specific embodiments can be implemented is shown. System 1100 can be used to implement any of the above-mentioned computer systems. As shown, computer system 1100 includes a processing unit 1104, which communicates with multiple peripheral subsystems through a bus subsystem 1102. These peripheral subsystems may include a processing acceleration unit 1106, an I / O subsystem 1108, a storage subsystem 1118, and a communication subsystem 1124. Storage subsystem 1118 includes a tangible computer-readable storage medium 1122 and a system memory 1110.

[0060] The bus subsystem 1102 provides a mechanism for allowing the various components and subsystems of the computer system 1100 to communicate with each other as expected. Although the bus subsystem 1102 is schematically shown as a single bus, the replaceable specific embodiments of the bus subsystem can utilize multiple buses. The bus subsystem 1102 can be any of a variety of types of bus structures, including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. For example, such architectures can include an industry standard architecture (ISA) bus, a microchannel architecture (MCA) bus, an extended ISA (EISA) bus, a video electronics standard association (VESA) local bus, and a peripheral component interconnect (PCI) bus, which can be implemented as a mezzanine bus manufactured according to the IEEE P1386.1 standard.

[0061] The processing unit 1104, which may be implemented as one or more integrated circuits (e.g., conventional microprocessors or microcontrollers), controls the operation of the computer system 1100. One or more processors may be included in the processing unit 1104. These processors may include single-core or multi-core processors. In some specific embodiments, the processing unit 1104 may be implemented as one or more independent processing units 1132 and / or 1134, each of which includes a single-core or multi-core processor. In other specific embodiments, the processing unit 1104 may also be implemented as a quad-core processing unit formed by integrating two dual-core processors on a single chip.

[0062] In various specific embodiments, the processing unit 1104 can execute various programs in response to program code and can maintain multiple concurrently executed programs or processes. At any given time, some or all of the program code to be executed may reside in the processor 1104 and / or the storage subsystem 1118. Through appropriate programming, the processor 1104 can provide the various functions described above. The computer system 1100 may additionally include a processing acceleration unit 1106, which may include a digital signal processor (DSP), a special processor, and / or the like.

[0063] I / O subsystem 1108 may include user interface input devices and user interface output devices. User interface input devices may include keyboards, pointing devices such as mice or trackballs, touch pads or touch screens incorporated into displays, scroll wheels, click wheels, dials, buttons, switches, keypads, audio inputs with voice command recognition systems, microphones, and other types of input devices. User interface input devices may include, for example, motion sensing and / or gesture recognition devices, such as Microsoft Motion sensors, which allow users to control and interact with input devices such as Microsoft 360 game controller, a natural user interface using gestures and verbal commands. User interface input devices may also include eye gesture recognition devices such as Google Blink detector, which detects the user's eye activity (such as "blinking" when taking a picture and / or making a menu selection) and converts the eye gesture into an input device (such as Google ). In addition, the user interface input device may include a voice recognition sensing device that allows the user to communicate with the voice recognition system (e.g., Navigator) interaction.

[0064] The user interface input device may also include, but is not limited to, a three-dimensional (3D) mouse, a joystick or pointing stick, a game controller, and a drawing board, as well as an audio / video device, such as a speaker, a digital camera, a digital video recorder, a portable media player, a webcam, an image scanner, a fingerprint scanner, a barcode reader 3D scanner, a 3D printer, a laser rangefinder, and a sight tracking device. In addition, the user interface input device may include, for example, a medical imaging input device, such as a computer tomography, a magnetic resonance imaging, a position emission tomography, a medical ultrasound device. The user interface input device may also include, for example, an audio input device, such as a MIDI keyboard, a digital musical instrument, etc.

[0065] User interface output devices may include a display subsystem, indicator lights, or non-visual displays such as audio output devices. The display subsystem may be a cathode ray tube (CRT), a flat panel device (such as a device using a liquid crystal display (LCD) or plasma display), a projection device, a touch screen, and the like. In general, the use of the term "output device" is intended to include all possible types of devices and mechanisms for outputting information from the computer system 1100 to a user or another computer. For example, user interface output devices may include, but are not limited to, various display devices that visually convey text, graphics, and audio / video information, such as monitors, printers, speakers, headphones, car navigation systems, plotters, voice output devices, and modems.

[0066] Computer system 1100 may include storage subsystem 1118, which includes software elements, shown currently located within system memory 1110. System memory 1110 may store program instructions loadable and executable on processing unit 1104, as well as data generated during execution of these programs.

[0067] Depending on the configuration and type of computer system 1100, system memory 1110 may be volatile (e.g., random access memory (RAM)) and / or non-volatile (e.g., read-only memory (ROM), flash memory, etc.). RAM typically contains data and / or program modules that are immediately accessible and / or currently being operated on and executed by processing unit 1104. In some embodiments, system memory 1110 may include multiple different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some embodiments, a basic input / output system (BIOS), which contains basic routines that help transfer information between elements within computer system 1100, such as during startup, may typically be stored in ROM. By way of example and not limitation, system memory 1110 also illustrates application programs 1112, which may include client applications, web browsers, middle-tier applications, relational database management systems (RDBMS), etc., program data 1114, and an operating system 1116. For example, operating system 1116 may include various versions of Microsoft Apple and / or Linux operating systems, various commercially available or UNIX-like operating systems (including but not limited to various GNU / Linux operating systems, Google OS, etc.) and / or mobile operating systems (such as iOS, Phone, OS, 10OS and OS operating system).

[0068] The storage subsystem 1118 may also provide a tangible computer-readable storage medium for storing basic programming and data structures that provide the functionality of some specific embodiments. Software (programs, code modules, instructions) that provide the above-mentioned functionality when executed by the processor may be stored in the storage subsystem 1118. These software modules or instructions may be executed by the processing unit 1104. The storage subsystem 1118 may also provide a repository for storing data used according to some specific embodiments.

[0069] The storage subsystem 1100 may also include a computer-readable storage media reader 1120 that may be further connected to a computer-readable storage media 1122. Together with and optionally in conjunction with the system memory 1110, the computer-readable storage media 1122 may comprehensively represent remote, local, fixed and / or removable storage devices and are used to temporarily and / or more permanently contain, store, transfer, and retrieve computer-readable information.

[0070] The computer-readable storage medium 1122 containing the code or part of the code may also include any suitable media, including storage media and communication media, such as, but not limited to, volatile and non-volatile, removable and non-removable media for storing and / or transmitting information implemented in any method or technology. This may include tangible computer-readable storage media, such as RAM, ROM, electrically erasable programmable ROM (EEPROM), flash memory or other storage technology, CD-ROM, digital versatile disk (DVD) or other optical storage, cassettes, magnetic tape, disk storage or other magnetic storage devices, or other tangible computer-readable media. This may also include intangible computer-readable media, such as data signals, data transmissions, or any other medium that can be used to transmit the desired information and can be accessed by the computing system 1100.

[0071] By way of example, computer-readable storage media 1122 may include a hard disk drive that reads from or writes to non-removable nonvolatile magnetic media, a disk drive that reads from or writes to removable nonvolatile disks, and a disk drive that reads from or writes to removable nonvolatile optical disks such as CD ROMs, DVDs, and The computer readable storage medium 1122 may include, but is not limited to, a drive, a flash memory card, a universal serial bus (USB) flash drive, a secure digital (SD) card, a DVD disk, a digital video tape, etc. The computer readable storage medium 1122 may also include a solid-state drive (SSD) based on non-volatile memory, such as a flash-based SSD, an enterprise flash drive, a solid-state ROM, etc., an SSD based on volatile memory, such as a solid-state RAM, a dynamic RAM, a static RAM, a DRAM-based SSD, a magnetoresistive RAM (MRAM) SSD, and a hybrid SSD that uses a combination of DRAM and a flash-based SSD. The disk drive and its associated computer readable medium may provide non-volatile storage of computer readable instructions, data structures, program modules, and other data for the computer system 1100.

[0072] The communication subsystem 1124 provides an interface to other computer systems and networks. The communication subsystem 1124 serves as an interface for receiving data from other systems of the computer system 1100 and transmitting data to other systems. For example, the communication subsystem 1124 can enable the computer system 1100 to be connected to one or more devices via the Internet. In some specific embodiments, the communication subsystem 1124 may include a radio frequency (RF) transceiver component for accessing a wireless voice and / or data network (e.g., using cellular phone technology, advanced data network technology, such as 3G, 4G or EDGE (Enhanced Global Evolution Data Rate), WiFi (IEEE 802.11 series standards or other mobile communication technologies, or any combination thereof), a global positioning system (GPS) receiver component, and / or other components. In some specific embodiments, the communication subsystem 1124 may provide a wired network link (e.g., Ethernet) to supplement or replace the wireless interface.

[0073] In some particular embodiments, communication subsystem 1124 may also receive incoming communications in the form of structured and / or unstructured data feeds 1126 , event streams 1128 , event updates 1130 , and the like on behalf of one or more users that may use computer system 1100 .

[0074] For example, the communication subsystem 1124 may be configured to receive data feeds 1126 in real time from users of a social network and / or other communication service, e.g. feed, Updates, web page feeds (such as Rich Site Summary (RSS) feeds), and / or real-time updates from one or more third-party information sources.

[0075] In addition, the communication subsystem 1124 can also be configured to receive data in the form of a continuous data stream, which can include an event stream 1128 of real-time events and / or event updates 1130, which can be continuous or essentially unbounded without a clear end. Examples of applications that generate continuous data can include, for example, sensor data applications, financial quotes, network performance measurement tools (such as network monitoring and traffic management applications), clickstream analysis tools, automobile traffic monitoring, etc.

[0076] The communication subsystem 1124 may also be configured to output structured and / or unstructured data feeds 1126 , event streams 1128 , event updates 1130 , etc. to one or more databases, which may be in computer communication with one or more streaming data source computers coupled to the computer system 1100 .

[0077] Computer system 1100 may be one of various types, including a handheld portable device (e.g., Cellular phone, computing tablets, PDAs), wearable devices (e.g., Google head mounted displays), PCs, workstations, mainframes, kiosks, server racks, or any other data processing system.

[0078] Due to the ever-changing nature of computers and networks, the description of the computer system 1100 depicted in the figure is intended only as a specific example. Many other configurations with more or fewer components than the system depicted in the figure are possible. For example, customized hardware can also be used and / or specific elements can be implemented in hardware, firmware, software (including applets), or a combination. In addition, links with other computing devices, such as network input / output devices, can be adopted. Based on the disclosure and teachings provided herein, other ways and / or methods of implementing various specific embodiments should be obvious.

[0079] As used herein, the term "about" or "approximately" or "substantially" may be interpreted as being within the range expected by one of ordinary skill in the art based on the specification.

[0080] In the foregoing description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of various specific embodiments. However, it is apparent that some specific embodiments may be practiced without some of these specific details. In other cases, well-known structures and devices are shown in block diagram form.

[0081] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. Instead, the foregoing description of various embodiments will provide a disclosure that can be implemented to implement at least one embodiment. It should be understood that various changes may be made to the function and arrangement of components without departing from the spirit and scope of the various embodiments set forth in the appended claims.

[0082] Specific details are given in the foregoing description to provide a thorough understanding of the specific embodiments. However, it should be understood that the specific embodiments may be implemented without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form to avoid obscuring the specific embodiments with unnecessary details. In other cases, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary details to avoid obscuring the specific embodiments.

[0083] In addition, it should be noted that various specific embodiments may have been described as processes, and processes are depicted as flow charts, flow diagrams, data flow diagrams, structure diagrams, or block diagrams. Although flow charts may describe operations as sequential processes, many operations can be performed in parallel or simultaneously. In addition, the order of operations can be rearranged. After the operations of the process are completed, they will terminate, but there may be other steps not included in the figure. The process can correspond to a method, function, procedure, subroutine, subprogram, etc. When the process corresponds to a function, its termination can correspond to the return of this function to the calling function or main function.

[0084] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing or carrying instructions and / or data. Code segments or machine executable instructions can represent any combination of procedures, functions, subroutines, programs, routines, subroutines, modules, software packages, classes, or instructions, data structures, or program statements. Code segments can be coupled to another code segment or hardware circuit by passing and / or receiving information, data, variables, parameters, or memory contents. Information, variables, parameters, data, etc. can be passed, forwarded, or transmitted in any suitable manner, including memory sharing, message passing, token passing, network transmission, etc.

[0085] In addition, specific embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments that perform the necessary tasks may be stored in a machine-readable medium. A processor may perform the necessary tasks.

[0086] In the above description, features are described in conjunction with their specific embodiments, but it should be appreciated that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used alone or in combination. In addition, without departing from the broader spirit and scope of this specification, the embodiments may be used in any number of environments and applications other than those described herein. Therefore, the description and drawings are to be considered illustrative rather than restrictive.

[0087] In addition, for the purpose of illustration, the methods are described in a specific order. It should be understood that in alternative specific embodiments, these methods can be performed in an order different from the order described. It should also be understood that the above methods can be performed by hardware components or can be embodied in a machine executable instruction sequence, which can be used to make a machine, such as a general or special processor or logic circuit, programmed to perform the method through instructions. These machine executable instructions can be stored on one or more machine readable media, such as CD-ROM or other types of optical disks, floppy disks, ROM, RAM, EPROM, EEPROM, magnetic cards or optical cards, flash memory or other types of machine readable media suitable for storing electronic instructions. Alternatively, these methods can be performed by a combination of hardware and software.

Claims

1. A three-dimensional (3D) stacked electronic component, comprising: Printed circuit boards; Package substrate; a plurality of integrated circuit (IC) packages mounted to the package substrate; as well as A substrate frame, the substrate frame is disposed between the printed circuit board and the packaging substrate in the 3D stacked electronic component, wherein: The substrate frame defines a cavity inside the substrate frame and between the printed circuit board and the packaging substrate; The plurality of IC packages are mounted to the package substrate within the cavity; and The substrate frame is divided into a plurality of frame parts, and the plurality of frame parts are separated by spaces between the plurality of frame parts.

2. The electronic assembly of claim 1, further comprising a second plurality of IC packages, wherein: The package substrate includes a first side, and the plurality of IC packages are mounted to the first side within the cavity; The package substrate includes a second side, the second plurality of IC packages being mounted to the second side; and The second plurality of IC packages are mounted to the second side of the packaging substrate within a footprint of the cavity. 3 . The electronic assembly of claim 2 , wherein the second plurality of IC packages includes fewer IC packages than the plurality of IC packages, thereby causing warpage in the package substrate. 4 . The electronic assembly of claim 3 , wherein the spaces between the plurality of frame portions of the substrate frame are located beside the warpage in the package substrate to reduce the warpage.

5. The electronic assembly of claim 1, wherein the printed circuit board extends beyond a footprint of the package substrate. 6 . The electronic component according to claim 1 , further comprising a second packaging substrate, the second packaging substrate being mounted to the printed circuit board via a second substrate frame.

7. A substrate frame for three-dimensional (3D) stacking of electronic components, the substrate frame comprising: a first side including a first interconnect configured to be mounted to a first substrate having a plurality of integrated circuit (IC) packages mounted to the first substrate; a second side, the second side comprising a second interconnect, the second interconnect configured to be mounted to a second substrate, such that the substrate frame is disposed between the first substrate and the second substrate in the 3D stacked electronic assembly, and a cavity is defined within the substrate frame and between the first substrate and the second substrate, the plurality of integrated IC packages being mounted in the cavity; as well as A plurality of frame portions are separated by spaces between the plurality of frame portions. The substrate frame of claim 7 , wherein the substrate frame has a rectangular shape. 9 . The substrate frame of claim 7 , wherein the space separating the plurality of frame portions is located on a side of the substrate frame. 10 . The substrate frame of claim 7 , wherein the space separating the plurality of frame portions is located at a corner of the substrate frame.

11. The substrate frame of claim 7, wherein a width of the plurality of frame portions is maintained across the spaces between the plurality of frame portions.

12. The substrate frame of claim 7, wherein the spaces between the plurality of frame portions are located in the substrate frame such that the substrate frame is symmetrical about an axis. 13 . The substrate frame of claim 7 , wherein a width of the plurality of frame portions is at least five times greater than a length of the space between the plurality of frame portions.

14. A method of assembling a three-dimensional (3D) stacked electronic component, the method comprising: mounting a plurality of integrated circuit (IC) packages to a first substrate; as well as A substrate frame is connected to the first substrate and to the second substrate, wherein: The substrate frame defines a cavity inside the substrate frame and between the first substrate and the second substrate; The plurality of IC packages are mounted to the first substrate within the cavity; and The substrate frame is divided into a plurality of frame parts, and the plurality of frame parts are separated by spaces between the plurality of frame parts.

15. The method of claim 14, further comprising identifying a region of the first substrate having warpage.

16. The method of claim 15, wherein identifying the region of the first substrate having the warpage comprises measuring a displacement of the region of the first substrate after mounting the plurality of IC packages to the first substrate relative to a displacement of the region of the first substrate before mounting the plurality of IC packages to the first substrate. 17 . The method of claim 16 , further comprising measuring the displacement of the region of the first substrate after coupling the substrate frame to the first substrate to determine whether the displacement of the region has been reduced by mounting the first substrate to the substrate frame.

18. The method of claim 15, wherein identifying the region of the first substrate having the warpage comprises simulating a 3D model of the first substrate, wherein the first substrate has the plurality of IC packages mounted to the first substrate.

19. The method of claim 18, further comprising simulating the 3D model of the substrate frame connected to the 3D model of the first substrate to determine whether the warpage of the region has been reduced by adding the 3D model of the substrate frame.

20. The method of claim 14, further comprising: determining the position of the space between the plurality of frame portions in the substrate frame based on an output provided by a machine learning model, wherein the machine learning model is trained to receive the positions of the plurality of IC packages and output the position of the space.

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