Service life intelligent evaluation system adaptive to power semiconductor device design

Abstract

The invention belongs to the field of semiconductor life evaluation, relates to a data analysis technology, and is used for solving the problems that in the prior art, feature analysis cannot be performed according to life test results of different types of semiconductor devices, and links such as sample extraction and key test parameter optimization cannot be performed by combining feature analysis results. The intelligent service life evaluation system adapted to the power semiconductor device design comprises a sampling analysis module, a balance evaluation module, a tendency evaluation module and an evaluation analysis module, the sampling analysis module is in communication connection with the balance evaluation module and the tendency evaluation module, and the evaluation analysis module is in communication connection with the balance evaluation module and the tendency evaluation module; according to the method, evaluation samples of the power semiconductor device can be extracted, and evaluation modes of the power semiconductor device can be marked according to evaluation test results of different device types in an evaluation period, so that an acceleration model can be reasonably distributed in a next evaluation period.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor life assessment and relates to data analysis technology, and specifically is a service life intelligent assessment system suitable for power semiconductor device design. Background Art

[0002] Power semiconductors are semiconductor devices used to control and regulate electricity. They have the advantages of high efficiency, fast switching and high temperature resistance, and are widely used in power electronics, electric vehicles, renewable energy and other fields. With the continuous increase in electricity demand, the importance of power semiconductor technology in the power system has become increasingly prominent. In the future, power semiconductor technology will continue to develop in the direction of high efficiency, intelligence and sustainability to meet the increasingly complex electricity needs.

[0003] The invention patent with announcement number CN116164935A discloses a life assessment method and system for a high-power semiconductor laser beam combining module. The assessment system accurately assesses whether the beam combining module meets the life indicators in a short time, improves the assessment efficiency and reduces the assessment cost; however, the assessment system can only test multiple performance parameters of semiconductor devices in sequence, but cannot perform feature analysis based on the life test results of different types of semiconductor devices, and optimize the sample extraction, key test parameters and other links based on the feature analysis results, resulting in low assessment efficiency and accuracy of the assessment results.

[0004] In view of the above technical problems, this application proposes a solution. Summary of the invention

[0005] The purpose of the present invention is to provide an intelligent service life evaluation system adapted to the design of power semiconductor devices, which is used to solve the problem that the prior art cannot perform feature analysis based on the life test results of different types of semiconductor devices, and optimize the sample extraction, key test parameters and other links in combination with the feature analysis results; The technical problem to be solved by the present invention is: how to provide an intelligent service life evaluation system for power semiconductor device design that can perform feature analysis based on the life test results of different types of semiconductor devices, and optimize sample extraction, key test parameters and other links based on the feature analysis results.

[0006] The purpose of the present invention can be achieved through the following technical solutions: An intelligent service life assessment system adapted for power semiconductor device design includes a sampling analysis module, a balanced assessment module, a tendency assessment module and an assessment analysis module; the sampling analysis module is communicatively connected to the balanced assessment module and the tendency assessment module, and the assessment analysis module is communicatively connected to the balanced assessment module and the tendency assessment module; The sampling analysis module is used to extract evaluation samples of power semiconductor devices: generate continuous evaluation cycles, mark the power semiconductor devices to be evaluated in the same batch as evaluation objects, randomly select L1 samples from the evaluation objects as test objects, and mark the evaluation modes of all device types as balanced modes at the beginning of the first evaluation cycle; at the end of each evaluation cycle, mark the evaluation mode of the device type in the next evaluation cycle as balanced mode or tendency mode; The balanced evaluation module is used to perform life evaluation analysis on the test object using a balanced mode; The tendency assessment module is used to perform life assessment analysis on the test object using a tendency model; The evaluation and analysis module is used to evaluate and analyze the life test data of the test object: the test objects that fail the life test simulated by the corresponding accelerated model are marked as faulty objects, the number of faulty objects is marked as the fault value, the ratio of the fault value to L1 is marked as the fault coefficient, and whether the life evaluation result of the evaluation object is qualified is determined by the fault coefficient.

[0007] Furthermore, the specific process of marking the evaluation mode of the device type includes: using an accelerated model to perform life evaluation analysis on the test object within the evaluation cycle, the accelerated models include the Arrhenius model, the inverse power law model, the Eyring model and the Coffin-Manson model, and at the end of the evaluation cycle, the fault objects of each device type are centrally analyzed and the evaluation mode of the device type in the next evaluation cycle is marked as a balanced mode or a tendency mode.

[0008] Furthermore, the specific process of centralized analysis of fault objects of device types includes: marking the acceleration model adopted by the fault objects of the same device type as the diagnostic model of the fault object, marking the number of times the acceleration model is marked as the diagnostic model as the diagnostic value, performing variance calculation on the diagnostic values ​​of all acceleration models corresponding to the same device type to obtain a tendency coefficient, and comparing the tendency coefficient with a preset tendency threshold: if the tendency coefficient is less than the tendency threshold, marking the evaluation mode of the device type in the next evaluation cycle as the balanced mode; if the tendency coefficient is greater than or equal to the tendency threshold, marking the evaluation mode of the device type in the next evaluation cycle as the tendency mode, marking the sum of the diagnostic values ​​of all acceleration models as the fault cardinality, and marking the ratio of the diagnostic value of the acceleration model to the fault cardinality as the allocation coefficient of the acceleration model.

[0009] Furthermore, the specific process of the balanced assessment module using the balanced mode to perform life assessment analysis on the test object includes: uniformly and randomly assigning the test object to the acceleration model, and performing life test analysis on the test object according to the assigned acceleration model.

[0010] Furthermore, the specific process of the tendency assessment module using the tendency model to perform life assessment analysis on the test object includes: marking the product of L1 and the distribution coefficient as the distribution value of the acceleration model, randomly distributing the test object to the acceleration model according to the distribution value, and performing life test analysis on the test object according to the distributed acceleration model.

[0011] Furthermore, the specific process of determining whether the life assessment result of the assessment object is qualified includes: comparing the fault coefficient with the preset fault threshold: if the fault coefficient is less than the fault threshold, the life assessment result of the assessment object is determined to be qualified; if the fault coefficient is greater than or equal to the fault threshold, the life assessment result of the assessment object is determined to be unqualified, generating a life abnormality signal and sending the life abnormality signal to the mobile phone terminal of the administrator.

[0012] Furthermore, it also includes a sampling optimization module, which is communicatively connected with the evaluation and analysis module and the sampling analysis module; The sampling optimization module is used to optimize and analyze the sample extraction link of power semiconductor devices: in the first evaluation cycle, before the life test analysis of the test object is performed on the test object through the acceleration model, basic tests are performed on all test objects and basic parameters of the test objects are obtained, the basic parameters include on-resistance, size error, rated current and rated voltage, all test objects of the same device type are sorted according to the value of a single basic parameter to obtain resistance sequence, size sequence, current sequence and voltage sequence respectively, wherein the resistance sequence and error sequence are arranged in the order of the basic parameter value from large to small, and the current sequence and voltage sequence are arranged in the order of the basic parameter value from small to large, the serial numbers of the fault objects screened out in the evaluation and analysis process of the same device type in the resistance sequence, size sequence, current sequence and voltage sequence are summed and averaged, and the resistance priority value, size priority value, current priority value and voltage priority value are obtained, and the basic parameter corresponding to the minimum value among the resistance priority value, size priority value, current priority value and voltage priority value is marked as the priority parameter of the device type; the priority parameters of all device types are sent to the sampling analysis module.

[0013] Furthermore, in the subsequent evaluation cycle, the sampling analysis module performs basic tests on all evaluation objects according to their device types and obtains priority parameters of the evaluation objects, sorts the evaluation objects according to the sorting rules of the priority parameters to obtain a priority sequence, and marks the first L1 evaluation objects in the priority sequence as test objects.

[0014] The present invention has the following beneficial effects: 1. The sampling analysis module can extract evaluation samples of power semiconductor devices, and mark their evaluation modes according to the evaluation test results of different device types in the evaluation cycle, so that the acceleration model can be rationally allocated in the next evaluation cycle to improve the accuracy of the life evaluation results; 2. The balanced evaluation module can be used to distribute the acceleration models to the test objects in a balanced manner, so that the number of test objects obtained by different acceleration models is equal, ensuring the coverage of the acceleration model test performance. The tendency evaluation module can be used to distribute the acceleration models to the test objects in a tendency manner, and the number of test objects is distributed according to the distribution coefficients of different acceleration models corresponding to the device type, so that the acceleration models with high failure rates can be allocated with more samples. 3. The evaluation and analysis module can be used to evaluate and analyze the life test data of the test object, and the failure coefficient can be obtained by comprehensive analysis of the accelerated test results of all test objects in the same batch. The overall life performance of the semiconductor devices in this batch can be evaluated through the failure coefficient, and feedback and warning can be given in time when abnormalities occur; 4. The sampling optimization module can be used to optimize and analyze the sample extraction process of power semiconductor devices, and the priority parameters can be screened based on the basic parameter values ​​of the test object and the marking of the faulty object, thereby providing a reference for subsequent sample extraction. The failure rate of power semiconductors can be pre-evaluated through basic parameters to improve the accuracy of sample extraction, thereby further ensuring the validity of the test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A system block diagram of the present invention as a whole; Figure 2 is a system block diagram of Embodiment 1 of the present invention; Figure 3 is a system block diagram of Embodiment 2 of the present invention; Figure 4 This is a method flow chart of embodiment 3 of the present invention. DETAILED DESCRIPTION

[0017] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] like Figure 1 As shown, an intelligent service life evaluation system suitable for power semiconductor device design includes an evaluation and analysis subsystem and a test optimization subsystem. The evaluation and analysis subsystem includes a sampling analysis module, a balance evaluation module, a tendency evaluation module and an evaluation and analysis module; the test optimization subsystem includes a sampling optimization module and a performance optimization module.

[0019] Embodiment 1: Figure 2 As shown, the sampling analysis module is communicatively connected with the balance assessment module and the tendency assessment module, and the assessment analysis module is communicatively connected with the balance assessment module and the tendency assessment module.

[0020] The sampling analysis module is used to extract evaluation samples of power semiconductor devices: generate continuous evaluation cycles, mark the power semiconductor devices to be evaluated in the same batch as evaluation objects, randomly select L1 samples from the evaluation objects as test objects, L1 is a numerical constant, and the specific value of L1 is set by the management personnel; at the beginning of the first evaluation cycle, the evaluation mode of all device types is marked as balanced mode; at the end of each evaluation cycle, the evaluation mode of the device type in the next evaluation cycle is marked as balanced mode or tendency mode: within the evaluation cycle, an accelerated model is used to perform life evaluation analysis on the test object, and the accelerated models include the Arrhenius model, the inverse power law model, the Eyring model and the Coffin-Manson model.

[0021] ‌The Arrhenius model is one of the most commonly used accelerated life test models, mainly used to describe the effect of temperature on product life. The Arrhenius model is based on the relationship between chemical reaction rate and temperature, and accelerates life tests by increasing temperature. The inverse power law model describes the relationship between electrical stresses such as voltage, current, and power and product life; The Eyring Model describes the relationship between product life and temperature stress. The Eyring Model is also used in accelerated life testing, especially when changes in temperature and pressure are involved; Coffin-Manson model: Suitable for simulating fatigue failure under temperature alternating stress; this model reflects the fatigue failure process under temperature alternating stress and is often used to simulate the crack propagation process of solder joints.

[0022] At the end of the evaluation cycle, the fault objects of each device type are centrally analyzed: the acceleration model used by the fault objects of the same device type is marked as the diagnostic model of the fault object, the number of times the acceleration model is marked as the diagnostic model is marked as the diagnostic value, the variance of the diagnostic values ​​of all acceleration models corresponding to the same device type is calculated to obtain the tendency coefficient, and the tendency coefficient is compared with the preset tendency threshold: if the tendency coefficient is less than the tendency threshold, the evaluation mode of the device type in the next evaluation cycle is marked as the balanced mode; if the tendency coefficient is greater than or equal to the tendency threshold, the evaluation mode of the device type in the next evaluation cycle is marked as the tendency mode, the sum of the diagnostic values ​​of all acceleration models is marked as the fault base number, and the ratio of the diagnostic value of the acceleration model to the fault base number is marked as the allocation coefficient of the acceleration model; the evaluation modes of different device types are marked according to the evaluation test results in the evaluation cycle, so that the acceleration models can be rationally allocated in the next evaluation cycle to improve the accuracy of the life evaluation results.

[0023] The balanced assessment module is used to perform life assessment analysis on the test object using a balanced mode: the test object is evenly and randomly assigned to the acceleration model, and the life test analysis of the test object is performed according to the assigned acceleration model.

[0024] The tendency assessment module is used to perform life assessment analysis on the test object using a tendency model: mark the product of L1 and the allocation coefficient as the allocation value of the acceleration model, randomly allocate the test object to the acceleration model according to the allocation value, and perform life test analysis on the test object according to the allocated acceleration model; make the number of test objects allocated to different acceleration models equal to ensure the coverage of the acceleration model test performance. The tendency assessment module can be used to allocate a tendency to the acceleration model for the test object, and allocate the number of test objects according to the allocation coefficient of different acceleration models corresponding to the device type, so that the acceleration model with a high failure rate can be allocated a larger number of samples.

[0025] The evaluation and analysis module is used to evaluate and analyze the life test data of the test object: the test objects that have not passed the life test simulated by the corresponding accelerated model are marked as faulty objects, the number of faulty objects is marked as the fault value, the ratio of the fault value to L1 is marked as the fault coefficient, and the fault coefficient is compared with the preset fault threshold: if the fault coefficient is less than the fault threshold, the life evaluation result of the evaluation object is judged to be qualified; if the fault coefficient is greater than or equal to the fault threshold, the life evaluation result of the evaluation object is judged to be unqualified, and a life anomaly signal is generated and sent to the mobile phone terminal of the manager; the accelerated test results of all test objects in the same batch are comprehensively analyzed to obtain the fault coefficient, and the overall life performance of the batch of power semiconductor devices is evaluated through the fault coefficient, and timely feedback and early warning are provided in case of abnormalities.

[0026] Embodiment 2: Figure 3 As shown, the sampling optimization module is communicatively connected to the evaluation and analysis module and the sampling analysis module; the performance optimization module is communicatively connected to the evaluation and analysis module.

[0027] The sampling optimization module is used to optimize and analyze the sampling process of power semiconductor devices: in the first evaluation cycle, before the life test analysis of the test object is carried out through the acceleration model, basic tests are carried out on all test objects and the basic parameters of the test objects are obtained. The basic parameters include on-resistance, dimensional error, rated current and rated voltage. The on-resistance is the resistance value of the power semiconductor in the on state. Low on-resistance can reduce energy loss and improve equipment efficiency. The dimensional error is the sum of the errors of each measured dimension on the surface of the power semiconductor. The rated current is the maximum current that the power semiconductor can withstand. The high current handling capability is crucial for high-power applications. The rated voltage is the maximum voltage that the power semiconductor can withstand, which determines the stability and reliability of the device under high-voltage environment. All test objects of the same device type are sorted according to the value of a single basic parameter to obtain resistance sequence, size sequence, current sequence and voltage sequence, wherein the resistance sequence and error sequence are arranged in descending order according to the value of the basic parameter, and the current sequence and voltage sequence are arranged in descending order according to the value of the basic parameter, and the serial numbers of the fault objects screened out in the evaluation and analysis process of the same device type in the resistance sequence, size sequence, current sequence and voltage sequence are summed and averaged to obtain the resistance priority value, size priority value, current priority value and voltage priority value, and the basic parameter corresponding to the minimum value among the resistance priority value, size priority value, current priority value and voltage priority value is marked as the priority parameter of the device type; The priority parameters of all device types are sent to the sampling analysis module; in the subsequent evaluation cycle, the sampling analysis module performs basic tests on all evaluation objects according to their device types and obtains the priority parameters of the evaluation objects, sorts the evaluation objects according to the sorting rules of the priority parameters (i.e., when the priority parameter is on-resistance or dimensional error, the sorting rule is from large to small, and when the priority parameter is rated current or rated voltage, the sorting rule is from small to large) to obtain a priority sequence, and marks the first L1 evaluation objects in the priority sequence as test objects; the priority parameters are screened in combination with the basic parameter values ​​of the test objects and the marking of the faulty objects, so as to provide a reference basis for the subsequent sample extraction, and pre-evaluate the failure rate of power semiconductors through basic parameters to improve the accuracy of sample extraction, thereby further ensuring the validity of the test results.

[0028] The performance optimization module is used to perform performance optimization analysis on power semiconductor devices: when the evaluation mode of the device type is marked as the tendency mode at the end of the evaluation cycle, the test performance corresponding to the acceleration model with the largest diagnostic value is marked as the optimized performance of the device type, and the optimized performance of the device type is sent to the mobile terminal of the manager.

[0029] Embodiment 3: Figure 4 As shown, the intelligent service life evaluation method adapted for the design of power semiconductor devices includes the following steps: Step 1: Extract evaluation samples of power semiconductor devices: Generate a continuous evaluation cycle, mark the power semiconductor devices to be evaluated in the same batch as evaluation objects, randomly extract L1 samples from the evaluation objects as test objects, and execute step 2 or step 3; Step 2: Use the balanced mode to conduct life assessment analysis on the test objects: randomly assign the test objects to the acceleration model uniformly, and perform life test analysis on the test objects according to the assigned acceleration model; Step 3: Use the propensity model to conduct life assessment analysis on the test object: mark the product of L1 and the distribution coefficient as the distribution value of the acceleration model, randomly distribute the test object to the acceleration model according to the distribution value, and conduct life test analysis on the test object according to the allocated acceleration model; Step 4: Evaluate and analyze the life test data of the test objects: mark the test objects that fail the life test simulated by the corresponding accelerated model as faulty objects, mark the number of faulty objects as the fault value, mark the ratio of the fault value to L1 as the fault coefficient, and evaluate the overall life performance of the batch of power semiconductor devices through the fault coefficient.

[0030] An intelligent service life assessment system adapted to the design of power semiconductor devices generates continuous assessment cycles when working, marks the power semiconductor devices of the same batch to be assessed as assessment objects, randomly selects L1 samples from the assessment objects as test objects, and uses a balanced mode to perform a life assessment analysis on the test objects: the test objects are evenly and randomly assigned to the acceleration model, and a life test analysis is performed on the test objects according to the assigned acceleration model; or a tendency mode is used to perform a life assessment analysis on the test objects: the product of L1 and the allocation coefficient is marked as the allocation value of the acceleration model, the test objects are randomly assigned to the acceleration model according to the allocation value, and a life test analysis is performed on the test objects according to the assigned acceleration model; the test objects that fail the life test simulated by the corresponding acceleration model are marked as fault objects, the number of fault objects is marked as the fault value, the ratio of the fault value to L1 is marked as the fault coefficient, and the overall life performance of the batch of power semiconductor devices is evaluated by the fault coefficient.

[0031] The above contents are merely examples and explanations of the structure of the present invention. The technicians in this technical field may make various modifications or additions to the specific embodiments described or replace them in a similar manner. As long as they do not deviate from the structure of the invention or exceed the scope defined by the claims, they should all fall within the protection scope of the present invention.

[0032] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0033] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to only specific implementation methods. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An intelligent service life evaluation system adapted to the design of power semiconductor devices, characterized in that: It includes a sampling analysis module, a balanced assessment module, a tendency assessment module and an assessment analysis module; the sampling analysis module is communicatively connected with the balanced assessment module and the tendency assessment module, and the assessment analysis module is communicatively connected with the balanced assessment module and the tendency assessment module; The sampling analysis module is used to extract evaluation samples of power semiconductor devices: generate continuous evaluation cycles, mark the power semiconductor devices to be evaluated in the same batch as evaluation objects, randomly select L1 samples from the evaluation objects as test objects, and mark the evaluation modes of all device types as balanced modes at the beginning of the first evaluation cycle; and mark the evaluation mode of the device type in the next evaluation cycle as balanced mode or tendency mode at the end of each evaluation cycle; The balanced evaluation module is used to perform life evaluation analysis on the test object using a balanced mode; The tendency assessment module is used to perform life assessment analysis on the test object using a tendency model; The evaluation and analysis module is used to evaluate and analyze the life test data of the test object: the test objects that fail the life test simulated by the corresponding accelerated model are marked as faulty objects, the number of faulty objects is marked as the fault value, the ratio of the fault value to L1 is marked as the fault coefficient, and whether the life evaluation result of the evaluation object is qualified is determined by the fault coefficient.

2. The intelligent service life evaluation system adapted for power semiconductor device design according to claim 1, characterized in that: The specific process of marking the evaluation mode of the device type includes: using the acceleration model to perform life evaluation analysis on the test object within the evaluation cycle, the acceleration models include the Arrhenius model, the inverse power law model, the Eyring model and the Coffin-Manson model, and at the end of the evaluation cycle, the fault objects of each device type are centrally analyzed and the evaluation mode of the device type in the next evaluation cycle is marked as a balanced mode or a tendency mode.

3. The intelligent service life evaluation system adapted for power semiconductor device design according to claim 2, characterized in that: The specific process of centralized analysis of fault objects of device types includes: marking the acceleration model used by fault objects of the same device type as the diagnostic model of the fault object, marking the number of times the acceleration model is marked as the diagnostic model as the diagnostic value, performing variance calculation on the diagnostic values ​​of all acceleration models corresponding to the same device type to obtain a tendency coefficient, and comparing the tendency coefficient with a preset tendency threshold: if the tendency coefficient is less than the tendency threshold, the evaluation mode of the device type in the next evaluation cycle is marked as the balanced mode; if the tendency coefficient is greater than or equal to the tendency threshold, the evaluation mode of the device type in the next evaluation cycle is marked as the tendency mode, the sum of the diagnostic values ​​of all acceleration models is marked as the fault base number, and the ratio of the diagnostic value of the acceleration model to the fault base number is marked as the allocation coefficient of the acceleration model.

4. The intelligent service life evaluation system adapted for power semiconductor device design according to claim 3 is characterized in that: The specific process of the balanced assessment module using the balanced mode to perform life assessment analysis on the test object includes: uniformly and randomly assigning the test object to the acceleration model, and performing life test analysis on the test object according to the assigned acceleration model.

5. The intelligent service life evaluation system adapted for power semiconductor device design according to claim 4, characterized in that: The specific process of the tendency assessment module using the tendency model to perform life assessment analysis on the test object includes: marking the product of L1 and the distribution coefficient as the distribution value of the acceleration model, randomly assigning the test object to the acceleration model according to the distribution value, and performing life test analysis on the test object according to the assigned acceleration model.

6. The intelligent service life evaluation system adapted for power semiconductor device design according to claim 5, characterized in that: The specific process of determining whether the life assessment result of the assessment object is qualified includes: comparing the failure coefficient with the preset failure threshold: if the failure coefficient is less than the failure threshold, the life assessment result of the assessment object is determined to be qualified; if the failure coefficient is greater than or equal to the failure threshold, the life assessment result of the assessment object is determined to be unqualified, generating a life abnormality signal and sending the life abnormality signal to the mobile phone terminal of the manager.

7. The intelligent service life evaluation system adapted for power semiconductor device design according to claim 6, characterized in that: It also includes a sampling optimization module, which is communicatively connected with the evaluation and analysis module and the sampling analysis module; The sampling optimization module is used to optimize and analyze the sample extraction link of power semiconductor devices: in the first evaluation cycle, before the life test analysis of the test object is performed on the test object through the acceleration model, basic tests are performed on all test objects and basic parameters of the test objects are obtained, the basic parameters include on-resistance, size error, rated current and rated voltage, all test objects of the same device type are sorted according to the value of a single basic parameter to obtain resistance sequence, size sequence, current sequence and voltage sequence respectively, wherein the resistance sequence and error sequence are arranged in the order of the basic parameter value from large to small, and the current sequence and voltage sequence are arranged in the order of the basic parameter value from small to large, the serial numbers of the fault objects screened out in the evaluation and analysis process of the same device type in the resistance sequence, size sequence, current sequence and voltage sequence are summed and averaged, and the resistance priority value, size priority value, current priority value and voltage priority value are obtained, and the basic parameter corresponding to the minimum value among the resistance priority value, size priority value, current priority value and voltage priority value is marked as the priority parameter of the device type; the priority parameters of all device types are sent to the sampling analysis module.

8. The intelligent service life evaluation system adapted for power semiconductor device design according to claim 7, characterized in that: In the subsequent evaluation cycle, the sampling analysis module performs basic tests on all evaluation objects according to their device types and obtains priority parameters of the evaluation objects, sorts the evaluation objects according to the sorting rules of the priority parameters to obtain a priority sequence, and marks the first L1 evaluation objects in the priority sequence as test objects.

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