Pixel circuit and display device

Abstract

Some embodiments of the present application disclose a pixel circuit and a display device, the pixel circuit comprising a first transistor, a second transistor, a third transistor and a light emitting element, the first transistor being used for providing a driving signal for the light emitting element, the second transistor being used for providing a driving signal for the light emitting element; the second transistor is used for providing a control signal for controlling the light-emitting duration of the light-emitting element for the first transistor, and the third transistor is used for providing a reset signal for the second transistor and the first transistor in response to a reset control signal received by the grid electrode. According to the pixel circuit provided by the invention, the first transistor and the second transistor are combined with the pulse amplitude modulation and pulse width modulation driving mode, and meanwhile, the reset signals are provided for the first transistor and the second transistor only through the third transistor, so that the number of devices in the pixel circuit is reduced, and the pixel circuit reliability is improved. The area occupied by a pixel circuit in the display panel is saved, and the pixel density and the resolution of the display panel can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit and a display device. Background Art

[0002] Compared with AMOLED (Active matrix organic light emitting diode), micro LED has the advantages of smaller size, faster response speed, higher luminous efficiency, stronger stability and longer service life. Therefore, the display application field based on micro LED has developed rapidly. However, there are urgent problems to be solved for active micro LED display technology. Because the IV characteristic curve of micro LED is very steep, that is, the change in the voltage between the two poles of micro LED from low grayscale current to high grayscale current is very small, it is difficult to develop gray scale through traditional analog voltage drive, that is, PAM (Pulse Amplitude Modulation). Using the PAM drive method means that the drive circuit needs an extremely fast clock signal to meet the extremely high voltage resolution, which requires CMOS (Complementary Metal Oxide Semiconductor) drive, but the use of CMOS drive has an adverse effect on the flexibility, transparency and thickness of the panel.

[0003] Although the method of using PWM (Pulse Width Modulation) alone can partially solve the problems existing in the above-mentioned background technology, there are still many problems. Using the PWM solution, GOA (Gate Driven on Array) can be used to generate a drive control signal, and each frame display time can be divided into n sub-frames of equal proportion. Each pixel unit needs to be turned on once in each sub-frame time, and the data voltage input each time determines whether the micro-LED emits light at the time corresponding to the sub-frame. This method can achieve a higher grayscale, but the driving speed of the GOA circuit is limited. When the resolution is high, multiple openings cause the light-emitting element to be unable to emit light for a longer period of time, which in turn limits the increase in the number of grayscales.

[0004] Combining the PWM and PAM driving modes, the PAM module can increase the driving voltage of the light-emitting element while the PWM module can extend the light-emitting time of the light-emitting element, thereby achieving a higher grayscale without excessively high requirements for the circuit driving speed. However, using two driving modes will inevitably make the pixel circuit bear a larger number of components and occupy the area of ​​the display panel. Summary of the invention

[0005] In order to solve the problem that a large number of pixel circuit devices occupy a display panel area, the present application provides a pixel circuit and a display device.

[0006] The present application provides a pixel circuit, comprising a first transistor, a second transistor, a third transistor, a fourth transistor and a light-emitting element, wherein: the first electrode of the first transistor and the first electrode of the second transistor are used to receive a power supply signal, the second electrode of the first transistor is connected to the light-emitting element, and the second electrode of the second transistor is connected to the gate of the first transistor; the second electrode of the third transistor is connected to the gate of the first transistor and the gate of the second transistor, the first electrode of the third transistor is used to receive a reset signal, and the gate of the third transistor is used to receive a reset control signal; the first electrode of the fourth transistor is used to receive a first data signal, the second electrode of the fourth transistor is connected to the gate of the first transistor, and the gate of the fourth transistor is used to receive a first data write control signal; the first transistor is used to provide a driving signal for the light-emitting element, the second transistor is used to provide a control signal for controlling the light-emitting duration of the light-emitting element to the first transistor, and the third transistor is used to provide the reset signal to the gate of the first transistor and the gate of the second transistor in response to the reset control signal received by the gate; the fourth transistor is used to write the first data signal into the gate of the first transistor in response to the first data write control signal received by the gate.

[0007] The present application also provides a display device, including a data driving circuit, a scanning driving circuit, a data line, a scanning line and a pixel circuit, wherein: the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a light-emitting element; the second electrode of the first transistor is connected to the light-emitting element, and the second electrode of the second transistor is connected to the gate of the first transistor; the second electrode of the third transistor is connected to the gate of the first transistor and the gate of the second transistor, and the gate of the third transistor is used to receive a reset control signal; the second electrode of the fourth transistor is connected to the gate of the first transistor, and the gate of the fourth transistor is used to receive a first data writing control signal; the driving stage of the pixel circuit includes a first reset stage, a first compensation and data writing stage, a second reset stage, a second compensation stage, a second data writing stage and a light-emitting stage, wherein: the reset control signal is at a valid level in the first reset stage and the second reset stage; the first data writing control signal is at a valid level in the second data writing stage.

[0008] The present application provides a pixel circuit and a display device, wherein the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a light-emitting element, wherein: the first electrode of the first transistor and the first electrode of the second transistor are used to receive a power supply signal, the second electrode of the first transistor is connected to the light-emitting element, and the second electrode of the second transistor is connected to the gate of the first transistor; the second electrode of the third transistor is connected to the gate of the first transistor and the gate of the second transistor, the first electrode of the third transistor is used to receive a reset signal, and the gate of the third transistor is used to receive a reset control signal; the first electrode of the fourth transistor is used to receive a first data signal, the second electrode of the fourth transistor is connected to the gate of the first transistor, and the gate of the fourth transistor is used to receive a first data write control signal; the first transistor is used to provide a driving signal for the light-emitting element, the second transistor is used to provide a control signal for controlling the light-emitting duration of the light-emitting element to the first transistor, and the third transistor is used to provide the reset signal to the gate of the first transistor and the gate of the second transistor in response to the reset control signal received by the gate; the fourth transistor is used to write the first data signal into the gate of the first transistor in response to the first data write control signal received by the gate. The pixel circuit provided in the present application adopts a driving method combining pulse amplitude modulation and pulse width modulation through a first transistor and a second transistor. At the same time, a reset signal is provided to the first transistor and the second transistor only through a third transistor, thereby reducing the number of devices in the pixel circuit, saving the area occupied by the pixel circuit in the display panel, and effectively improving the pixel density and the resolution of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a planar structure of a display device according to one or more embodiments of the present application;

[0010] Figure 2 is a schematic structural diagram of a pixel circuit according to one or more embodiments of the present application;

[0011] Figure 3 is a schematic structural diagram of a pixel circuit according to another one or more embodiments of the present application;

[0012] Figure 4 is a schematic structural diagram of a pixel circuit according to another one or more embodiments of the present application;

[0013] Figure 5 is a schematic structural diagram of a pixel circuit according to another one or more embodiments of the present application;

[0014] Figure 6is a schematic structural diagram of a pixel circuit according to another one or more embodiments of the present application;

[0015] Figure 7 is a schematic structural diagram of a pixel circuit according to another one or more embodiments of the present application;

[0016] Figure 8 is a schematic structural diagram of a pixel circuit according to another one or more embodiments of the present application;

[0017] Fig. 9 is a schematic structural diagram of a pixel circuit according to another one or more embodiments of the present application;

[0018] Fig.10 is a schematic structural diagram of a pixel circuit according to another one or more embodiments of the present application;

[0019] Fig.11 is a driving signal timing diagram of a pixel circuit according to one or more embodiments of the present application;

[0020] Fig.12 A schematic diagram of a transistor conduction state in a pixel circuit according to one or more embodiments of the present application;

[0021] Fig.13 is a schematic diagram of a transistor conduction state in a pixel circuit according to another one or more embodiments of the present application;

[0022] Fig.14 is a schematic diagram of a transistor conduction state in a pixel circuit according to another one or more embodiments of the present application;

[0023] Fig.15 is a schematic diagram of a transistor conduction state in a pixel circuit according to another one or more embodiments of the present application;

[0024] Fig.16 is a schematic diagram of a transistor conduction state in a pixel circuit according to another one or more embodiments of the present application;

[0025] Fig.17 is a schematic diagram of a transistor conduction state in a pixel circuit according to another one or more embodiments of the present application;

[0026] Fig.18 is a schematic diagram of a transistor conduction state in a pixel circuit according to another one or more embodiments of the present application;

[0027] Fig.19 is a driving signal timing diagram of a pixel circuit according to another one or more embodiments of the present application;

[0028] Fig. 20is a driving signal timing diagram of a pixel circuit according to another one or more embodiments of the present application;

[0029] Fig.21 is a schematic structural diagram of a pixel circuit according to another one or more embodiments of the present application;

[0030] Fig. 22 is a driving signal timing diagram of a pixel circuit according to another one or more embodiments of the present application;

[0031] Fig.23 is a driving signal timing diagram of a pixel circuit according to another one or more embodiments of the present application;

[0032] Fig.24 is a driving signal timing diagram of a pixel circuit according to another one or more embodiments of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, implementation mode and advantages of the present application clearer, the exemplary implementation mode of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0034] Figure 1 is a plan view showing a display device according to an embodiment of the present application. Figure 1 According to an embodiment of the present application, a display device may include a pixel array unit 100, a control circuit 300, a data driving circuit 500 (e.g., a data driver), and a scan driving circuit 700 (e.g., a gate driver). The pixel array unit 100 may include a plurality of scan lines SL and a plurality of data lines DL disposed on a substrate, and a plurality of pixels P disposed in a plurality of pixel regions defined by intersections of the plurality of scan lines SL and the plurality of data lines DL.

[0035] Each of the plurality of pixels P may include a pixel circuit in the embodiment of the present application that displays an image based on a scan signal provided by an adjacent scan line SL and a data signal provided by an adjacent data line DL. In detail, the pixel circuit may include at least one thin film transistor and at least one capacitor, and the pixel circuit may be a liquid crystal unit that drives the liquid crystal to display an image based on an electric field based on a data signal, or may be a self-luminous unit that displays an image based on self-luminescence of a data signal. In this case, the self-luminous unit may include a plasma discharge element, a quantum dot light-emitting element, an organic light-emitting element, an inorganic light-emitting element, or a micro-light-emitting diode. The signals received by the pixel circuits in the following embodiments of the present application are all provided by the above-mentioned control circuit 300, the data drive circuit 500, and the scan drive circuit 700.

[0036] The control circuit 300 may generate pixel data corresponding to each of the plurality of pixels P based on the image signal. The control circuit 300 may generate a data control signal based on the timing synchronization signal to provide the data control signal to the data driving circuit 500. According to an example, the control circuit 300 may generate a scan control signal including a start signal and a plurality of scan clock signals based on the timing synchronization signal to provide the scan control signal to the scan driving circuit 700. The control circuit 300 may additionally generate a plurality of carry clock signals according to the driving mode of the scan driving circuit 700 to provide the plurality of carry clock signals to the scan driving circuit 700. The data driving circuit 500 may be connected to a plurality of data lines DL provided in the pixel array unit 100. The data driving circuit 500 may receive the pixel data and the data control signal provided from the control circuit 300, and may receive a plurality of reference gamma voltages provided from the power supply circuit. The data driving circuit 500 may convert the pixel data into a pixel-based analog data signal using the data control signal and the plurality of reference gamma voltages, and may provide the pixel-based analog data signal to the corresponding data line DL.

[0037] The scan driving circuit 700 may be connected to a plurality of scan lines SL provided in the pixel array unit 100. In detail, the scan driving circuit 700 may generate scan signals according to a predetermined order determined based on a scan control signal provided by the control circuit 300 and may provide the scan signals to corresponding scan lines SL.

[0038] According to one example, the scan driving circuit 700 may be integrated at one edge or both edges of the substrate according to the manufacturing process of the thin film transistor, and then connected to the plurality of scan lines SL in a one-to-one correspondence. For example, the scan driving circuit 700 may be provided in an integrated circuit, may be packaged in a substrate or a flexible circuit film, and may be connected to the plurality of scan lines SL in a one-to-one correspondence.

[0039] In the related art, in order to combine the PWM and PAM driving modes, it is necessary to add corresponding thin film transistors and / or capacitors in the pixel circuit. For example, both the PWM module and the PAM module need to be provided with thin film transistors for driving, and in order to achieve a better display effect, other circuit designs need to be made for the thin film transistors for driving, which inevitably makes the pixel circuit bear a larger number of devices, so that the pixel array unit 100 occupies more display panel area with the same number of light-emitting units, affecting the overall display effect of the display device. In addition, the number of scan lines SL and data lines DL, as well as the number of devices in the control circuit 300, the data driving circuit 500 and the scan driving circuit 700 also need to be increased accordingly, resulting in an increase in the border area of ​​the display device and the overall weight and volume.

[0040] In view of this, an embodiment of the present application provides a pixel circuit, such as Figure 2 As shown, Figure 2 The reference numeral 1 is the first electrode, 2 is the second electrode, and 3 is the gate. It can be understood by those skilled in the art that, due to the different levels of each signal in the pixel circuit in different implementation scenarios, for the same transistor, the first electrode can be the source electrode and the second electrode can be the drain electrode in one implementation scenario, and the first electrode can be the drain electrode and the second electrode can be the source electrode in another implementation scenario. The first electrode and the second electrode in the embodiment of the present application are only used to distinguish the two pins of the transistor other than the gate electrode, and no further restrictions are made. The same is true for other embodiments of the present application and other embodiment drawings, which will not be repeated.

[0041] The pixel circuit comprises a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a light emitting element LED, wherein:

[0042] The first electrode of the first transistor T1 and the first electrode of the second transistor T2 are used to receive the power signal VDD, and the second electrode of the first transistor T1 is connected to the light emitting element LED. The first transistor T1 is used to provide a driving signal for the light emitting element LED.

[0043] The second electrode of the second transistor T2 is connected to the gate of the first transistor T1. The second transistor T2 is used to provide a control signal for controlling the light emitting duration of the light emitting element to the first transistor T1.

[0044] Specifically, the first transistor T1 can provide driving signals of different amplitudes to the light-emitting element LED, realizing the PAM driving mode, and can provide a higher driving voltage for the light-emitting element LED, thereby improving the grayscale of the circuit. The second transistor T2 can control the on and off of the first transistor T1 by applying a light-emitting duration control signal to the gate of the first transistor T1, thereby controlling the time when the first transistor T1 provides the driving signal to the light-emitting element LED, and can also increase the proportion of the light-emitting time of the light-emitting device in the refresh frame, extend the light-emitting time of the light-emitting element LED, thereby realizing the PWM driving mode, thereby improving the brightness felt by the human eye, and thereby improving the grayscale of the circuit.

[0045] The second electrode of the third transistor T3 is connected to the gate of the first transistor T1 and the gate of the second transistor T2. The first electrode of the third transistor T3 is used to receive the reset signal REF, and the gate of the third transistor T3 is used to receive the reset control signal S3. The third transistor T3 is used to provide the reset signal REF to the second transistor T2 and the first transistor T1 in response to the reset control signal S3 received at the gate. Specifically, when the reset control signal S3 is at an effective level, the third transistor T3 is turned on, and the reset signal REF can be provided to the second electrode through the first electrode. Figure 2In the illustrated embodiment, the third transistor T3 is a P-type transistor and is turned on in response to a low level. The effective level of the reset control signal S3 is a low level. When the reset control signal S3 is a low level, the third transistor T3 is turned on, and the reset signal REF can be provided to the second electrode through the first electrode.

[0046] Specifically, Figure 1 and Figure 2 As shown, the reset control signal S3 is provided by the scan line SL. The reset signal REF can be provided by the data line DL, or can be connected to a fixed potential.

[0047] The first electrode of the fourth transistor T4 is used to receive the first data signal Date_PAM, the second electrode of the fourth transistor T4 is connected to the gate of the first transistor T1, and the gate of the fourth transistor T4 is used to receive the first data write control signal S5. The fourth transistor T4 is used to write the first data signal Date_PAM into the gate of the first transistor T1 in response to the first data write control signal S5 received at the gate. The above-mentioned first data signal Date_PAM is a PAM modulated data signal, which can adjust the brightness of the light-emitting element according to the voltage amplitude of the input signal. Specifically, when the first data write control signal S5 is at a valid level, the fourth transistor T4 is turned on, and the first data signal Date_PAM can be provided to the second electrode through the first electrode. Figure 2 In the illustrated embodiment, the fourth transistor T4 is a P-type transistor and is turned on in response to a low level. The effective level of the first data write control signal S5 is a low level. When the first data write control signal S5 is a low level, the fourth transistor T4 is turned on, and the first data signal Date_PAM can be provided to the second electrode through the first electrode.

[0048] Specifically, Figure 1 and Figure 2 As shown, the first data writing control signal S5 is provided by the scan line SL, and the first data signal Date_PAM is provided by the data line DL.

[0049] The first transistor T1 and the second transistor T2 are used as driving transistors. After each time the light emitting element LED is controlled to emit light, the gate potential thereof will change. Therefore, in order to make the state of the driving transistor the same at the beginning of each light emitting process, the first transistor T1 and the second transistor T2 need to be reset before controlling the light emitting element LED to emit light. In the related art, since the two transistors are located at different positions in the pixel circuit, two reset transistors are usually provided for the two driving transistors respectively, which increases the number of transistors in the pixel circuit to a certain extent. In this embodiment, the first transistor T1 and the second transistor T2 can be reset by a third transistor T3, which reduces one transistor for each pixel circuit. For the entire display device, N transistors in N pixel circuits are reduced, which directly reduces the number of devices in the display device, thereby saving the area occupied by the pixel circuit in the display panel, and effectively improving the pixel density and the resolution of the display panel.

[0050] Specifically, the above-mentioned light-emitting element LED is preferably a micro LED, or other light-emitting elements applicable to pixel circuits, which are not further limited herein.

[0051] During specific implementation, the specific model and parameters of the transistor in the embodiment of the present application can be set by technical personnel in this field according to actual conditions. It can be a P-type transistor or an N-type transistor, and can be a TFT (Thin Film Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or a low-temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) thin film transistor. No excessive restrictions are made here. The same applies to other transistors in the embodiment of the present application and will not be repeated.

[0052] In some embodiments, Figure 3 As shown, the pixel circuit further includes a fifth transistor T5, a first electrode of the fifth transistor T5 is connected to the gate of the second transistor T2, a second electrode of the fifth transistor T5 is connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3, and the gate of the fifth transistor T5 is used to receive the second compensation control signal S1. Specifically, as Figure 1 and Figure 3 As shown, the second compensation control signal S1 is provided by the scan line SL.

[0053] The fifth transistor T5 is used to provide the reset signal REF provided by the third transistor T3 received at the second electrode to the gate of the second transistor T2 through the first electrode in response to the second compensation control signal S1 received through the gate; the fifth transistor T5 is also used to provide threshold compensation for the second transistor T2 in response to the second compensation control signal S1 received through the gate.

[0054] Specifically, when the third transistor T3 is turned on and the second transistor T2 needs to be reset, the second compensation control signal S1 is at an effective level, the fifth transistor T5 is turned on, and the reset signal REF provided by the third transistor T3 is provided to the gate of the second transistor T2. When threshold compensation is required for the second transistor T2, the second compensation control signal S1 is at an effective level, the fifth transistor T5 is turned on, and the level of the second electrode of the second transistor T2 is compensated to the gate, thereby completing the threshold compensation for the second transistor T2. Figure 3 In the embodiment shown, the third transistor T3 and the fifth transistor T5 are both P-type transistors and are turned on in response to a low level, and the effective levels of the reset control signal S3 and the second compensation control signal S1 are both low levels; when the third transistor T3 is turned on and the second transistor T2 needs to be reset, the second compensation control signal S1 is low, the fifth transistor T5 is turned on, and the reset signal REF provided by the third transistor T3 is provided to the gate of the second transistor T2; when the threshold compensation is required for the second transistor T2, the second compensation control signal S1 is low, the fifth transistor T5 is turned on, and the level of the second pole of the second transistor T2 is compensated to the gate, thereby completing the threshold compensation of the second transistor T2. Specifically, due to the influence of the uniformity of the process manufacturing, the drift of the threshold voltage of the second transistor T2 will affect the size of the driving current or driving voltage of the light-emitting element, resulting in the uneven wavelength of the light emitted by the light-emitting element, thereby affecting the display color and display effect of the panel. In the above embodiment of the present application, by adding the fifth transistor T5 between the gate and the second pole of the second transistor T2, the threshold compensation of the second transistor T2 can be performed, thereby achieving a better display effect. Meanwhile, the fifth transistor T5 is disposed between the gate of the second transistor T2 and the second electrode of the third transistor T3, and can cooperate with the third transistor T3 to reset the second transistor T2, thereby eliminating the need to provide an additional reset transistor for the second transistor T2.

[0055] In some embodiments, Figure 4As shown, it also includes a sixth transistor T6, the first electrode of the sixth transistor T6 is connected to the first electrode of the second transistor T2, the second electrode of the sixth transistor T6 is used to receive the second data signal Date_PWM, and the gate of the sixth transistor T6 is used to receive the second data write control signal S2. The sixth transistor T6 is used to write the second data signal Date_PWM into the first electrode of the second transistor T2 in response to the second data write control signal S2 received at the gate. Specifically, when the second transistor T2 is turned on, the second data signal Date_PWM is transmitted to the second electrode of the second transistor T2. Specifically, when the second data write control signal S2 is at a valid level, the sixth transistor T6 is turned on, and the second data signal Date_PWM can be provided to the first electrode through the second electrode. Figure 4 In the illustrated embodiment, the sixth transistor T6 is a P-type transistor and is turned on in response to a low level. The effective level of the second data write control signal S2 is a low level. When the second data write control signal S2 is a low level, the sixth transistor T6 is turned on, and the second data signal Date_PWM can be provided to the first electrode through the second electrode.

[0056] Specifically, Figure 1 and Figure 4 As shown, the second data writing control signal S2 is provided by the scan line SL, and the second data signal Date_PWM is provided by the data line DL.

[0057] The fifth transistor T5 is also used to respond to the second compensation control signal S1 received through the gate, provide threshold compensation for the second transistor T2, and provide the second data signal Date_PWM transmitted to the second electrode of the second transistor T2 to the gate of the second transistor T2. After the second data signal Date_PWM is written to the gate of the second transistor T2, it can coordinately control the conduction time of the second transistor T2, so that the second transistor T2 provides the first transistor T1 with a control signal for controlling the light-emitting duration of the light-emitting element LED.

[0058] Specifically, in this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, which will not be described again.

[0059] In some embodiments, Figure 5 As shown, the pixel circuit further includes a seventh transistor T7, a first electrode of the seventh transistor T7 is connected to the gate of the first transistor T1, a second electrode of the seventh transistor T7 is connected to the second electrode of the first transistor T1, and the gate of the seventh transistor T7 is used to receive the first compensation control signal S4. Figure 1 and Figure 5 As shown, the first compensation control signal S4 is provided by the scan line SL.

[0060] The seventh transistor T7 is used to provide threshold compensation for the first transistor T1 in response to the first compensation control signal S4 received by the gate. Specifically, when the first compensation control signal S4 is at an effective level, the seventh transistor T7 is turned on to compensate the level of the second electrode of the first transistor T1 to the gate, thereby completing the threshold compensation for the first transistor T1. Figure 5 In the illustrated embodiment, the seventh transistor T7 is a P-type transistor and is turned on in response to a low level. The effective level of the first compensation control signal S4 is a low level. When the first compensation control signal S4 is a low level, the seventh transistor T7 is turned on and the level of the second electrode of the first transistor T1 is compensated to the gate, thereby completing the threshold compensation of the first transistor T1.

[0061] Specifically, due to the influence of the uniformity of the manufacturing process, the drift of the threshold voltage of the first transistor T1 will affect the magnitude of the driving current or driving voltage of the light-emitting element, resulting in the non-uniform wavelength of the light-emitting element, thereby affecting the display color and display effect of the panel. The above embodiment of the present application can perform threshold compensation on the first transistor T1 by adding the seventh transistor T7 between the gate and the second electrode of the first transistor T1, thereby achieving a better display effect.

[0062] Specifically, in this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, which will not be described again.

[0063] In some embodiments, Figure 6 As shown, the pixel circuit further includes an eighth transistor T8 and a ninth transistor T9, wherein the first electrode of the eighth transistor T8 is used to receive a power signal VDD, the second electrode of the eighth transistor T8 is connected to the first electrode of the second transistor T2, and the gate of the eighth transistor T8 is used to receive a drive control signal EM. The eighth transistor T8 is used to provide the power signal VDD to the first electrode of the second transistor T2 in response to the drive control signal EM received at the gate. Specifically, when the drive control signal EM is at an effective level, the eighth transistor T8 is turned on, and the power signal VDD can be provided to the first electrode of the second transistor T2 through the eighth transistor T8. Figure 6 In the illustrated embodiment, the eighth transistor T8 is a P-type transistor and is turned on in response to a low level. The effective level of the driving control signal EM is a low level. When the driving control signal EM is a low level, the eighth transistor T8 is turned on, and the power signal VDD can be provided to the first electrode of the second transistor T2 through the eighth transistor T8.

[0064] The first electrode of the ninth transistor T9 is connected to the second electrode of the first transistor T1, the second electrode of the ninth transistor T9 is connected to the light emitting element LED, and the gate of the ninth transistor T9 is used to receive the driving control signal EM. The ninth transistor T9 is used to provide the driving signal provided by the first transistor T1 to the light emitting element LED in response to the driving control signal EM received by the gate. Specifically, when the driving control signal EM is at an effective level, the ninth transistor T9 is turned on, and the driving signal can be provided to the light emitting element LED through the ninth transistor T9. Figure 6 In the embodiment shown, the ninth transistor T9 is a P-type transistor and is turned on in response to a low level. The effective level of the driving control signal EM is a low level. When the driving control signal EM is a low level, the ninth transistor T9 is turned on, and the driving signal can be provided to the light emitting element LED through the ninth transistor T9. Specifically, Figure 1 and Figure 6 As shown, the driving control signal EM is provided by the scanning line SL.

[0065] In order to prevent the driving transistor from generating leakage current and affecting the normal light emission of the light emitting element, the above embodiment sets two control transistors on the driving circuit, so that the driving circuit can be turned off when the light emitting element does not emit light, and turned on again in the light emitting stage. Specifically, the eighth transistor T8 and the ninth transistor T9 are turned on in the light emitting stage, and the driving signal provided by the first transistor T1 can drive the light emitting element LED to emit light through the ninth transistor T9; at the same time, the power signal VDD reaches the first electrode of the second transistor T2 through the turned-on eighth transistor T8. When the second transistor T2 controls the light emission duration of the light emitting element LED, it turns on itself, allowing the power signal to reach the gate of the first transistor T1 through the second transistor T2, so that the first transistor T1 is turned off.

[0066] Specifically, in this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, which will not be described again.

[0067] In some embodiments, Figure 7 As shown, the above-mentioned pixel circuit also includes a first capacitor C1, a first electrode of the first capacitor C1 is connected to the gate of the second transistor T2, and a second electrode is used to receive a light-emitting duration control signal SWEEP. The first capacitor C1 is used to couple the light-emitting duration control signal SWEEP to the gate of the second transistor T2 and thereby control the on and off of the second transistor T2. The second transistor T2 provides a control signal for controlling the light-emitting duration of the light-emitting element LED to the first transistor T1 according to the control of the light-emitting duration control signal SWEEP.

[0068] Specifically, in Figure 7In the embodiment shown, the second transistor T2 and the first transistor T1 are both P-type transistors, and their gates are turned on in response to a low level, and the above-mentioned light-emission duration control signal SWEEP is an electrical signal with a gradually decreasing level. At the initial moment of the light-emission phase of the light-emitting element LED, the second transistor T2 is in an off state, and the level of the light-emission duration control signal SWEEP gradually decreases, so that the second transistor T2 is turned on at a certain moment. Since the first electrode of the second transistor T2 can receive the power signal VDD in the light-emission phase, when it is turned on, the high-level power signal VDD will pull up the potential of the gate of the first transistor T1 through the second electrode of the second transistor T2, so that the first transistor T1 is turned off, and the light-emitting element LED stops emitting light.

[0069] In another embodiment, the second transistor T2 and the first transistor T1 are both N-type transistors, and their gates are turned on in response to a high level, and the above-mentioned light-emitting duration control signal SWEEP is an electrical signal with a gradually rising level. At the initial moment of the light-emitting stage of the light-emitting element LED, the second transistor T2 is in an off state, and the level of the light-emitting duration control signal SWEEP gradually rises so that the second transistor T2 is turned on at a certain moment. Since the first electrode of the second transistor T2 can receive the power signal VSS in the light-emitting stage, when it is turned on, the low-level power signal VSS will pull down the potential of the gate of the first transistor T1 through the second electrode of the second transistor T2, so that the first transistor T1 is turned off, and the light-emitting element LED stops emitting light.

[0070] Specifically, in this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, which will not be described again.

[0071] In some embodiments, Figure 8 As shown, the above-mentioned pixel circuit also includes a second capacitor C2, a first electrode of the second capacitor C2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second capacitor C2 is used to receive the first data signal Date_PAM, and the second capacitor C2 is used to couple the first data signal Date_PAM written by the fourth transistor T4 to the first transistor T1.

[0072] Specifically, in this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, which will not be described again.

[0073] In some embodiments, Fig. 9 As shown, the pixel circuit further includes a third capacitor C3, a first terminal of the third capacitor C3 is connected to the gate of the first transistor T1, and a second terminal of the third capacitor C3 is used to receive a power signal VDD.

[0074] Specifically, the third transistor T3 can reset the potential of the gate of the first transistor T1 to the reset voltage by charging the third capacitor C3 connected to the gate of the first transistor T1.

[0075] Specifically, in this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, which will not be described again.

[0076] During specific implementation, the specific models and capacitances of the first capacitor C1 , the second capacitor C2 , and the third capacitor C3 can be set by those skilled in the art according to actual conditions, and are not limited in detail herein.

[0077] This application also provides a specific embodiment to illustrate the overall working principle of the above pixel circuit. Fig.10 As shown, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2 and a third capacitor C3. Fig.10 The working principle of the transistor and the capacitor in the illustrated embodiment is the same as that in the above-mentioned embodiment, and the signals provided by the data lines and the scanning lines are also the same, which will not be described in detail here.

[0078] In this embodiment, the first transistor T1 and the second transistor T2 can be reset by a third transistor T3, which directly reduces the number of components in the display device, saves the area occupied by the pixel circuit in the display panel, and effectively improves the pixel density and the resolution of the display panel. Fig.10 The pixel circuit shown in the embodiment does not have a transistor cross-charging phenomenon, thereby reducing the driving power consumption of the pixel circuit.

[0079] It should be noted that Fig.10 The illustrated embodiments are merely exemplary and do not limit all transistors in the circuit to be P-type transistors. Those skilled in the art can select different types of transistors according to actual conditions and set the effective level of the gate signal accordingly, which will not be elaborated herein.

[0080] The present application also provides a pixel circuit, wherein the pixel circuit can be the above embodiment and the appended embodiment. Figures 2 to 10 Any one of the pixel circuits. The driving phase of the pixel circuit includes a first reset phase, a first compensation and data writing phase, a second reset phase, a second compensation phase, a second data writing phase and a light emitting phase. Figure 2 The pixel circuit shown in the embodiment, wherein:

[0081] In the first reset stage, the reset control signal S3 is at an effective level, the third transistor T3 is turned on and provides the reset signal REF to the gate of the second transistor T2, and the second transistor T2 is reset and turned on by the reset signal REF received at the gate.

[0082] Specifically, in Figure 2 In the illustrated embodiment, the first transistor T1, the second transistor T2 and the third transistor T3 are all P-type transistors, and their gates are turned on in response to a low level. Naturally, the above-mentioned effective level is a low level, and the reset signal REF is also a low level. Since the third transistor T3 is turned on, the low-level reset signal REF can be provided to the gate of the second transistor T2 through the third transistor T3, thereby lowering the gate potential of the second transistor T2, thereby resetting and turning on the second transistor T2.

[0083] In the second reset stage, the reset control signal S3 is at an effective level, the third transistor T3 is turned on and provides the reset signal REF to the gate of the first transistor T1, and the first transistor T1 is reset and turned on by the reset signal REF received at the gate.

[0084] Specifically, since the reset signal REF is at a low level and the third transistor T3 is turned on, the low level reset signal REF can be provided to the gate of the first transistor T1 through the third transistor T3, thereby lowering the gate potential of the first transistor T1, thereby resetting and turning on the first transistor T1.

[0085] In the second data writing phase, the first data writing control signal S5 is at an effective level, the fourth transistor T4 is turned on and provides the first data signal Date_PAM to the gate of the first transistor T1 .

[0086] In the light-emitting stage, the gate of the first transistor T1 receives a valid level and is turned on, and uses the power signal VDD received by the first electrode and the first data signal Date_PAM received by the gate to provide a driving signal to the light-emitting element LED through the second electrode; and the gate of the second transistor T2 receives a valid level and is turned on, and uses the power signal VDD received by the first electrode to provide a control signal for controlling the light-emitting duration of the light-emitting element LED to the gate of the first transistor T1 through the second electrode.

[0087] Specifically, after the first transistor T1 is turned on, it can provide driving signals of different amplitudes to the light-emitting element LED according to the first data signal Date_PAM, so as to ensure that the light-emitting element LED emits light of a fixed wavelength, thereby realizing the PAM driving mode. The second transistor T2 can control the on and off of the first transistor T1 through the light-emitting duration control signal applied to the gate of the first transistor T1, thereby controlling the time when the first transistor T1 provides the driving signal to the light-emitting element LED, thereby realizing the PWM driving mode.

[0088] In the embodiment of the present application, the first transistor T1 and the second transistor T2 can be reset by a third transistor T3, thereby reducing the number of components in the display device, saving the area occupied by the pixel circuit in the display panel, and effectively improving the pixel density and the resolution of the display panel.

[0089] exist Figure 4 In the illustrated embodiment, in the first reset stage, the second compensation control signal S1 and the reset control signal S3 are at the effective level, the third transistor T3 is turned on and provides the reset signal REF to the second electrode of the fifth transistor T5, the fifth transistor T5 is turned on and provides the reset signal REF to the gate of the second transistor T2, and the second transistor T2 is reset and turned on using the reset signal REF received at the gate.

[0090] In the first compensation and data writing stage, the second compensation control signal S1 and the second data writing control signal S2 are at the effective level, the fifth transistor T5 is turned on and provides threshold compensation for the second transistor T2, and at the same time, the sixth transistor T6 is turned on, and the second data signal Date_PWM is written into the gate of the second transistor T2 through the sixth transistor T6, the second transistor T2, and the fifth transistor T5 that are turned on in sequence. Since the second data signal Date_PWM is written into the first electrode of the second transistor T2, and the threshold compensation is performed on the gate of the second transistor T2, data writing and threshold compensation can be performed on the second transistor T2 at the same time.

[0091] Specifically, in this embodiment, the principles of other driving stages are the same as those in the above embodiment and will not be described in detail here.

[0092] exist Figure 5 In the illustrated embodiment, in the above-mentioned second compensation stage, the first compensation control signal S4 is at an effective level, the seventh transistor T7 is turned on, and the level of the second electrode of the first transistor T1 is compensated to the gate, thereby completing the threshold compensation of the first transistor T1. Specifically, since the first data signal Date_PAM is written into the gate of the first transistor T1, the threshold compensation of the first transistor T1 cannot be performed while the first data signal Date_PAM is written, otherwise the threshold compensation of the gate of the first transistor T1 will be interfered by the first data signal Date_PAM.

[0093] Specifically, in this embodiment, the principles of other driving stages are the same as those in the above embodiment and will not be described in detail here.

[0094] exist Figure 6In the illustrated embodiment, in the above-mentioned light-emitting stage, the driving control signal EM is at an effective level, the eighth transistor T8 and the ninth transistor T9 are turned on, and the driving signal provided by the first transistor T1 can drive the light-emitting element LED to emit light through the ninth transistor T9; at the same time, the power signal VDD reaches the first electrode of the second transistor T2 through the turned-on eighth transistor T8, and when the second transistor T2 controls the light-emitting duration of the light-emitting element LED, it turns on itself, allowing the power signal to reach the gate of the first transistor T1 through the second transistor T2, so that the first transistor T1 is turned off.

[0095] exist Figure 7 In the illustrated embodiment, in the above-mentioned light-emitting stage, the light-emitting duration control signal transitions from an invalid level to a valid level, and the valid level of the light-emitting duration control signal can turn on the second transistor T2. Since the first electrode of the second transistor T2 can receive the power signal VDD in the light-emitting stage, when it is turned on, the invalid level power signal VDD will pass through the second transistor T2 to reach the gate of the first transistor T1, turning off the first transistor T1, and the light-emitting element LED stops emitting light.

[0096] Specifically, in this embodiment, the principles of other driving stages are the same as those in the above embodiment and will not be described in detail here.

[0097] This application also provides a complete example to illustrate Fig.10 The driving method of each stage of the pixel circuit shown in the embodiment. Specifically, Fig.10 The timing diagram of each signal in the circuit corresponding to the embodiment is as follows Fig.11 As shown, Fig.10 The driving phase of the pixel circuit shown in the embodiment includes a first reset phase (1), a first compensation and data writing phase (2), a second reset phase (3), a second compensation phase (4), a second data writing phase (5), and a light emitting phase (6). Fig.10 In the pixel circuit shown in the embodiment, each transistor is a P-type transistor, and the gate is turned on in response to a low level, so the effective level is a low level.

[0098] In the first reset phase, the corresponding Fig.11 In the (1) stage, the reset control signal S3 and the second compensation control signal S1 become low level, and other signals remain high level, such as Fig.12 As shown ( Fig.12In the figure, the transistor marked with "×" indicates the off state, which does not mean that the transistor does not exist, and the unmarked transistor indicates the on state. The same is true for the other embodiment drawings, which will not be repeated). Since the reset control signal S3 and the second compensation and reset control signal S1 are at a low level, the fifth transistor T5 and the third transistor T3 are turned on accordingly, and the other transistors are turned off. Since the fifth transistor T5 and the third transistor T3 are turned on, the other transistors are all in the off state. The reset signal REF will first pass through the third transistor T3, and then pass through the fifth transistor T5 to charge the first capacitor C1, so that the node of the gate of the second transistor T2 is reset to the REF potential. At the same time, due to the Fig.10 In the illustrated embodiment, the REF potential is at a low level, so the second transistor T2 is turned on in response to the REF potential of the gate being at a low level.

[0099] In the first compensation and data writing phase, corresponding to Fig.11 In the (2) stage, the second data writing control signal S2 and the second compensation control signal S1 are at a low level, and other signals remain at a high level, such as Fig.13 As shown, since the second data writing control signal S2 and the second compensation control signal S1 are at low level, the fifth transistor T5 and the sixth transistor T6 are turned on accordingly, and the other transistors are turned off. Since the second transistor T2 is in the on state at this time, the second data signal Date_PWM can reach the second electrode of the second transistor T2, and the fifth transistor T5 writes the second data signal Date_PWM into the node of the gate of the second transistor T2 while performing threshold compensation on the second transistor T2. At this time, the gate potential VA of the second transistor T2 is V(Date_PWM)+Vth, and the second transistor T2 is turned off.

[0100] In the second reset phase, the corresponding Fig.11 In the (3) stage, the reset control signal S3 becomes low level, and other signals remain high level, such as Fig.14 As shown, since the reset control signal S3 is at a low level, the third transistor T3 is turned on accordingly, and the other transistors are turned off. Since the third transistor T3 is turned on, the reset signal REF will charge the third capacitor C3 through the third transistor T3, so that the node of the gate of the first transistor T1 is reset to the REF potential, and the first transistor T1 is turned on. It should be noted that, although the third transistor T3 is turned on in the first reset stage, after the above-mentioned first compensation and data writing stage, the second data signal Date_PWM reaches the gate node of the first transistor T1 through the turned-on second transistor T2, so that the potential of the gate of the first transistor T1 is no longer the REF potential, so it is necessary to reset the gate of the first transistor T1 again in the second reset stage.

[0101] In the second compensation stage, corresponding to Fig.11 In the (4) stage, the first compensation control signal S4 becomes low level, and other signals remain high level, such as Fig.15 As shown, since the first compensation control signal S4 is at a low level, the seventh transistor T7 is turned on, and the other transistors are turned off. Since the seventh transistor T7 is turned on with the first transistor T1, the power signal VDD can pass through the first transistor T1 to reach the second electrode of the first transistor T1, and the seventh transistor T7 can provide the signal of the second electrode of the first transistor T1 to the gate, thereby realizing the threshold compensation of the first transistor T1. At this time, the gate potential VB of the first transistor T1 is VDD+Vth.

[0102] In the second data writing phase, corresponding to Fig.11 In the (5) stage, the first data write control signal S5 becomes low level, and other signals remain high level, such as Fig.16 As shown, since the first data writing control signal S5 is at a low level, the fourth transistor T4 is turned on. The first data signal Date_PAM can be coupled to the gate of the first transistor T1 through the fourth transistor T4 and the second capacitor C2. At this time, the gate potential of the first transistor T1 VB=V(Date_PAM)+VDD+Vth.

[0103] In the light-emitting stage, Fig.11 In the (6) stage, the driving control signal EM changes to a low level, the light-emitting duration control signal SWEEP level gradually decreases from a high level, and other signals remain at a high level. Fig.17 As shown, since the driving control signal EM is at a low level, the eighth transistor T8 and the ninth transistor T9 are turned on, and since the first transistor T1 remains turned on in the previous stage, the power signal VDD drives the light-emitting element LED to start emitting light through the first transistor T1 and the ninth transistor T9. As the level of the light-emitting duration control signal SWEEP becomes lower and lower, coupled with the coupling effect of C1, the potential VA of the gate of the second transistor T2 gradually decreases from V(Date_PWM)+Vth until the second transistor T2 is in the on state, as shown in FIG. Fig.18 After the second transistor T2 is turned on, and the eighth transistor T8 is also turned on, the high-level VDD signal can charge the third capacitor C3 through the eighth transistor T8 and the second transistor T2, and at the same time, the node potential at the gate of the first transistor T1 gradually increases until the first transistor T1 is turned off. Fig.18 As shown, at this time, the light-emitting element LED stops emitting light.

[0104] In some embodiments, Fig.19As shown, in the second data writing stage, the starting time of the effective level of the first data signal Date_PAM lags behind the starting time of the effective level of the first data writing control signal S5 by a first preset time; in the light emitting stage, the ending time of the effective level of the first data signal Date_PAM lags behind the ending time of the effective level of the first data writing control signal S5 by a second preset time. Both the first preset time and the second preset time are shorter than the duration of the effective level of the first data writing control signal S5. On this basis, the first preset time and the second preset time make the effective level of the first data signal Date_PAM slightly lag behind the effective level of the first data writing control signal S5, and the specific value is not limited.

[0105] In specific implementation, if the first data signal Date_PAM stops being written when the fourth transistor T4 is turned off, the second capacitor C2 will couple part of the first data signal Date_PAM, so that the first data signal Date_PAM cannot be completely written into the first transistor T1. Fig.19 As shown in the timing diagram, the overall timing of the first data signal Date_PAM needs to slightly lag behind the first data write control signal S5, that is, the falling edge of the high level of the first data signal Date_PAM needs to slightly lag behind the falling edge of the high level of the first data write control signal S5, and at the same time, the rising edge of the low level of the first data signal Date_PAM needs to slightly lag behind the rising edge of the low level of the first data write control signal S5.

[0106] In some embodiments, Fig. 20 As shown, in the first reset stage, the starting time of the invalid level of the light-emitting duration control signal SWEEP lags behind the starting time of the valid level of the reset control signal S3 by a third preset time. The third preset time is less than the duration of the valid level of the reset signal S3 in the first reset stage. On this basis, the third preset time makes the starting time of the invalid level of the light-emitting duration control signal SWEEP slightly lag behind the valid level of the reset control signal S3 in the first reset stage, and the specific value is not limited.

[0107] In a specific implementation, in order to ensure that the first transistor T1 is always turned off when the light emitting element LED needs to stop emitting light, the rising edge of the light emitting duration control signal SWEEP after the light emitting stage (6) ends may be slightly delayed from the time point when the light emitting stage (6) ends, such as Fig. 20As shown, the rising edge of the low level of the light-emission duration control signal SWEEP in the first reset stage (1) of the next frame slightly lags behind the falling edge of the high level of the reset control signal S3. At the same time, since the circuit is still in the first reset stage (1) after the light-emission duration control signal SWEEP is restored to a high level, the influence of the voltage jump of the light-emission duration control signal SWEEP on the gate of the second transistor T2 can be repaired by the reset signal REF, and will not affect the normal operation of the circuit.

[0108] In other embodiments, Fig.21 In the pixel circuit shown in the figure, each transistor is an N-type transistor, and the gate is turned on in response to a high level, that is, the effective level is a high level, and Fig.21 The timing diagram of each signal in the circuit corresponding to the embodiment is as follows Fig. 22 shown.

[0109] In the first reset phase, the corresponding Fig. 22 In the (1) stage, the reset control signal S3 and the second compensation control signal S1 become high level, and other signals remain low level. Since the reset control signal S3, the second compensation and reset control signal S1 are high level, the fifth transistor T5 and the third transistor T3 are turned on accordingly, and other transistors are turned off. Since the fifth transistor T5 and the third transistor T3 are turned on, and other transistors are all turned off, the reset signal REF will first pass through the third transistor T3, and then pass through the fifth transistor T5 to charge the first capacitor C1, so that the node of the gate of the second transistor T2 is reset to the REF potential. At the same time, due to the Fig.10 In the illustrated embodiment, the REF potential is at a high level, so the second transistor T2 is turned on in response to the REF potential of the gate being at a high level.

[0110] In the first compensation and data writing phase, corresponding to Fig. 22 In the (2) stage, the second data writing control signal S2 and the second compensation control signal S1 are at a high level, and other signals remain at a low level. Since the second data writing control signal S2 and the second compensation control signal S1 are at a high level, the fifth transistor T5 and the sixth transistor T6 are turned on accordingly, and other transistors are turned off. Since the second transistor T2 is in the on state at this time, the second data signal Date_PWM can reach the second electrode of the second transistor T2, and the fifth transistor T5 writes the second data signal Date_PWM into the node of the gate of the second transistor T2 while performing threshold compensation on the second transistor T2. At this time, the gate potential of the second transistor T2 VA=V(Date_PWM)+Vth, and the second transistor T2 is turned off.

[0111] In the second reset phase, the corresponding Fig. 22In the (3) stage, the reset control signal S3 becomes high level, and other signals remain low level. Since the reset control signal S3 is high level, the third transistor T3 is turned on accordingly, and other transistors are turned off. Since the third transistor T3 is turned on, the reset signal REF will charge the third capacitor C3 through the third transistor T3, so that the node of the gate of the first transistor T1 is reset to the REF potential, and the first transistor T1 is turned on. It should be noted that although the third transistor T3 is turned on in the first reset stage, after the above-mentioned first compensation and data writing stage, the second data signal Date_PWM reaches the gate node of the first transistor T1 through the turned-on second transistor T2, so that the potential of the gate of the first transistor T1 is no longer the REF potential, so it is necessary to reset the gate of the first transistor T1 again in the second reset stage.

[0112] In the second compensation stage, corresponding to Fig. 22 In the (4) stage, the first compensation control signal S4 becomes high level, and other signals remain low level. Since the first compensation control signal S4 is high level, the seventh transistor T7 is turned on, and other transistors are turned off. Since the seventh transistor T7 is turned on with the first transistor T1, the power signal VSS can pass through the first transistor T1 to reach the second electrode of the first transistor T1, and the seventh transistor T7 can provide the signal of the second electrode of the first transistor T1 to the gate, thereby realizing the threshold compensation of the first transistor T1. At this time, the gate potential VB of the first transistor T1 = VSS + Vth.

[0113] In the second data writing phase, corresponding to Fig. 22 In the (5) stage, the first data write control signal S5 becomes high level, and other signals remain low level. Since the first data write control signal S5 is high level, the fourth transistor T4 is turned on. The first data signal Date_PAM can be coupled to the gate of the first transistor T1 through the fourth transistor T4 and the second capacitor C2. At this time, the gate potential VB of the first transistor T1 is V(Date_PAM)+VSS+Vth.

[0114] In the light-emitting stage, Fig. 22In the (6) stage, the driving control signal EM becomes high level, the level of the light-emitting duration control signal SWEEP gradually increases from low level, and other signals remain low level. Since the driving control signal EM is high level, the eighth transistor T8 and the ninth transistor T9 are turned on, and since the first transistor T1 remains turned on in the previous stage, the power supply signal VSS drives the light-emitting element LED to start emitting light through the first transistor T1 and the ninth transistor T9. As the level of the light-emitting duration control signal SWEEP becomes higher and higher, coupled with the coupling effect of C1, the potential VA of the gate of the second transistor T2 gradually increases from V(Date_PWM)+Vth until the second transistor T2 is in the on state. After the second transistor T2 is turned on, coupled with the eighth transistor T8 also being in the on state, the low-level VSS signal can charge the third capacitor C3 via the eighth transistor T8 and the second transistor T2, and at the same time gradually reduce the node potential at the gate of the first transistor T1 until the first transistor T1 is turned off, at which time the light-emitting element LED stops emitting light.

[0115] In specific implementation, if the first data signal Date_PAM stops being written when the fourth transistor T4 is turned off, the second capacitor C2 will couple part of the first data signal Date_PAM, so that the first data signal Date_PAM cannot be completely written into the first transistor T1. Fig.23 As shown in the timing diagram, the overall timing of the first data signal Date_PAM needs to slightly lag behind the first data write control signal S5, that is, the rising edge of the low level of the first data signal Date_PAM needs to slightly lag behind the rising edge of the low level of the first data write control signal S5, and at the same time, the falling edge of the high level of the first data signal Date_PAM needs to slightly lag behind the falling edge of the high level of the first data write control signal S5.

[0116] In a specific implementation, in order to ensure that the first transistor T1 is always turned off when the light emitting element LED needs to stop emitting light, the falling edge of the light emitting duration control signal SWEEP after the light emitting stage (6) ends may be slightly delayed from the time point when the light emitting stage (6) ends, such as Fig.24 As shown, the falling edge of the high level of the light-emission duration control signal SWEEP in the first reset stage (1) of the next frame slightly lags behind the rising edge of the low level of the reset control signal S3. At the same time, since the circuit is still in the first reset stage (1) after the light-emission duration control signal SWEEP is restored to a low level, the influence of the voltage jump of the light-emission duration control signal SWEEP on the gate of the second transistor T2 can be repaired by the reset signal REF, and will not affect the normal operation of the circuit.

[0117] The above embodiments of the present application respectively provide embodiments in which all the pixel circuits are N-type transistors and all the pixel circuits are P-type transistors. For embodiments in which some of the pixel circuits are N-type transistors and some are P-type transistors, those skilled in the art can, based on the description of the above embodiments and Figures 10 to 24 The corresponding driving mode and driving timing are obtained, which are all within the protection scope of this application.

[0118] Based on the same inventive concept, an embodiment of the present application further provides a Figure 1 The display device shown includes a data driving circuit 500, a scanning driving circuit 700, data lines DL, scanning lines SL, and a pixel array unit 100. The pixel array unit 100 includes a corresponding pixel circuit in any of the aforementioned embodiments.

[0119] The specific structure of the above display device can be referred to the above embodiment and will not be described in detail.

[0120] In some embodiments, the above-mentioned display device can be a separate display panel, or it can be a terminal device with a display function, such as a television, a smart phone, a computer, a learning machine, etc.

[0121] Specifically, the display device may include a processor and a memory storing computer program instructions, and the computer program instructions are used to execute the driving method of the corresponding pixel circuit at each stage in any of the aforementioned embodiments. The processor reads and executes the computer program instructions stored in the memory to execute the steps of the driving method of the pixel circuit at each stage provided in the embodiment of the present disclosure.

[0122] The display device of the above embodiment includes a pixel circuit that implements the corresponding pixel circuit in any of the above embodiments, and has the beneficial effects of the corresponding embodiment, which will not be described in detail here.

[0123] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a..." do not exclude the existence of other identical elements in the process, method, article or device including the above elements.

[0124] Based on the exemplary embodiments described in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the claims attached to this application. In addition, although the disclosure in this application is introduced according to one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method separately. It should be noted that the brief description of the terms in this application is only for the convenience of understanding the implementation methods described below, and is not intended to limit the implementation methods of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0125] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above discussion in some embodiments is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. According to the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A pixel circuit, comprising a first transistor, a second transistor, a third transistor, a fourth transistor and a light-emitting element, wherein: The first electrode of the first transistor and the first electrode of the second transistor are used to receive a power supply signal, the second electrode of the first transistor is connected to the light emitting element, and the second electrode of the second transistor is connected to the gate of the first transistor; The second electrode of the third transistor is connected to the gate of the first transistor and the gate of the second transistor, the first electrode of the third transistor is used to receive a reset signal, and the gate of the third transistor is used to receive a reset control signal; The first electrode of the fourth transistor is used to receive a first data signal, the second electrode of the fourth transistor is connected to the gate of the first transistor, and the gate of the fourth transistor is used to receive a first data writing control signal; The first transistor is used to provide a driving signal for the light-emitting element, the second transistor is used to provide a control signal to the first transistor to control the light-emitting duration of the light-emitting element, the third transistor is used to respond to the reset control signal received by the gate to provide the reset signal to the gate of the first transistor and the gate of the second transistor; the fourth transistor is used to respond to the first data write control signal received by the gate, and write the first data signal into the gate of the first transistor.

2. The pixel circuit according to claim 1, further comprising a fifth transistor, a first electrode of the fifth transistor being connected to the gate of the second transistor, a second electrode of the fifth transistor being connected to the second electrode of the second transistor and the second electrode of the third transistor, and a gate of the fifth transistor being used to receive a second compensation control signal; The fifth transistor is used to provide the reset signal provided by the third transistor to the gate of the second transistor in response to the second compensation control signal received through the gate, and the fifth transistor is also used to provide threshold compensation for the second transistor in response to the second compensation control signal received through the gate.

3. The pixel circuit according to claim 2, further comprising a sixth transistor, a first electrode of the sixth transistor being connected to the first electrode of the second transistor, a second electrode of the sixth transistor being used to receive a second data signal, and a gate of the sixth transistor being used to receive a second data write control signal; The sixth transistor is used to write the second data signal into the first electrode of the second transistor in response to the second data writing control signal received by the gate, and the second transistor is also used to transfer the second data signal received by the first electrode to the second electrode after being turned on; The fifth transistor is further configured to provide the second data signal to the gate of the second transistor in response to the second compensation control signal received through the gate, and provide threshold compensation for the second transistor.

4. The pixel circuit according to claim 1, further comprising a seventh transistor, a first electrode of the seventh transistor being connected to a gate of the first transistor, a second electrode of the seventh transistor being connected to a second electrode of the first transistor, and a gate of the seventh transistor being used to receive a first compensation control signal; The seventh transistor is configured to provide threshold compensation for the first transistor in response to the first compensation control signal received by a gate.

5. The pixel circuit according to claim 1 further includes a first capacitor, a first electrode of the first capacitor is connected to the gate of the second transistor, a second electrode of the first capacitor is used to receive a light-emitting duration control signal, and the first capacitor is used to couple the light-emitting duration control signal to the gate of the second transistor.

6. A display device, comprising a data driving circuit, a scanning driving circuit, a data line, a scanning line and a pixel circuit, wherein: The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a light emitting element; The second electrode of the first transistor is connected to the light emitting element, and the second electrode of the second transistor is connected to the gate of the first transistor; The second electrode of the third transistor is connected to the gate of the first transistor and the gate of the second transistor, and the gate of the third transistor is used to receive a reset control signal; The second electrode of the fourth transistor is connected to the gate of the first transistor, and the gate of the fourth transistor is used to receive a first data writing control signal; The driving phase of the pixel circuit includes a first reset phase, a first compensation and data writing phase, a second reset phase, a second compensation phase, a second data writing phase and a light emitting phase, wherein: The reset control signal is at a valid level in the first reset stage and the second reset stage; The first data writing control signal is at an effective level in the second data writing phase.

7. The display device according to claim 6, further comprising a fifth transistor, a first electrode of the fifth transistor being connected to a gate of the second transistor, a second electrode of the fifth transistor being connected to a second electrode of the second transistor and a second electrode of the third transistor, and a gate of the fifth transistor being used to receive a second compensation control signal, wherein: The second compensation control signal and the reset control signal have the same level state in the first reset phase, the second compensation phase, the second data writing phase and the light emitting phase.

8. The display device according to claim 7, further comprising a sixth transistor, a first electrode of the sixth transistor being connected to the first electrode of the second transistor, and a gate of the sixth transistor being used to receive a second data writing control signal, wherein: The second data writing control signal and the second compensation control signal have different level states in the first reset stage; The level states of the second data writing control signal and the reset control signal are different in the first reset phase, the first compensation and data writing phase, and the second reset phase.

9. The display device according to claim 6, wherein: In the second data writing phase, the starting time of the effective level of the first data signal lags behind the starting time of the effective level of the first data writing control signal by a first preset time; In the light emitting stage, the end time of the effective level of the first data signal lags behind the end time of the effective level of the first data writing control signal by a second preset time.

10. The display device according to claim 6, further comprising a first capacitor, a first electrode of the first capacitor being connected to the gate of the second transistor, a second electrode of the first capacitor being used to receive a light emission duration control signal, and the first capacitor being used to couple the light emission duration control signal to the gate of the second transistor; The light-emitting duration control signal is at an invalid level in the first reset phase, and the light-emitting duration control signal transitions from the invalid level to the valid level in the light-emitting phase, wherein: In the first resetting stage, a starting time of the inactive level of the light-emitting duration control signal lags behind a starting time of the active level of the reset control signal by a third preset time.

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