Multilayer ceramic capacitor and method of manufacturing same

Abstract

A multilayer ceramic capacitor and a method of manufacturing the same are provided. The multilayer ceramic capacitor includes a capacitor body including a dielectric layer and an inner electrode layer, and an outer electrode disposed outside the capacitor body. The dielectric layer includes a barium titanate-based main component containing barium (Ba) and titanium (Ti) and gallium (Ga), and a peak intensity ratio of Ba / Ga (IBa / IGa) obtained by TEM-EDS analysis from an interface between the dielectric layer and the inner electrode layer to a region of a depth surface of 10 nm to 500 nm within the dielectric layer is 1.0 to 5.0.

Description

Technical Field

[0001] The present disclosure relates to a multilayer ceramic capacitor and a method of manufacturing the same. Background Art

[0002] As electronic components using ceramic materials, there are capacitors, inductors, piezoelectric elements, varistors, thermistors, etc. Among ceramic electronic components, multilayer ceramic capacitors (MLCCs) are used in various electronic devices due to advantages such as small size, high capacitance, easy mounting features, etc.

[0003] For example, a multilayer ceramic capacitor can be a chip capacitor mounted on boards of various electronic products (such as, for example, image display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), computers, personal portable terminals, smart phones, etc.) for charging or discharging therefrom.

[0004] Recently, with the trend toward miniaturization and thin-filming of multilayer ceramic capacitors, short-circuit defects often occur due to the reduction in thickness of dielectric layers and internal electrode layers. Summary of the invention

[0005] The embodiment provides a multilayer ceramic capacitor having improved internal electrode connectivity by alleviating sintering mismatch between dielectric layers and internal electrode layers.

[0006] Another embodiment provides a method of manufacturing a multilayer ceramic capacitor.

[0007] The embodiment provides a multilayer ceramic capacitor, comprising: a capacitor body including a dielectric layer and an inner electrode layer; and an outer electrode disposed outside the capacitor body. The dielectric layer includes a barium titanate-based main component containing barium (Ba) and titanium (Ti) and gallium (Ga). The peak intensity ratio (I) of Ba / Ga obtained by TEM-EDS analysis of a region from an interface between the dielectric layer and the inner electrode layer to a depth surface of 10 nm to 500 nm in the dielectric layer. Ba / I Ga ) is 1.0 to 5.0.

[0008] The peak intensity ratio of Ti / Ga obtained by TEM-EDS analysis of the region (I Ti / I Ga ) can be from 1.0 to 5.0.

[0009] The dielectric layer may further include a subcomponent, and the subcomponent may include aluminum (Al), silicon (Si), magnesium (Mg), vanadium (V), manganese (Mn), or a combination thereof.

[0010] The subcomponent may include aluminum (Al), and a peak intensity ratio (I Al / I Ga ) is 1.0 to 5.0.

[0011] The subcomponent may include silicon (Si), and a peak intensity ratio (I Si / I Ga ) is 1.0 to 5.0.

[0012] The subcomponent may include magnesium (Mg), and a peak intensity ratio (I Mg / I Ga ) is 0.4 to 2.0.

[0013] Gallium (Ga) may exist as a second phase combined with the subcomponents.

[0014] Gallium (Ga) may be included in an amount of 0.01 parts by mol to 10 parts by mol based on 100 parts by mol of the barium titanate-based main component.

[0015] The dielectric layer may include a plurality of grains and grain boundaries between adjacent grains among the plurality of grains, and gallium (Ga) may exist at the grain boundaries.

[0016] A molar ratio of gallium (Ga) present in the grain boundary to gallium (Ga) present in the crystal grain may be 5:1 to 50:1.

[0017] Gallium (Ga) may be formed from a gallium (Ga) complex.

[0018] The capacitor body may be formed by sintering at a temperature of 1000°C to 1200°C.

[0019] The capacitor body has an effective portion in which the dielectric layers and the inner electrode layers are alternately arranged, and in which the inner electrode connectivity defined by the following Formula 1 may be 80% to 100%,

[0020] (Formula 1)

[0021] Internal electrode connectivity (%)=(total length of connected portions excluding disconnected portions in the plurality of internal electrode layers / total length of the plurality of internal electrode layers)×100.

[0022] The capacitor body also has a side edge portion, which is arranged on two side end portions of the effective portion opposite to each other in the width direction, and in the area near the side edge portion, the internal electrode connectivity defined by Formula 1 can be 80% to 100%, and the area near the side edge portion is defined as an area extending from the boundary between the effective portion and the side edge portion into the effective portion to a depth surface corresponding to 5% to 20% of the total length of the effective portion in the width direction.

[0023] Another embodiment provides a method for manufacturing a multilayer ceramic capacitor, comprising: preparing a dielectric slurry by mixing a barium titanate-based main component powder and a gallium (Ga) complex; preparing a dielectric green sheet using the dielectric slurry, and forming a conductive paste layer on the surface of the dielectric green sheet; preparing a dielectric green sheet stacking structure by stacking the dielectric green sheets on which the conductive paste layer is formed; preparing a capacitor body including a dielectric layer and an inner electrode layer by sintering the dielectric green sheet stacking structure; and forming an outer electrode on the outer surface of the capacitor body. The dielectric layer includes a barium titanate-based main component containing barium (Ba) and titanium (Ti) and gallium (Ga). The peak intensity ratio (I) of Ba / Ga obtained by TEM-EDS analysis of a region from an interface between the dielectric layer and the inner electrode layer to a depth surface of 10 nm to 500 nm in the dielectric layer. Ba / I Ga ) is 1.0 to 5.0.

[0024] The gallium (Ga) complex may include gallium carboxylate in an ionic form.

[0025] The gallium (Ga) complex may be mixed in an amount of 0.01 to 10 parts by mol based on 100 parts by mol of the barium titanate-based main component powder.

[0026] By further mixing aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), magnesium oxide (MgO), vanadium oxide (V 2 O 5 ), manganese oxide (MnO 2 ) or a combination thereof to prepare a dielectric slurry.

[0027] Aluminum oxide (Al2O3) may be mixed in an amount of 0.01 to 5 parts by mole based on 100 parts by mole of the barium titanate-based main component powder. 2 O 3 ), silicon dioxide (SiO 2), magnesium oxide (MgO) may be mixed in an amount of 0.01 to 5 mol parts, and vanadium oxide (V 2 O 5 ), and manganese oxide (MnO 2 ).

[0028] Sintering may be performed at a temperature of 1000°C to 1200°C.

[0029] The multilayer ceramic capacitor according to the embodiment can alleviate sintering mismatch between dielectric layers and internal electrode layers, thereby minimizing electrode breakage and improving internal electrode connectivity, thus having high reliability without short circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment.

[0031] Figure 2 is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line I-I'.

[0032] Figure 3 is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line II-II'.

[0033] Figure 4 yes Figure 3 An enlarged view of a portion of area B.

[0034] Figure 5 is a TEM-EDS analysis image of the multilayer ceramic capacitor according to Example 1.

[0035] Figure 6 is a TEM-EDS analysis image of the multilayer ceramic capacitor according to Comparative Example 1.

[0036] Figure 7 Results of STEM-EDS mapping analysis of an effective portion of the multilayer ceramic capacitor according to Example 3 are shown.

[0037] Figure 8 are SEM images of effective portions of the multilayer ceramic capacitors according to Examples 1 and 2 and Comparative Example 2.

[0038] Fig. 9 1 and 2 are SEM images of regions near side edge portions of the multilayer ceramic capacitors according to Examples 1 and 2 and Comparative Example 2.

[0039] Fig.10is a graph showing changes in density of dielectric layers according to Examples 1 to 3 and Comparative Example 2 depending on sintering temperature. DETAILED DESCRIPTION

[0040] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. The accompanying drawings and descriptions are considered to be illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals represent the same elements. In the accompanying drawings, some constituent elements are enlarged, omitted or schematically shown, and the size of each constituent element does not fully reflect the actual size.

[0041] The drawings are intended only to facilitate understanding of the exemplary embodiments disclosed in this specification, and it should be understood that the technical ideas disclosed herein are not limited to the drawings, and include all modifications, equivalents, or replacements within the scope of the ideas and technologies of the present disclosure.

[0042] Although the terms "first", "second", etc. are used to explain various constituent elements, the constituent elements are not limited to these terms. These terms are only used to distinguish one constituent element from another constituent element.

[0043] In addition, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, when an element is referred to as being "on" or "above" a reference element, it can be located above or below the reference element, and does not necessarily mean being "on" or "above" relative to the direction of gravity.

[0044] Throughout the specification, the term "includes" or "has" is intended to specify the presence of the features, numbers, steps, operations, constituent elements, components or combinations thereof, but does not exclude the presence or addition of one or more other features, numbers, steps, operations, constituent elements, components and / or combinations thereof. Therefore, unless explicitly described to the contrary, the word "includes" and variations such as "comprises" (including, containing, having) will be understood to imply the inclusion of the elements but not the exclusion of any other elements.

[0045] Furthermore, throughout the specification, the phrase “in a plan view” or “on a plane” means observing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0046] Throughout the specification, the term "connected" not only means that two or more constituent components are directly connected but may also mean that two or more constituent components are indirectly connected through another constituent component, that two or more components are electrically or physically connected, or that two or more constituent components are represented by different names but are united by position or function.

[0047] In the following, reference will be made to Figures 1 to 4 A multilayer ceramic capacitor according to an example is described.

[0048] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment, Figure 2 is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line I-I'. Figure 3 is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line II-II', and Figure 4 yes Figure 3 An enlarged view of a portion of area B.

[0049] Figures 1 to 3 The L-axis direction, W-axis direction, and T-axis direction shown in represent the length direction, width direction, and thickness direction of the capacitor body 110, respectively. Here, the thickness direction (T-axis direction) may be a direction perpendicular to the wide surface (main surface) of the sheet component, for example, the same concept as the stacking direction of the stacked dielectric layer 111 may be used. The length direction (L-axis direction) may be a direction extending parallel to the wide surface (main surface) of the sheet component, and may be substantially perpendicular to the thickness direction (T-axis direction). For example, the length direction (L-axis direction) may be a direction in which the first external electrode 131 and the second external electrode 132 are arranged on both sides of the direction. The width direction (W-axis direction) may be a direction extending parallel to the wide surface (main surface) of the sheet component, and may be substantially perpendicular to the thickness direction (T-axis direction) and the length direction (L-axis direction). The length of the sheet component in the length direction (L-axis direction) may be longer than the length in the width direction (W-axis direction).

[0050] Reference Figures 1 to 4 , the multilayer ceramic capacitor 100 according to the embodiment includes a capacitor body 110 and external electrodes 131 and 132 disposed outside the capacitor body 110. The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 disposed at opposite ends of the capacitor body 110 in the length direction (L-axis direction).

[0051] For example, the capacitor body 110 may have a substantially hexahedral shape.

[0052] For the convenience of describing the embodiments, the two surfaces opposite to each other in the thickness direction (T-axis direction) of the capacitor body 110 are referred to as the first surface and the second surface, the two surfaces connected to the first surface and the second surface and opposite to each other in the length direction (L-axis direction) are referred to as the third surface and the fourth surface, and the two surfaces connected to the first surface and the second surface and the third surface and the fourth surface and opposite to each other in the width direction (W-axis direction) are referred to as the fifth surface and the sixth surface.

[0053] As an example, the first surface as the lower surface may be a surface facing the installation direction. In addition, the first to sixth surfaces may be flat, but the embodiment is not limited thereto. For example, the first to sixth surfaces may be curved surfaces having a convex central portion, and the edges as the boundaries of each surface may be rounded.

[0054] The shape and size of the capacitor body 110 and the stacking number of the dielectric layers 111 are not limited to the shape and size and the stacking number shown in the drawings of the embodiment.

[0055] The capacitor body 110 includes a plurality of dielectric layers 111 and internal electrode layers 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111, first internal electrode layers 121 and second internal electrode layers 122 alternately arranged in a thickness direction (T-axis direction), and a plurality of dielectric layers 111 are interposed between the first internal electrode layers 121 and the second internal electrode layers 122.

[0056] At this time, the boundaries between the adjacent dielectric layers 111 of the capacitor body 110 may be integrated to such an extent that they are difficult to identify without using a scanning electron microscope (SEM).

[0057] The capacitor body 110 may have an effective portion A. The effective portion A is a region where the dielectric layer 111 and the internal electrode layers 121 and 122 are alternately arranged, and is a portion that contributes to forming the capacitance of the multilayer ceramic capacitor 100. Specifically, the effective portion A may be a region where the first internal electrode layer 121 or the second internal electrode layer 122 stacked in the thickness direction (T-axis direction) overlaps.

[0058] In addition, the capacitor body 110 may further include a cover portion and a side edge portion 140 .

[0059] The covering portion is a thickness direction edge portion, and may be located on both surfaces of the effective portion A in the thickness direction (T-axis direction), respectively.

[0060] The side margin portion 140 may be regarded as a side covering portion, and may be located on both side ends of the effective portion A that are opposite to each other in the width direction (W-axis direction). When a conductive paste layer for an internal electrode layer is applied on the surface of a dielectric green sheet, the side margin portion 140 may be formed by applying the conductive paste layer only on a portion of the surface of the dielectric green sheet without applying the conductive paste layer on both sides of the surface of the dielectric green sheet, and then stacking the dielectric green sheets and sintering them. However, the side margin portion 140 is not limited to this formation method.

[0061] The covering part and the side margin part 140 serve to prevent damage to the first and second internal electrode layers 121 and 122 due to physical stress or chemical stress.

[0062] The dielectric layer 111 according to the embodiment includes a barium titanate-based main component and gallium (Ga), and the barium titanate-based main component includes barium (Ba) and titanium (Ti).

[0063] The capacitor body 110 may be formed by sintering a stacked structure in which a plurality of dielectric layers 111 and internal electrode layers 121 and 122 are stacked in a thickness direction (T-axis direction). At this time, since the internal electrode layers 121 and 122 including metal are sintered at a relatively lower temperature than the dielectric layer 111 including ceramic, the internal electrode layers 121 and 122 may be over-sintered and over-contracted when the dielectric layer 111 is sintered, resulting in cracks.

[0064] According to an embodiment, gallium (Ga) may be used as a low-temperature sintering agent that alleviates a sintering mismatch between the dielectric layer 111 and the internal electrode layers 121 and 122 .

[0065] The barium titanate-based main component is a dielectric base material, has a high dielectric constant, and contributes to forming the dielectric constant of the multilayer ceramic capacitor 100 .

[0066] Gallium (Ga) may be an element formed by a gallium (Ga) complex (i.e., gallium (Ga) may be an element derived from a gallium (Ga) complex), and the gallium (Ga) complex is a material added to a dielectric substrate. When gallium (Ga) is formed by a gallium (Ga) complex, gallium (Ga) is stably added so that it can be uniformly distributed in atomic units, thereby improving the low temperature sintering effect of the dielectric layer.

[0067] Therefore, by alleviating the sintering mismatch between the dielectric layer and the internal electrode layer, electrode breakage may be minimized and internal electrode connectivity may be improved.

[0068] In addition, gallium (Ga) is a metal element having a low melting point of 29.76° C., and may exist in a liquid form at a temperature higher than 30° C. This may accelerate phenomena such as heat transfer and mass transfer, thereby providing a low temperature sintering effect of the dielectric layer.

[0069] Specifically, when TEM-EDS (Transmission Electron Microscopy-Energy Dispersive Spectroscopy) analysis is performed in a region near the interface between the dielectric layer 111 and the internal electrode layers 121 and 122, that is, in a region R near the interface, the peak intensity ratio (I Ba / I Ga ) may be 1.0 to 5.0, for example, 1.1 to 3.0, or 1.2 to 2.0. In TEM-EDS analysis, when the peak intensity ratio (I Ba / I Ga ) is within the above range, sintering mismatch between the dielectric layer and the inner electrode layer can be alleviated, electrode breakage can be minimized, and thus inner electrode connectivity can be improved. Therefore, it is possible to ensure that the multilayer ceramic capacitor has high reliability without causing a short circuit.

[0070] Here, the region R near the interface may be defined as a region starting from the interface between the dielectric layer 111 and the internal electrode layers 121 and 122 and extending from the interface to a depth surface of 10nm to 500nm (e.g., a depth surface of 50nm to 200nm) within the dielectric layer 111.

[0071] Figure 4 The region R near the interface is shown to help understand, and for convenience, only one region R near the interface is shown, but it is not limited to this figure. In other words, the region R near the interface may exist anywhere where the interface between the dielectric layer 111 and the internal electrode layers 121 and 122 exists, and may exist on another surface other than one surface of one internal electrode layer.

[0072] TEM-EDS analysis can be performed as follows. Specifically, after the multilayer ceramic capacitor 100 is placed in the epoxy resin mixture and cured, the W-axis direction and T-axis direction surfaces (WT surfaces) of the capacitor body 110 are polished to a 1 / 2 point in the L-axis direction, fixed and maintained in a vacuum atmosphere chamber, so that a cross-sectional sample can be obtained to observe the effective portion where the dielectric layer 111 and the internal electrode layers 121 and 122 overlap.

[0073] Then, a transmission electron microscope (TEM) can be used to measure the central part of the effective part of the cross-sectional sample. TEM analysis can be performed using a Xe-FIB (focused ion beam) under the conditions of an acceleration voltage of 200 kV and an analysis magnification of 110 k times, and measurement can be performed to capture at least 1 layer (e.g., at least 3 layers, at least 5 layers, or at least 10 layers) of the dielectric layer 111 and the inner electrode layers 121 and 122.

[0074] Next, in the TEM image of the measured cross-section sample, the peak intensities of gallium (Ga) and barium (Ba) can be obtained by EDS analysis. The peak intensity ratio of Ba / Ga (I Ba / I Ga ) is the peak intensity of barium (Ba) divided by the peak intensity of gallium (Ga) shown in the TEM-EDS analysis. The peak intensity ratio of Ba / Ga may be an average value measured at at least two points (e.g., at least three points or at least five points) in the effective portion for the region R near the interface. For example, if the region R near the interface is measured at two points, it may be an average value of the peak intensity ratio of Ba / Ga at each point.

[0075] Furthermore, when TEM-EDS analysis was performed in the region R near the interface in the same manner as above, the peak intensity ratio (I Ti / I Ga ) can be 1.0 to 5.0, such as 1.1 to 3.0, or 1.2 to 2.0. In TEM-EDS analysis, when the peak intensity ratio (I Ti / I Ga ) is within the above range, the sintering mismatch between the dielectric layer and the internal electrode layer can be alleviated, the electrode breakage can be minimized, and thus the internal electrode connectivity can be improved.

[0076] Based on 100 parts by mole of the barium titanate-based main component, the amount of gallium (Ga) included in the dielectric layer 111 may be 0.01 parts by mole to 10 parts by mole, for example, 0.05 parts by mole to 8 parts by mole, or 0.1 parts by mole to 5 parts by mole. When the gallium (Ga) included is within the above content range, the low-temperature sintering effect of the dielectric layer can be improved, and thus, the sintering mismatch between the dielectric layer and the inner electrode layer can be reduced, and the electrode breakage can be minimized, so that the inner electrode connectivity can be improved. Therefore, a highly reliable multilayer ceramic capacitor can be ensured without causing a short circuit.

[0077] The dielectric layer 111 according to an embodiment may further include a secondary component including aluminum (Al), silicon (Si), magnesium (Mg), vanadium (V), manganese (Mn), or a combination thereof. Gallium (Ga) may also exist in the second phase in combination with these secondary components.

[0078] The secondary components may originate from metal oxides added as secondary components to the dielectric matrix.

[0079] When a region near the interface between the dielectric layer 111 and the internal electrode layers 121 and 122 (i.e., a region R near the interface) is subjected to TEM-EDS analysis in the same manner as described above, the peak intensity ratio (I Al / I Ga ) may be 1.0 to 5.0, for example, 1.0 to 4.0 or 1.2 to 3.0. In TEM-EDS analysis, when the peak intensity ratio (I Al / I Ga) is within the above range, the sintering mismatch between the dielectric layer and the internal electrode layer can be alleviated, the electrode breakage can be minimized, and thus the internal electrode connectivity can be improved.

[0080] In addition, when a region near the interface between the dielectric layer 111 and the internal electrode layers 121 and 122 (i.e., a region R near the interface) is subjected to TEM-EDS analysis in the same manner as described above, the peak intensity ratio (I Si / I Ga ) may be 1.0 to 5.0, for example, 1.0 to 4.0 or 1.5 to 3.0. In TEM-EDS analysis, when the peak intensity ratio (I Si / I Ga ) is within the above range, sintering mismatch between the dielectric layer and the internal electrode layer can be alleviated, electrode breakage can be minimized, and thus internal electrode connectivity can be improved.

[0081] In addition, when a region near the interface between the dielectric layer 111 and the internal electrode layers 121 and 122 (i.e., a region R near the interface) is subjected to TEM-EDS analysis in the same manner as described above, the peak intensity ratio (I Mg / I Ga ) may be 0.4 to 2.0, for example, 0.4 to 1.5, or 0.5 to 1.0. In TEM-EDS analysis, when the peak intensity ratio (I Mg / I Ga ) is within the above range, the sintering mismatch between the dielectric layer and the internal electrode layer can be alleviated, the electrode breakage can be minimized, and thus the internal electrode connectivity can be improved.

[0082] Based on 100 mole parts of the barium titanate-based main component, an amount of 0.01 to 5 mole parts of aluminum (Al) (subcomponent) may be included, based on 100 mole parts of the barium titanate-based main component, an amount of 0.01 to 5 mole parts of silicon (Si) may be included, based on 100 mole parts of the barium titanate-based main component, an amount of 0.01 to 5 mole parts of magnesium (Mg) may be included, based on 100 mole parts of the barium titanate-based main component, an amount of 0.01 to 5 mole parts of vanadium (V) may be included, and based on 100 mole parts of the barium titanate-based main component, an amount of 0.01 to 5 mole parts of manganese (Mn) may be included. When the content of each subcomponent is within the above content range, it is easy to form a second phase with gallium (Ga), and thus, the low-temperature sintering effect of the dielectric layer can be improved. Therefore, the sintering mismatch between the dielectric layer and the inner electrode layer can be reduced, and the electrode breakage can be minimized, so that the inner electrode connectivity can be improved.

[0083] The dielectric layer 111 may include a plurality of grains and grain boundaries between adjacent grains.

[0084] The grains may include a barium titanate-based main component.

[0085] Gallium (Ga) may be present in both the grains and grain boundaries in the dielectric layer 111, for example, at the grain boundaries. In addition, gallium (Ga) may be present at the grain boundaries in the form of a second phase. Specifically, the molar ratio of gallium (Ga) present at the grain boundaries to gallium (Ga) present at the grains may be 5:1 to 50:1, for example, 10:1 to 30:1. When the molar ratio of gallium (Ga) present at the grain boundaries to gallium (Ga) present at the grains is within the above range, the sintering mismatch between the dielectric layer and the inner electrode layer may be reduced, electrode fracture may be minimized, and thus the inner electrode connectivity may be improved.

[0086] The average thickness (average length in the T-axis direction) of the dielectric layer 111 may be 2.0 μm to 8.0 μm, for example, 2.4 μm to 7.8 μm. When the average thickness of the dielectric layer 111 is within the above range, the reliability of the multilayer ceramic capacitor is excellent.

[0087] The average thickness of the dielectric layer 111 may be measured by placing the multilayer ceramic capacitor 100 in an epoxy resin mixture, curing it, polishing it, and then ion milling it to analyze it by SEM.

[0088] The SEM can use, for example, the Verios G4 product from Thermofisher Scientific. The measurement conditions are 10 kV, 0.2 nA, and the analysis magnification can be 100 times. The SEM measurement can be used to photograph at least one layer (for example, 3 or more layers, 5 or more layers, or 10 or more layers) of the dielectric layer 111. The average thickness of the dielectric layer 111 can be the arithmetic mean of the thickness of the dielectric layer 111 at 10 points in the SEM image that are spaced apart from a reference point at a predetermined interval, and the reference point is the center point in the length direction (L-axis direction) or the width direction (W-axis direction) of the dielectric layer 111.

[0089] The intervals between the 10 points may be adjusted according to the scale of the SEM image, and may be, for example, 1 μm to 100 μm, 1 μm to 50 μm, or 1 μm to 10 μm. At this time, all 10 points must be located within the dielectric layer 111. If not all 10 points are located within the dielectric layer 111, the position of the reference point may be changed, or the intervals between the 10 points may be adjusted.

[0090] The first inner electrode layer 121 and the second inner electrode layer 122 are electrode layers with different polarities, which are alternately arranged relative to each other along the T-axis direction, the dielectric layer 111 is interposed between the first inner electrode layer 121 and the second inner electrode layer 122, and one end of the first inner electrode layer 121 and one end of the second inner electrode layer 122 can be exposed through the third surface and the fourth surface of the capacitor body 110, respectively.

[0091] The first and second internal electrode layers 121 and 122 may be electrically insulated from each other by the dielectric layer 111 disposed therebetween.

[0092] One end of the first and second internal electrode layers 121 and 122 alternately exposed through the third and fourth surfaces of the capacitor body 110 may be connected and electrically connected to the first and second external electrodes 131 and 132 , respectively.

[0093] The first and second internal electrode layers 121 and 122 may include a conductive metal, for example, a metal such as Ni, Cu, Ag, Pd, Au, or an alloy thereof such as an Ag—Pd alloy.

[0094] In addition, the first and second internal electrode layers 121 and 122 may include dielectric particles having the same composition as the ceramic material included in the dielectric layer 111 .

[0095] The first and second internal electrode layers 121 and 122 may be formed using a conductive paste including a conductive metal. A printing method of the conductive paste may be a screen printing method or a gravure printing method.

[0096] The average thickness of the first and second internal electrode layers 121 and 122 may be 0.1 μm to 2 μm. The average thickness of the first and second internal electrode layers 121 and 122 may be measured by SEM analysis. Here, since the SEM analysis is the same as the above-mentioned method for measuring the average thickness of the dielectric layer 111, a description thereof will be omitted.

[0097] As described above, the capacitor body 110 may be formed by sintering a stacked structure of a plurality of dielectric layers 111 and internal electrode layers 121 and 122. Specifically, the capacitor body 110 may be formed by sintering at a temperature of 1000° C. to 1200° C. (e.g., 1050° C. to 1150° C.). By sintering the capacitor body 110 at a low temperature within the above temperature range, sintering mismatch between the dielectric layer 111 and the internal electrode layers 121 and 122 is mitigated, and thus electrode fracture may be minimized and internal electrode connectivity may be improved.

[0098] The multilayer ceramic capacitor 100 according to the embodiment may have an internal electrode connectivity of 80% to 100% in the effective portion A, for example, 82% to 95%, or 84% to 93%. When the internal electrode connectivity in the effective portion A is within the above range, the occurrence of electrode breakage is minimized, and thus a highly reliable multilayer ceramic capacitor without short circuits can be ensured. Here, the effective portion A is a region where the dielectric layer 111 and the internal electrode layers 121 and 122 are alternately arranged, such as Figure 3 shown.

[0099] The inter-electrode connectivity can be measured as follows.

[0100] First, after the multilayer ceramic capacitor 100 is placed in the epoxy resin mixture and cured, the W-axis and T-axis direction surfaces (WT surfaces) of the capacitor body 110 are polished to the 1 / 2 point in the L-axis direction, fixed and maintained in a vacuum atmosphere chamber so that a cross-sectional sample can be obtained to observe the effective portion where the dielectric layer 111 overlaps with the internal electrode layers 121 and 122.

[0101] Next, the effective part of the cross-sectional sample can be ion milled and measured using SEM. SEM can use, for example, the Verios G4 product from Thermofisher Scientific. The measurement conditions are 10 kV, 0.2 nA, and the analysis magnification can be 100 times. SEM measurement can be used to produce at least one layer (e.g., 3 or more layers, 5 or more layers, or 10 or more layers) of dielectric layer 111.

[0102] Therefore, the internal electrode connectivity may be calculated using the following Equation 1.

[0103] (Formula 1)

[0104] Internal electrode connectivity (%) = (total length of connected portions excluding disconnected portions in a plurality of internal electrode layers / total length of a plurality of internal electrode layers) × 100

[0105] In Formula 1, the denominator is the sum of the total lengths of the plurality of internal electrode layers present in the effective portion A, which is a value including all the connection portions L and the disconnection portions C. In Formula 1, the numerator is the sum of the lengths of the connection portions L in the plurality of internal electrode layers excluding the disconnection portions C. For reference, Figure 4 , for convenience, the connecting portion L and the disconnecting portion C are shown only in one place, and the indications in other portions are omitted.

[0106] In addition, the multilayer ceramic capacitor 100 according to the embodiment may have 80% to 100% internal electrode connectivity in the region near the side edge portion B, for example, 82% to 95% or 84% to 93%. Figure 3 ) is within the above range, the occurrence of electrode breakage can be minimized, thereby ensuring a highly reliable multilayer ceramic capacitor without short circuit.

[0107] Here, as above Figure 3 As shown, area B near the side edge portion refers to an area extending from the boundary between the effective portion A and the side edge portion 140 into the effective portion A to a depth surface corresponding to 5% to 20% (for example, 8% to 15%) of the total length of the effective portion A in the width direction (W-axis direction).

[0108] The method of measuring the inner electrode connectivity in the region B near the side edge portion is the same as the method defined by Formula 1 described above.

[0109] The first and second external electrodes 131 and 132 are supplied with voltages of different polarities and may be electrically connected to exposed portions of the first and second internal electrode layers 121 and 122 , respectively.

[0110] According to the above configuration, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charges are accumulated between the opposing first and second internal electrode layers 121 and 122. At this time, the capacitance of the multilayer ceramic capacitor 100 is proportional to the overlapping area where the first and second internal electrode layers 121 and 122 overlap each other in the T-axis direction in the effective portion A.

[0111] The first external electrode 131 may include a first connecting portion arranged on the third surface of the capacitor body 110 to be connected to the first internal electrode layer 121, and a first band portion arranged at a corner where the third surface of the capacitor body 110 intersects with the first surface, the second surface, the fifth surface and the sixth surface. The second external electrode 132 may include a second connecting portion arranged on the fourth surface of the capacitor body 110 to be connected to the second internal electrode layer 122, and a second band portion arranged at a corner where the fourth surface of the capacitor body 110 intersects with the first surface, the second surface, the fifth surface and the sixth surface.

[0112] The first band portion may extend from the first connection portion to a portion of the first surface and the second surface of the capacitor body 110, and may further extend from the first connection portion to a portion of the fifth surface and the sixth surface of the capacitor body 110, and the second band portion may extend from the second connection portion to a portion of the first surface and the second surface of the capacitor body 110, and may further extend from the second connection portion to a portion of the fifth surface and the sixth surface of the capacitor body 110. The first band portion and the second band portion may be used to improve the bonding strength of the first external electrode 131 and the second external electrode 132.

[0113] The first and second external electrodes 131 and 132 may each include a sintered metal layer contacting the capacitor body 110 , a conductive resin layer disposed to cover the sintered metal layer, and a plated layer disposed to cover the conductive resin layer.

[0114] The sintered metal layer may include conductive metal and glass.

[0115] The conductive metal may include copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof or combinations thereof. For example, the conductive metal including copper (Cu) may mean that the conductive metal includes copper (Cu) or a copper (Cu) alloy. When the conductive metal includes copper, other metals other than copper may be included in an amount of 5 mol parts or less based on 100 mol parts of copper.

[0116] The glass may include an oxide, for example, may include one or more selected from the group consisting of silicon oxide, boron oxide, aluminum oxide, transition metal oxide, alkali metal oxide, and alkaline earth metal oxide. The transition metal is selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni), the alkali metal may be selected from the group consisting of lithium (Li), sodium (Na), and potassium (K), and the alkaline earth metal may be selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba). One or more.

[0117] Alternatively, the conductive resin layer is formed on the sintered metal layer, for example, may be formed to completely cover the sintered metal layer. In addition, the first external electrode 131 and the second external electrode 132 may not include the sintered metal layer. In this case, the conductive resin layer may be in direct contact with the capacitor body 110.

[0118] The conductive resin layer extends to the first and second surfaces of the capacitor body 110, and may also extend to the fifth and sixth surfaces of the capacitor body 110, and the length of the region (i.e., the band portion) where the conductive resin layer extends and is disposed to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110 may be longer than the length of the region (i.e., the band portion) where the sintered metal layer extends and is disposed to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110.

[0119] In other words, the conductive resin layer is formed on the sintered metal layer, and may be formed to completely cover the sintered metal layer.

[0120] The conductive resin layer includes resin and conductive metal.

[0121] The resin included in the conductive resin layer may be implemented by a material having adhesiveness and shock absorption and capable of forming a paste when mixed with the conductive metal powder, but is not limited thereto. For example, the resin may include phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin.

[0122] The conductive metal included in the conductive resin layer serves to electrically connect the first internal electrode layer 121 or the second internal electrode layer 122 or to electrically connect the sintered metal layer.

[0123] The conductive metal included in the conductive resin layer may have a spherical shape, a flake shape, or a combination thereof. That is, the conductive metal may be formed only in a flake form, only in a spherical form, or in a mixed form of a flake form and a spherical form.

[0124] Here, the spherical shape may also include a shape that is not a perfect spherical shape, for example, a shape in which the length ratio of the major axis to the minor axis (major axis / minor axis) is 1.45 or less. The flake shape refers to a shape having a flat and elongated shape, and is not particularly limited. However, for example, the length ratio of the major axis to the minor axis (major axis / minor axis) may be 1.95 or more.

[0125] The first and second external electrodes 131 and 132 may further include a plating layer disposed outside the conductive resin layer.

[0126] The plating layer may include a single nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti) or lead (Pb) or an alloy thereof. For example, the plating layer may be a nickel (Ni) plating layer or a tin (Sn) plating layer, may be a nickel (Ni) plating layer and a tin (Sn) plating layer stacked in sequence, or may be a tin (Sn) plating layer, a nickel (Ni) plating layer and a tin (Sn) plating layer stacked in sequence.

[0127] In addition, the plating layer may include a plurality of nickel (Ni) plating layers and / or a plurality of tin (Sn) plating layers.

[0128] The plating layer may improve the mountability to a substrate, structural reliability, durability to the outside, heat resistance, and equivalent series resistance (ESR) of the multilayer capacitor 100 .

[0129] Hereinafter, a method of manufacturing the multilayer ceramic capacitor 100 according to an embodiment will be described.

[0130] According to an embodiment, a method for preparing a multilayer ceramic capacitor 100 may include: preparing a dielectric slurry by mixing a barium titanate-based main component powder and a gallium (Ga) complex; preparing a dielectric green sheet using the dielectric slurry, and forming a conductive paste layer on a surface of the dielectric green sheet; preparing a dielectric green sheet stacking structure by stacking the dielectric green sheets on which the conductive paste layer is formed; preparing a capacitor body including a dielectric layer and an inner electrode layer by sintering the dielectric green sheet stacking structure; and forming an outer electrode on one surface of the capacitor body.

[0131] The dielectric slurry may be produced by mixing a barium titanate-based main component powder and a gallium (Ga) complex.

[0132] The gallium (Ga) complex is a compound in which gallium (Ga) is dispersed in a polycarboxylic acid compound and has an ion form, and may include gallium carboxylate in an ion form.

[0133] The gallium (Ga) complex may be mixed in an amount of 0.01 to 10 parts by mol (eg, 0.05 to 8 parts by mol, or 0.1 to 5 parts by mol) based on 100 parts by mol of the barium titanate-based main component powder.

[0134] When the gallium (Ga) complex is mixed within the above content range, gallium (Ga) is stably added to barium titanate (corresponding to the dielectric substrate), so that atoms can be evenly distributed, thereby improving the low-temperature sintering effect of the dielectric layer. Therefore, by alleviating the sintering mismatch between the dielectric layer and the internal electrode layer, electrode breakage can be minimized and internal electrode connectivity can be improved.

[0135] The dielectric slurry can be prepared by additionally mixing a subsidiary component powder. The subsidiary component powder can be used in the form of a sol dispersed in an organic solvent.

[0136] The auxiliary component powder may include aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), magnesium oxide (MgO), vanadium oxide (V 2 O 5 ), manganese oxide (MnO 2 ) or a combination thereof. The auxiliary component powder may be used in the form of a sol dispersed in an organic solvent.

[0137] Based on 100 parts by mole of barium titanate-based main component powder, aluminum oxide (Al 2 O 3 ) may be mixed in an amount of 0.01 to 5 parts by mole, based on 100 parts by mole of the barium titanate-based main component powder, silicon dioxide (SiO 2 ) may be mixed in an amount of 0.01 to 5 parts by mole based on 100 parts by mole of the barium titanate-based main component powder, magnesium oxide (MgO) may be mixed in an amount of 0.01 to 5 parts by mole based on 100 parts by mole of the barium titanate-based main component powder, vanadium oxide (V 2 O 5 ) may be mixed in an amount of 0.01 to 5 parts by mole, based on 100 parts by mole of the barium titanate-based main component powder, manganese oxide (MnO 2 ) can be mixed in an amount of 0.01 to 5 parts by mole. When the auxiliary component powder is mixed within the above content range, it is easy to form a second phase with gallium (Ga), thereby improving the low temperature sintering effect of the dielectric layer.

[0138] In addition, the dielectric slurry may be prepared by further mixing additives such as a dispersant, a binder, a plasticizer, a lubricant, and an antistatic agent and a solvent.

[0139] The dispersant may include, for example, a phosphate dispersant, a polycarboxylic acid dispersant, or a combination thereof. Based on 100 parts by weight of the total amount of barium titanate and gallium (Ga) complex, the dispersant may be mixed in an amount of 0.1 to 5 parts by weight (e.g., 0.3 to 3 parts by weight). When the dispersant is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the prepared dielectric layer can be reduced.

[0140] The binder may be, for example, an acrylic resin, a polyvinyl butyral resin, a polyvinyl acetal resin, or an ethyl cellulose resin, etc. The binder may be added in an amount of 0.1 to 50 parts by weight (e.g., 3 to 30 parts by weight) based on 100 parts by weight of the total amount of the barium titanate and gallium (Ga) complex. When the binder is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the prepared dielectric layer can be reduced.

[0141] The plasticizer may include, for example, phthalic acid compounds such as dioctyl phthalate, benzyl butyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl)phthalate and di(2-ethylbutyl)phthalate; adipic acid compounds such as dihexyl adipate and di(2-ethylhexyl) adipate; glycol compounds such as ethylene glycol, diethylene glycol and triethylene glycol; glycol ester compounds such as triethylene glycol dibutyrate, triethylene glycol di(2-ethylbutyrate) and triethylene glycol di(2-ethylhexanoate). Based on 100 parts by weight of the total amount of barium titanate and gallium (Ga) complex, the plasticizer may be added in an amount of 0.1 to 20 parts by weight (e.g., 1 to 10 parts by weight). When the plasticizer is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities included in the prepared dielectric layer can be reduced.

[0142] The solvent may be an aqueous solvent such as water; an alcohol solvent such as ethanol, methanol, benzyl alcohol, and methoxyethanol; a glycol solvent such as ethylene glycol and diethylene glycol; a ketone solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, and cyclohexanone; an ester solvent such as butyl acetate, ethyl acetate, carbitol acetate, and butyl carbitol acetate; an ether solvent such as methyl cellosolve, ethyl cellosolve, butyl ether, and tetrahydrofuran; an aromatic solvent such as benzene, toluene, or xylene. For example, the solvent may be selected in consideration of the solubility or dispersibility of various additives included in the dielectric slurry, and an alcohol solvent or an aromatic solvent may be used.

[0143] The solvent may be mixed in an amount of 50 to 1000 parts by weight (e.g., 100 to 500 parts by weight) based on 100 parts by weight of the total amount of the barium titanate and the gallium (Ga) complex. When the solvent is mixed within the above content range, the dielectric slurry components may be fully mixed, and the solvent may be easily removed thereafter.

[0144] The mixing of the barium titanate main component powder, the gallium (Ga) complex, and the optional auxiliary component powder can be performed using a wet ball mill or a stirring mill.

[0145] When zirconia balls are used in a wet ball mill, a plurality of zirconia balls having a diameter of 0.1 mm to 10 mm may be used for wet mixing for 8 to 48 hours, or 10 to 24 hours.

[0146] After sintering, the prepared dielectric slurry is formed into a dielectric layer.

[0147] As a method for molding the prepared dielectric slurry into a sheet, a belt molding method such as a doctor blade method, a calender roll method, etc. can be used. For example, the prepared dielectric slurry can be molded into a sheet using a roller molding coater with a head discharge method, and the dielectric green sheet can be obtained by drying the molded body afterwards.

[0148] In order to form a conductive paste layer which becomes an inner electrode layer after sintering, the conductive paste can be prepared by mixing a conductive powder made of a conductive metal or its alloy, a binder and a solvent. In addition, if necessary, barium titanate powder as a co-material can be mixed together. The co-material can be used to suppress the sintering of the conductive powder during the sintering process. The conductive paste layer is formed by applying the conductive paste to the surface of the dielectric green sheet in a predetermined pattern using various printing methods such as a screen printing method or a transfer method.

[0149] Next, a dielectric green sheet stack structure is prepared by stacking a plurality of dielectric green sheets on which the internal electrode patterns are formed, and then pressing the plurality of dielectric green sheets in a stacking direction. At this time, the dielectric green sheets and the internal electrode patterns may be stacked such that the dielectric green sheets are located on the upper and lower surfaces of the dielectric green sheet stack structure in the stacking direction.

[0150] Alternatively, a step of cutting the prepared dielectric green sheet stack structure into a predetermined size by dicing or the like may be performed.

[0151] In addition, if necessary, the dielectric green sheet stack structure may be cured and dried to remove the plasticizer and the like, and after the curing and drying, the dielectric green sheet stack structure may be subjected to drum polishing using a horizontal centrifugal drum machine and the like. In drum polishing, the dielectric green sheet stack structure is placed in a drum container having a medium and a polishing liquid, and a rotational motion or vibration is applied to the drum container, so that unnecessary portions such as burrs generated during cutting can be polished.

[0152] In addition, after barrel polishing, the dielectric green sheet stack may be cleaned with a cleaning solution such as water and dried.

[0153] Subsequently, a capacitor body may be prepared after a binder removal process and sintering of the dielectric green sheet stack structure.

[0154] The conditions for removing the binder may be appropriately adjusted according to the components of the dielectric layer or the internal electrode layer.

[0155] For example, the temperature increase rate during the binder removal process may be 5°C / hour to 300°C / hour, the process temperature may be 180°C to 400°C, and the temperature holding time may be 0.5 hour to 24 hours. The process atmosphere for binder removal may be an air atmosphere or a reducing atmosphere.

[0156] The sintering of the dielectric green sheet stack structure may be performed at a temperature of 1000° C. to 1200° C. (e.g., 1050° C. to 1150° C.). When sintering is performed at a temperature within the above range, sintering mismatch between the dielectric layer and the internal electrode layer is alleviated, thereby minimizing electrode breakage and improving internal electrode connectivity.

[0157] In addition, the sintering may be performed for 0.5 hours to 8 hours, for example, 1 hour to 3 hours. In addition, the sintering may be performed in a reducing atmosphere, for example, in a humidified mixed gas of nitrogen and hydrogen. When the inner electrode layer includes nickel (Ni) or a nickel (Ni) alloy, the oxygen partial pressure in the sintering atmosphere may be 1.0×10 -14 MPa to 1.0×10 -10 MPa.

[0158] After sintering, annealing may be performed as needed. Annealing is a process for reoxidizing the dielectric layer, and if sintering is performed in a reducing atmosphere, annealing may be performed. The conditions of the annealing process may also be appropriately adjusted according to the composition of the dielectric layer. For example, the annealing temperature may be 950°C to 1150°C, the time may be 1 minute to 20 hours, and the temperature increase rate may be 50°C / hour to 500°C / hour. The annealing atmosphere may be humidified nitrogen (N 2 ) atmosphere, and the oxygen partial pressure may be 1.0×10 -9 MPa to 1.0×10 -5 MPa.

[0159] In the binder removal process, the sintering process or the annealing process, for example, a wetting agent may be used to wet the nitrogen gas or the mixed gas. In this case, the wetting agent temperature may be 5° C. to 75° C. The binder removal process, the sintering process and the annealing process may be performed sequentially or independently.

[0160] Optionally, surface treatment such as sandblasting, laser irradiation, barrel polishing, etc. may be performed on the third and fourth surfaces of the prepared capacitor body 110. By performing the surface treatment, ends of the first and second inner electrode layers may be exposed to the third and fourth surfaces, thereby improving electrical connection between the first outer electrode and the first inner electrode layer and between the second outer electrode and the second inner electrode layer.

[0161] Next, external electrodes are formed on the outer surface of the prepared capacitor body 110 .

[0162] For example, a paste for forming a sintered metal layer may be applied to the external electrode and then sintered to form the sintered metal layer.

[0163] The paste for forming the sintered metal layer may include conductive metal and glass. Since the description of conductive metal and glass is the same as above, repeated description will be omitted. In addition, optionally, the paste for forming the sintered metal layer may include adhesive, solvent, dispersant, plasticizer, oxide powder, etc. The adhesive may be, for example, ethyl cellulose, acrylic acid, butyral, etc., and the solvent may be, for example, an organic solvent or an aqueous solvent, such as, alcohol (for example, terpineol, butyl carbitol), methyl ethyl ketone, acetone, toluene, etc.

[0164] The method of applying the paste for forming the sintered metal layer on the outer surface of the capacitor body 110 may include a dipping method, various printing methods such as screen printing, an application method using a dispenser, etc., and a spraying method using spraying. The paste for forming the sintered metal layer may be applied to at least the third and fourth surfaces of the capacitor body 110, and optionally, to portions of the first, second, fifth, or sixth surfaces on which the band portions of the first and second external electrodes are to be formed.

[0165] Thereafter, the capacitor body 110 on which the paste for forming the sintered metal layer is applied is dried and sintered at a temperature of 700° C. to 1000° C. for 0.1 to 3 hours to form a sintered metal layer.

[0166] Alternatively, a paste for forming a conductive resin layer may be applied to the outer surface of the obtained capacitor body 110 and then cured to form the conductive resin layer.

[0167] The paste for forming the conductive resin layer may include resin and conductive metal, and optionally include non-conductive filler. Since the description of conductive metal and resin is the same as above, repeated description is omitted. In addition, optionally, the paste for forming the conductive resin layer may include adhesive, solvent, dispersant, plasticizer, oxide powder, etc. The adhesive may be, for example, ethyl cellulose, acrylic acid, butyral, etc., and the solvent may be an organic solvent or an aqueous solvent, such as, alcohol (for example, terpineol, butyl carbitol), methyl ethyl ketone, acetone, and toluene.

[0168] For example, the method of forming the conductive resin layer may include: immersing the capacitor body 110 in a paste for forming the conductive resin layer and then curing it, or printing the paste for forming the conductive resin layer on the surface of the capacitor body 110 by a screen printing method or a gravure printing method, or by applying the paste for forming the conductive resin layer to the surface of the capacitor body 110 and then curing it.

[0169] Next, a plating layer is formed on the outer side of the conductive resin layer.

[0170] For example, the plated layer can be formed by a plating method, sputtering, or electrolytic plating (electrodeposition).

[0171] The above embodiments will be described in more detail by the following examples. However, the following examples are only for illustrative purposes and do not limit the scope of the appended claims.

[0172] (Manufacturing of Multilayer Ceramic Capacitors)

[0173] Examples 1 to 3 and Comparative Examples 1 and 2

[0174] By using barium titanate (BaTiO 3 ) powder, gallium raw material and aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), magnesium oxide (MgO), vanadium oxide (V 2 O 5 ) and manganese oxide (MnO 2 ) were mixed with the auxiliary component powders of the composition shown in Table 1 to prepare a dielectric slurry. At this time, in Examples 1 to 3, ionic gallium carboxylate (Ga-COO) was used as the gallium raw material, and in Comparative Example 1, gallium oxide (Ga 2 O 3 ), and in Comparative Example 2, no gallium raw material was used. By using zirconium balls (ZrO 2 The mixture is prepared by mixing the obtained mixture with polyvinyl butyral (PVB) resin (polyvinyl butyral (PVB) resin) as a dispersion medium, and adding ethanol / toluene and polyvinyl butyral (PVB) resin as a wetting and dispersing agent and a binder, followed by mechanical grinding for mixing.

[0175] A dielectric green sheet was prepared using the prepared dielectric slurry using a roll die coater.

[0176] A conductive paste layer containing nickel (Ni) was printed on the surface of the dielectric green sheet, and the dielectric green sheets (width×length×height=3.2 mm×2.5 mm×2.5 mm) formed with the conductive paste layer were stacked and pressed to prepare a dielectric green sheet stack structure.

[0177] The binder removal process is performed in a nitrogen atmosphere at 400°C or less, and the sintering temperature is 1200°C or less in a 1.0% H 2 The dielectric green sheet stack is sintered at a hydrogen concentration of 0.1% or less to form a capacitor body.

[0178] Next, external electrodes are formed on the outer surface of the capacitor body to prepare a multilayer ceramic capacitor.

[0179] (Table 1)

[0180] The unit is based on 100 mole parts of BaTiO 3 Indicates the molar parts.

[0181] Barium Titanate Ga raw materials <![CDATA[Al 2 THE 3 ]]> <![CDATA[SiO 2 ]]> MgO <![CDATA[V 2 THE 5 ]]> <![CDATA[MnO 2 ]]> Example 1 100 0.3 0.3 2.5 1.0 0.1 0.1 Example 2 100 0.6 0.3 2.5 1.0 0.1 0.1 Example 3 100 0.9 0.3 2.5 1.0 0.1 0.1 Comparative Example 1 100 0.3 0.3 2.5 1.0 0.1 0.1 Comparative Example 2 100 0 0.3 2.5 1.0 0.1 0.1

[0182] Assessment 1: TEM-EDS analysis

[0183] The multilayer ceramic capacitors prepared in Example 1 and Comparative Example 1 were subjected to TEM-EDS (Transmission Electron Microscopy-Energy Dispersive Spectroscopy) analysis, and the peak intensity of each element detected and the peak intensity ratio between two elements are shown in Tables 2 and 3 below.

[0184] The case of Example 1 is shown in Table 2 below, and the case of Comparative Example 1 is shown in Table 3 below.

[0185] TEM-EDS analysis is performed as follows. After the multilayer ceramic capacitor prepared in Example 1 and Comparative Example 1 is placed in an epoxy resin mixture and cured, the W-axis direction and T-axis direction surfaces (WT surfaces) of the capacitor body 110 are polished to 1 / 2 point in the L-axis direction, fixed and maintained in a vacuum atmosphere chamber, so that a cross-sectional sample is obtained to observe the effective portion where the dielectric layer and the inner electrode layer are stacked. The central part of the effective portion of the cross-sectional sample is measured by TEM. TEM analysis is performed using Xe-FIB (focused ion beam) under conditions of an acceleration voltage of 200kV and an analytical magnification of 110k times, and measurements are performed to shoot at least 5 dielectric layers and inner electrode layers. In the TEM image of the measured cross-sectional sample, an EDS analysis is performed on the region R near the interface starting from the interface between the dielectric layer and the inner electrode layer and extending from the interface into the dielectric layer to a depth surface of 100nm from the interface to measure the peak intensity ratio between the elements. The peak intensity ratio between each element is measured at two points in the region R near the interface in the effective portion to obtain the average value of the peak intensity ratio.

[0186] The peak intensity of each element and the peak intensity ratio of two elements shown in Tables 2 and 3 below are Figure 5 and Figure 6 Average value measured at the two points shown. Figure 5is a TEM-EDS analysis image of the multilayer ceramic capacitor according to Example 1, Figure 6 is a TEM-EDS analysis image of the multilayer ceramic capacitor according to Comparative Example 1.

[0187] In the following Tables 2 and 3, E1 is the peak intensity of each element at point 1, and E2 is the peak intensity of each element at point 2. After calculating the peak intensity of each element, the peak intensity ratio is obtained by setting the peak intensity of Ga as the denominator. The average value represents the average value of the E1 / Ga ratio and the E2 / Ga ratio.

[0188] (Table 2)

[0189] element O Mg Al Si Ti V Mn Ga Ba total E1 54.9 3.8 8.8 11.3 8.1 0.3 0.4 5.4 7 100 E2 51.1 3.2 8.3 12.3 9 0.4 0.5 6.8 8.4 100 E1 / Ga 10.15 0.70 1.63 2.09 1.50 0.06 0.07 1.00 1.30 - E2 / Ga 7.53 0.47 1.22 1.81 1.32 0.06 0.07 1.00 1.24 - average value 8.84 0.59 1.43 1.95 1.41 0.06 0.07 1.00 1.27 -

[0190] (Table 3)

[0191] element O Mg Al Si Ti V Mn Ga Ba total E1 60.0 4.4 2.8 0.8 4.6 0.1 1.1 25.6 0.6 100 E2 61.0 2.8 3.2 0.3 5.6 0.6 1.2 18.2 7.2 100 E1 / Ga 2.34 0.17 0.11 0.03 0.18 0.00 0.04 1.00 0.02 - E2 / Ga 3.35 0.15 0.18 0.02 0.31 0.03 0.06 1.00 0.40 - average value 2.85 0.16 0.14 0.02 0.24 0.02 0.05 1.00 0.21 -

[0192] Referring to Tables 2 and 3, it can be seen that in the case of Example 1 in which the gallium complex according to the embodiment is applied, the peak intensity ratio (I Ba / I Ga ) is in the range of 1.0 to 5.0, while in the case of Comparative Example 1 in which Ga in the form of metal oxide is applied, the peak intensity ratio (I Ba / I Ga ) is displayed as 0.21.

[0193] In addition, in the case of Comparative Example 1 in which Ga in the form of a metal oxide is applied, the peak intensity of Ga is large in a region near the interface between the dielectric layer and the inner electrode layer (i.e., in a region R near the interface), which indicates the possibility that Ga exists locally or alone. On the other hand, referring to Table 2, in Example 1 in which a gallium complex is applied, the peak intensity of Ga is relatively low in a region R near the interface, which means that Ga forms a glass phase (second phase) with elements such as Mg, Al, Si, etc., and is uniformly distributed in the glass phase. The formation of the glass phase can be seen by the fact that the peak intensity ratio of Al / Ga and the peak intensity ratio of Si / Ga are 1 or more.

[0194] Assessment 2: STEM-EDS analysis

[0195] The active part of the multilayer ceramic capacitor prepared in Example 3 was subjected to scanning transmission electron microscopy-energy dispersive spectroscopy (STEM-EDS) mapping analysis, and the results are shown in FIG. Figure 7 middle.

[0196] STEM-EDS analysis was performed as follows. After obtaining a cross-sectional sample from the multilayer ceramic capacitor prepared in Example 3 using the same method as in Evaluation 1, the central part of the effective portion of the cross-sectional sample was measured using STEM. STEM analysis was performed using Xe-FIB (focused ion beam) under conditions of an acceleration voltage of 200 kV and an analysis magnification of 110 k times. In the STEM image of the measured cross-sectional sample, EDS analysis was performed on an area R near the interface, which was an area starting from the interface between the dielectric layer and the inner electrode layer and extending from the interface into the dielectric layer to a depth of 100 nm on the surface.

[0197] Figure 7 Results of STEM-EDS mapping analysis of an effective portion of the multilayer ceramic capacitor according to Example 3 are shown.

[0198] Reference Figure 7 , it can be seen that Ga is uniformly distributed throughout the effective portion of the multilayer ceramic capacitor according to the embodiment, Ga is relatively more distributed at the grain boundaries than in the grains, and also exists at the grain boundaries in the form of a glass second phase.

[0199] Assessment 3: Internal Electrode Connectivity

[0200] The multilayer ceramic capacitors prepared in Example 1 and Example 2 and Comparative Example 2 were subjected to SEM (Scanning Electron Microscope) analysis to evaluate the internal electrode connectivity, and the results are shown in FIG. Figure 8 and 9 middle.

[0201] Figure 8 is an SEM image of an effective portion of the multilayer ceramic capacitor according to Examples 1 and 2 and Comparative Example 2, and Fig. 9 1 and 2 are SEM images of regions near side edge portions of the multilayer ceramic capacitors according to Examples 1 and 2 and Comparative Example 2.

[0202] Specifically, refer to Figure 8 , a cross-sectional sample was obtained from the multilayer ceramic capacitor prepared in Example 1 and Example 2 and Comparative Example 2 in the same manner as in Evaluation 1, and then a cross-sectional sample was obtained by ion milling, and an effective portion A of the cross-sectional sample was subjected to SEM analysis, thereby measuring the internal electrode connectivity. The SEM analysis was performed using a VeriosG4 product from Thermofisher Scientific, and the measurement conditions were 10 kV, 0.2 nA. The analysis magnification was 100 times, and the measurement was performed to produce about 20 dielectric layers.

[0203] In addition, refer to Fig. 9, SEM analysis was performed on the area B near the side edge portion of the cross-sectional sample obtained above, thereby measuring the internal electrode connectivity. At this time, the area B near the side edge portion refers to an area extending from the boundary between the effective portion and the side edge portion into the effective portion to a depth surface corresponding to 10% of the total length in the width direction of the effective portion.

[0204] The internal electrode connectivity is calculated by the following Equation 1.

[0205] (Formula 1)

[0206] Internal electrode connectivity (%) = (total length of connected portions excluding disconnected portions in a plurality of internal electrode layers / total length of a plurality of internal electrode layers) × 100

[0207] Reference Figure 8 and Fig. 9 It can be seen that for the region including gallium (Ga) in the dielectric layer and near the interface, the peak intensity ratio of Ba / Ga (I Ba / I Ga ) in Examples 1 and 2 within the range of 1.0 to 5.0, the internal electrode connectivity in the areas near the effective portion and the side edge portion was excellent compared to the case of Comparative Example 2 in which gallium (Ga) was not included in the dielectric layer.

[0208] Evaluation 4: Low temperature sintering effect

[0209] Fig.10 is a graph showing changes in density of dielectric layers according to Examples 1 to 3 and Comparative Example 2 depending on sintering temperature.

[0210] Reference Fig.10 It can be seen that for Examples 1 to 3, 5.8 g / cm 3 The sintering temperature for achieving the target density value of Example 1 is about 1100°C, while for Comparative Example 2, the target density value is not achieved even when the sintering temperature exceeds 1150°C. In other words, it can be seen that Examples 1 to 3 show a low temperature sintering effect of about 50°C or higher in achieving the target density value compared to Comparative Example 2. Therefore, it can be seen that for the dielectric layer including gallium (Ga) and the peak intensity ratio (I Ba / I Ga ) in the range of 1.0 to 5.0, the low temperature sintering effect of the dielectric layer is excellent compared with Comparative Example 2 in which gallium (Ga) is not included in the dielectric layer.

[0211] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A multilayer ceramic capacitor comprising: a capacitor body including a dielectric layer and an inner electrode layer; as well as An external electrode, disposed outside the capacitor body, wherein the dielectric layer comprises a barium titanate-based main component containing Ba and Ti and Ga, and The peak intensity ratio I of Ba / Ga obtained by TEM-EDS analysis of a region from the interface between the dielectric layer and the internal electrode layer to the surface of the dielectric layer at a depth of 10 nm to 500 nm is shown in FIG. Ba / I Ga 1.0 to 5.

0.

2. The multilayer ceramic capacitor according to claim 1, wherein: The peak intensity ratio of Ti / Ga obtained by TEM-EDS analysis of the region is Ti / I Ga 1.0 to 5.

0.

3. The multilayer ceramic capacitor of claim 1, wherein: The dielectric layer further includes a secondary component, and The subcomponents include Al, Si, Mg, V, Mn or a combination thereof.

4. The multilayer ceramic capacitor of claim 3, wherein: The subcomponent includes Al, and The peak intensity ratio of Al / Ga obtained by TEM-EDS analysis of the region is Al / I Ga 1.0 to 5.

0.

5. The multilayer ceramic capacitor of claim 3, wherein: The subcomponent includes Si, and The peak intensity ratio of Si / Ga obtained by TEM-EDS analysis of the region is Si / I Ga 1.0 to 5.

0.

6. The multilayer ceramic capacitor of claim 3, wherein: The secondary component includes Mg, and The peak intensity ratio of Mg / Ga obtained by TEM-EDS analysis of the region is Mg / I Ga 0.4 to 2.

0.

7. The multilayer ceramic capacitor of claim 3, wherein: Ga exists as a second phase combined with the above-mentioned subcomponents.

8. The multilayer ceramic capacitor of claim 1, wherein: Ga is included in an amount of 0.01 parts by mol to 10 parts by mol based on 100 parts by mol of the barium titanate-based main component.

9. The multilayer ceramic capacitor of claim 1, wherein: The dielectric layer includes a plurality of grains and grain boundaries between adjacent grains among the plurality of grains, and Ga exists at the grain boundaries.

10. The multilayer ceramic capacitor of claim 9, wherein: A molar ratio of Ga present in the grain boundaries to Ga present in the crystal grains is 5:1 to 50:

1.

11. The multilayer ceramic capacitor of claim 1, wherein: Ga is formed from a Ga complex.

12. The multilayer ceramic capacitor of claim 1, wherein: The capacitor body is formed by sintering at a temperature of 1000°C to 1200°C.

13. The multilayer ceramic capacitor of claim 1, wherein: The capacitor body has an effective portion in which the dielectric layers and the internal electrode layers are alternately arranged, In the active portion, the internal electrode connectivity defined by the following formula 1 is 80% to 100%, (Formula 1) Internal electrode connectivity (%)=(total length of connected portions excluding disconnected portions in the plurality of internal electrode layers / total length of the plurality of internal electrode layers)×100.

14. The multilayer ceramic capacitor of claim 13, wherein: The capacitor body further has side edge portions provided on both side end portions of the effective portion that are opposite to each other in the width direction, and In the area near the side edge portion, the internal electrode connectivity defined by Formula 1 is 80% to 100%, and the area near the side edge portion is defined as an area extending from the boundary between the effective portion and the side edge portion into the effective portion to a depth surface corresponding to 5% to 20% of the total length of the effective portion in the width direction.

15. A method of manufacturing a multilayer ceramic capacitor, comprising: A dielectric slurry is prepared by mixing a barium titanate-based main component powder and a Ga complex; preparing a dielectric green sheet using the dielectric slurry, and forming a conductive paste layer on a surface of the dielectric green sheet; preparing a dielectric green sheet stack structure by stacking the dielectric green sheets on which the conductive paste layers are formed; preparing a capacitor body including a dielectric layer and an internal electrode layer by sintering the dielectric green sheet stack structure; and forming external electrodes on the outer surface of the capacitor body, wherein the dielectric layer comprises a barium titanate-based main component containing Ba and Ti and Ga, and The peak intensity ratio I of Ba / Ga obtained by TEM-EDS analysis of a region from the interface between the dielectric layer and the internal electrode layer to the surface of the dielectric layer at a depth of 10 nm to 500 nm is shown in FIG. Ba / I Ga 1.0 to 5.

0.

16. The method for manufacturing a multilayer ceramic capacitor according to claim 15, wherein: The Ga complex includes gallium carboxylate in ionic form.

17. The method for manufacturing a multilayer ceramic capacitor according to claim 15, wherein: The Ga complex is mixed in an amount of 0.01 parts by mol to 10 parts by mol based on 100 parts by mol of the barium titanate-based main component powder.

18. The method of manufacturing a multilayer ceramic capacitor according to claim 15, wherein: The dielectric slurry is prepared by further mixing sub-component powders including Al2O3, SiO2, MgO, V2O5, MnO2, or a combination thereof.

19. The method for manufacturing a multilayer ceramic capacitor according to claim 18, wherein: Based on 100 parts by mole of the barium titanate-based main component powder, Al2O3 is mixed in an amount of 0.01 to 5 mol parts, SiO2 is mixed in an amount of 0.01 to 5 mol parts, MgO is mixed in an amount of 0.01 to 5 parts by mole, V2O5 is mixed in an amount of 0.01 to 5 parts by mole, and MnO2 is mixed in an amount of 0.01 parts by mol to 5 parts by mol.

20. The method for manufacturing a multilayer ceramic capacitor according to claim 15, wherein: The sintering is performed at a temperature of 1000°C to 1200°C.

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